A Digital Bang-Bang Clock and Data Recovery Circuit Combined with ADC-Based Wireline Receiver

Abstract

With the great increases in data transmission rate requirements, analog-to-digital converter (ADC)-based wireline receivers have received more and more attention due to their flexible and powerful equalization capabilities. Considering power consumption, baud-rate Mueller–Muller clock and data recovery (MM-CDR) circuits are widely used in ADC-based wireline receivers since MM-CDR circuits only need one sample signal per unit interval (UI). However, MM-CDR circuits need to set an additional Vref voltage to match the size of the main tap of the channel. If the Vref matching is not appropriate or the signal quality is good as a square wave, MM-CDR circuits cannot accurately lock on to a certain phase and instead drift within a phase range. Therefore, MM-CDR circuits are not as robust and stable as oversampled CDR circuits. In this study, a digital bang-bang clock and data recovery (DBB-CDR) circuit combined with an ADC-based wireline receiver was proposed. The DBB-CDR circuit could eliminate various unstable factors of MM-CDR circuits and achieve fast and robust phase locking without excessively increasing power consumption. A model of the DBB-CDR circuit was combined with an actual 32 Gb/s ADC-based wireline receiver, which was implemented in 28 nm CMOS technology to analyze the performance of the DBB-CDR circuit. The simulation results showed that the DBB-CDR circuit could achieve 0.42 UIpp JTOL@10MHz, and that the minimum JTOL value was 0.362 UIpp under a 0.04 UI variance of Gaussian jitter. The area and power consumption of the DBB-CDR circuit were only 64 μm² and 0.02 mW, respectively; and the DBB-CDR circuit could also obtain very stable phase locking and demonstrated a fast frequency offset tracking ability when there was a frequency offset.

1. Introduction

As the data transmission rates of wireline communication links have increased, channel impairments (such as skin effects, dielectric loss, fiber dispersion, reflection and crosstalk) have become more apparent, and traditional slicer-based receivers do not have the ability to recover data with low bit error rates under such high-loss channels. Thus, more attention has been devoted to analog-to-digital converter (ADC)-based wireline receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) and more powerful equalization [1,2,3]. Utilizing this back-end DSP enables complex digital equalization and higher bandwidth modulation schemes while significantly reducing process, voltage and temperature sensitivity. In addition, ADC-based receivers converting signals into the digital domain for the processing and updating of CMOS process technology nodes can be very convenient to reduce area and save power consumption, which greatly saves design cycles compared with slicer-based receivers.

The sampling clocks of ADC-based receivers are adjusted using clock and data recovery (CDR) circuits. Baud-rate CDR circuits have been increasingly applied in ADC-based high-speed wireline receivers that benefit from collecting one sample per unit interval (UI), so the rate requirements of the sampling clocks are halved compared with those of oversampled CDR circuits [4,5]. Baud-rate CDR circuits usually adopt a Mueller–Muller phase detector (MMPD) to determine the best sampling phase of the ADC clocks [6,7,8]. The convergence goal of traditional Mueller–Muller clock and data recovery (MM-CDR) circuits is to make the size of the pre-cursor equal to the size of the post-cursor, which requires a reference Vref level to generate the up/down signal. However, MM-CDR circuits face the problem of unstable convergence when the Vref matching is not appropriate, or the signal quality is good as a square wave [9,10]. Liu et al. [11] proposed a linear model for a Mueller–Muller CDR circuit and used a drift bit width to characterize the influence of the reference Vref level, which showed the phase drift that occurred when the Vref was not set properly through simulations. In order to solve the problem of phase locking not being unique, various structures have been invented. For example, in [12], Francese et al. modified the lock point of an MM-CDR circuit to the unequalized pulse response. In [13], Choi et al. adopted a weight-adjusting sign–sign MM-CDR circuit with a maximum-eye tracking algorithm to make a CDR circuit lock on to the optimal phase that maximized the eye height. However, the power consumption of the additional structure deviated from the original intention of using MM-CDR circuits in ADC-based wireline receivers, which was to reduce power consumption. Therefore, when MM-CDR circuits do not significantly reduce power consumption, the scheme of adopting MM-CDR circuits in ADC-based wireline receivers is not so attractive due to the additional problems that are specific to MMPD, including the requirement for a reasonable Vref under different signal amplitudes and the lack of a linearized MMPD model at the design stage [14].

In this work, we added a partial oversampling system to sample the edges of the signal by interpolating an intermediate phase clock through a time interpolator [15,16]. This meant that a digital bang-bang phase detector (DBBPD) could be used for phase locking in an ADC-based wireline receiver without excessively increasing its power consumption. The DBBPD could effectively lock on to the optimal phase, regardless of the magnitude of the signal amplitude. Using a DBBPD also helped us to analyze the performance of the overall CDR circuit at the design stage, unlike MM-CDR circuits, which cannot be analyzed at this stage because of the lack of linearized MMPD model. The rest of this article is organized as follows. Section 2 delineates the working principles of the MMPD and DBBPD. Section 3 elaborates on the specific circuit structure and clock generation scheme of our digital bang-bang clock and data recovery (DBB-CDR) circuit with an ADC-based wireline receiver. Section 4 details the small-signal DBB-CDR model followed by Section 5, which presents the simulation results of the DBB-CDR circuit. Finally, Section 6 summarizes our conclusions.

2. The Working Principles of the MMPD and DBBPD

2.1. The Working Principles of the MMPD

The MMPD infers channel responses from baud-rate samples of the received data. The adaptation aligned the sampling clock such that the pre-cursor h₋₁ was equal to the post-cursor h₁ in the pulse response, as shown in Figure 1.

The timing function f(τ) defined in [6] is expressed as:

$$f\left(\tau \right)=\frac{1}{2}\left(h_1-h_{-1}\right)$$

(1)

where h₁ and h₋₁ represent the amplitudes of the post-cursor and pre-cursor, respectively. Algorithms choose their steady-state timing in such a way as to yield equal values for h₁ and h₋₁. If h₁ is greater than h₋₁, the sampling time of the CDR circuit is early. Similarly, if h₁ is less than h₋₁, the sampling time of the CDR circuit is late.

The generation of the MMPD timing estimator z_k in binary signaling format defined in [6] is shown in Figure 2a and is expressed as:

$$z_k=\frac{1}{2}\left(x_k{d}_{k-1}-x_{k-1}{d}_k\right)$$

(2)

$$E\left\{z_k\right\}=\frac{1}{2}\left(h_1-h_{-1}\right)=f\left(\tau \right)$$

(3)

where x_k is the received sample and d_k is the signal decision value (d_k can only have a value of ±1).

Thus, the results of the timing function f(τ) are transformed into the expectation of the timing estimator z_k. The analog samples x_k are converted into digital signals s_k after the ADC. The comparison between x_k and ±Vref can generate error signal e_k. The values of d_k, e_k and s_k are shown in Figure 2b. According to the results of d_k and e_k, the expression of s_k can be obtained as:

$$s_k=d_k\left(e_k+1\right)/2$$

(4)

Thus, the MMPD timing estimator z_k can be converted into:

$$\begin{array}{ll}{z}_k& =\left(x_k{d}_{k-1}-x_{k-1}{d}_k\right)/2\\ & ~\left(s_k{d}_{k-1}-s_{k-1}{d}_k\right)/2\\ & z_k=d_k{d}_{k-1}\left(e_k-e_{k-1}\right)/4\end{array}$$

(5)

Equation (5) illustrates how a phase error is detected based on the signs of two consecutive samples and the signs of two consecutive errors. A waveform diagram of this phase error detection is shown in Figure 3 and the phase error values are listed in

Table 1. An MMPD truth table.

dk	dk−1	ek	ek−1	Phase Error
1	−1	1	−1	Late
−1	1	1	−1	Late
1	−1	−1	1	Early
−1	1	−1	1	Early
All Other Cases				Hold

. It can be clearly seen from Figure 3 that if Vref is not set properly, it affects the value of e_k, which, in turn, affects the up/down signal generated by the MMPD.

2.2. The Working Principles of BBPD

The BBPD is an oversampled phase detector used in most CDR implementations, which needs to obtain one more edge data between consecutive signal data [17,18,19]. Figure 4 shows the judgment principle of a BBPD and the truth table is shown in

Table 2. A BBPD truth table.

Data1	Edge1	Data2	Phase Error
0	1	1	Late
0	0	1	Early
1	1	0	Early
1	0	0	Late
All Other Cases			Hold

. Using three samples taken on three consecutive clock edges (S1, S2 and S3), the bang-bang phase detector can determine whether there is a data transition and whether the clock is leading or lagging the data. In the absence of data conversion, the three sampled data are equal without any changes. If the last edge of the clock is leading, the value of the last sample clock (S3) is opposite to the previous two samples. Conversely, if the clock is lagging, the last two samples (S2 and S3) are equal and opposite to the first sample (S1). Therefore, S1⊕S2 and S2⊕S3 provide early and late information about sampling clocks:

(a)

If S1⊕S2 is high and S2⊕S3 is low, the clock is late;

(b)

If S1⊕S2 is low and S2⊕S3 is high, the clock is early;

(c)

If S1⊕S2 = S2⊕S3, the data are not converted.

CDR circuits with a BBPD will lock on data crossing points and assume that the optimal data sampling point is a half-bit period away. According to the above detection principle, a block diagram of the implementation of a bang-bang phase detector is shown in Figure 5a and the waveform of a bang-bang phase detector is shown in Figure 5b.

When we design our CDR circuit, we need to analyze its performance. A key step is to linearize the nonlinear phase detector [20,21]. Both the MMPD and BBPD are nonlinear phase detectors, but since the judgment of the MMPD is affected by signal amplitude and the set value of Vref, its linearization is more complicated. The BBPD is not affected by signal amplitude, so its linearization model can be easily obtained by analyzing the relationships between its judgment responses and the size of the signal jitter, which was convenient for us to analyze the performance of our CDR circuit [22,23,24]. For a 50% transition density, the BBPD gain can be expressed as:

$$K_{PD}=\frac{1}{\sigma \sqrt{12}} \left(Gaussian jitter\right)$$

(6)

The BBPD is an efficient and simple two-times oversampling system that doubles the number of clock phases and front-end samplers in CDR circuits. It is precise because double oversampling is too expensive for ADC-based receiver hardware, so the BBPD is not as popular as baud-rate PD in an ADC-based wireline receiver. However, in order not to increase power consumption too much and simultaneously avoid the instability problem of the MMPD, the BBPD could also be very promising in an ADC-based receiver.

3. The Proposed DBB-CDR Circuit with an ADC-Based Wireline Receiver

The 32 Gb/s ADC-based receiver used in this work utilized a continuous-time linear equalizer (CTLE), 4 × 8 time-interleaved successive comparison register (TI-SAR) ADCs, four track and hold (T&H) circuits with eight sub-ADCs per track/hold. The 32 TI-SAR ADCs converted the signals into the digital domain and sent them to the DSP. The DSP performed ADC calibration, feedforward equalization (FFE) and decision feedback equalization (DFE). A combination of 1-tap DFE and 8-tap FFE was used in the DSP and the equalized results were discriminated and transmitted. The DSP also sent the signals to the clock data recovery circuit and then the CDR circuit adjusted the sampling phase of the track and hold circuits according to the obtained information. A block diagram of the whole 32 Gb/s ADC-based receiver is shown in Figure 6.

3.1. The Structure of the DBB-CDR Circuit

When ADC-based receivers are used in high-speed wireline transceivers, digital CDR circuits offer a more attractive solution compared with an analog implementation. Compared with analog CDR circuits, digital CDR circuits have many advantages [25]. MM-CDR circuits are the most common type of digital CDR circuit used in ADC-based wireline receivers, which include a Mueller–Muller phase detector, a decimation block, a frequency integrator, a phase integrator and a phase interpolator. When using an MMPD, the digital signal processing needs to send parallel sign–sign data and error-direction information to the MMPD.

However, we adopted a partial oversampling system for the ADC-based receiver, as shown in Figure 6. We added a sub-ADC 1.5 to the partial oversampling system (between sub-ADC 1 and sub-ADC 2) to sample the edge information, so the DSP only needed to send the Data<1>, Data<1.5> and Data<2> results to the CDR circuit (as judged from sub-ADC 1, sub-ADC 1.5 and sub-ADC 2) for the CDR circuit to adopt a more stable DBB-CDR structure. This also meant that the circuit did not require a summing block to decimate the input signals from the DSP.

The DBB-CDR circuit included a digital bang-bang phase detector, a frequency integrator, a phase integrator and a phase interpolator, as shown in Figure 7. The digital signal processing received the ADC data and equalized them adaptively, based on the sign–sign least mean square (SS-LMS) algorithm. Then, the sign–sign Data<1>, Data<1.5> and Data<2> data were sent to the DBBPD. The DBBPD generated up/down signals according to the Data<1>, Data<1.5> and Data<2> results. The proportional path through K_P combined with the integral path through K_I filtered the phase detector decisions. The phase interpolator used a multi-bit digital control bus to control the phases of the ADC sampling clocks.

3.2. The Clock Scheme of the Proposed DBB-CDR Circuit in an ADC-Based Wireline Receiver

In our 32 Gb/s ADC-based receiver, we adopted 4 × 8 hierarchical sampling for the 4 × 8 time-interleaved successive comparison register ADC structure shown in Figure 6. The first stage used a four-phase 8 GHz clock to perform four-phase 8 GS/s sampling and the second stage used an eight-phase 1 GHz clock to perform eight-phase 1 GS/s sampling for each phase of the first stage. Using this method, we could obtain a sampling time of 125 ps for each sub-ADC, with the four sub-ADC samples signaling simultaneously at each instant.

The clock requirements for the two-stage hierarchical sampling were a four-phase 8 GHz clock and an eight-phase clock that divided each four-phase 8 GHz clock by eight. First, the four-phase 8 GHz clock in the design was generated from an 8 GHz differential clock using the injection locking technique. The generated clock also went through duty cycle detection (DCD)/quadrature error detection (QED) circuits and duty cycle calibration (DCC)/quadrature error calibration (QEC) circuits to generate a high-quality four-phase clock: CKI_8G, CKQ_8G, CKIB_8G and CKQB_8G. At the same time, before the four-phase clocks reached the four track and hold circuits, the time skew deviation between the sampling clocks was adjusted again through the delay cell.

After obtaining the four-phase clock CKI_8G, CKQ_8G, CKIB_8G and CKQB_8G, we needed to divide the four-phase 8 GHz clock by eight to generate eight-phase clocks and then send them to the eight sub-ADCs for each lane. We used a ring shift register circuit to complete this task, as shown in Figure 8.

Considering that the partial oversampling system that we added required an edge sampling clock, we needed to generate an edge sampling clock from the existing eight-phase clock. From the perspective of low power consumption, we added a small interpolator circuit in the ADC T/H clock buffer, as shown in Figure 9. The interpolator adopted a CMOS structure to interpolate the cki<1> and ckq<1> clocks and the intermediate phase clock CK<1.5>. The CKI<1>, CK<1.5> and CKQ<1> clocks were used for sub-ADC 1, sub-ADC 1.5 and sub-ADC 2, respectively. The DSP generated Data<1>, Data<1.5> and Data<2> and sent them to the DBB-CDR circuit to adjust the optimal sampling phase. A timing diagram of the overall ADC sampling clock, including the edge sampling clock CK<1.5>, is shown in Figure 10.

4. Small-Signal DBB-CDR Model

An intuitive understanding of the performance of a CDR circuit is whether it can provide an optimal sampling phase for an ADC to allow the wireline transceiver system to achieve the lowest bit error rate (BER). In the testing stage, we could obtain the performance of the CDR circuit using the BER results. However, in the simulations, it was hard for us to verify the communication protocol requirements of a BER of 10⁻¹² or even 10⁻¹⁵. Thus, we could not verify the performance of the CDR circuit via time-domain simulations during the design stage. Therefore, during the design stage, we could only analyze the performance of the CDR circuit by linearizing it. However, the performance of MM-CDR circuits is hard to analyze because of the lack of a linearized MMPD model, so most studies have only focused on the application of MM-CDR circuits without systematic analysis. Different from MM-CDR circuits, it is easy to perform linearization analysis on DBB-CDR circuits because the linearization of the BBPD has been well analyzed.

In order to analyze the performance of our DBB-CDR circuit, it needed to be linearly modeled and then we could proceed to analyzing its jitter transfer function (JTF) and jitter tolerance (JTOL). The linearized model that was equivalent to the architecture in Figure 7 is shown in Figure 11.

In the figure, K_PD is the gain of the DBBPD, K_P is the gain of the proportional path, K_I is the gain of the integral path, K_PI is the gain of the phase interpolator and z^−N is the delay of the digital CDR circuit. These parameters are listed in

Table 3. The parameters of the linearized DBB-CDR model DBB-CDR.

Parameter	Value
KPD	14.4 per UI when σ = 0.02UI 9.6 per UI when σ = 0.03UI 7.2 per UI when σ = 0.04UI
KP	2−7
KI	2−18
KPI	1 UI/25 bit
N	5

and are described in the following content.

The values of K_PD were calculated according to Equation (6) under different variance values σ of Gaussian jitter. We assumed that σ equaled to 0.04 UI, 0.03 UI and 0.02 UI, to demonstrate the circuit performance under different Gaussian jitter values.

The values of K_P and K_I could be set within certain ranges to meet the requirements of the CDR loop circuit characteristics, such as the bandwidth of the CDR circuit and the range of the frequency deviation tracking.

The element K_PI corresponded to the resolution of the phase interpolator in UI per bit. Considering the performance and complexity of the circuit, we chose a phase interpolator resolution of 5 bits.

The performance of the CDR circuit under consideration was mainly analyzed in terms of jitter transfer function and jitter tolerance. The circuit gain of this linearized model could be analyzed as follows:

$$L\left(z^{-1}\right)=\frac{{\mathit{\phi }}_{OUT}}{{\mathit{\phi }}_E}=\frac{K_{PD}{K}_{PI}}{1-z^{-1}}\left(K_P+\frac{K_I}{1-z^{-1}}\right)z^{-N}$$

(7)

The expression of the jitter transfer function was:

$$H\left(e^{-j\omega }\right)=\frac{{\mathit{\phi }}_{OUT}}{{\mathit{\phi }}_{IN}}=\frac{L\left(e^{-j\omega }\right)}{1+L\left(e^{-j\omega }\right)}$$

(8)

Jitter tolerance is required under a specific bit error rate requirement. The CDR circuit in this study needed to meet the JESD204C protocol, which has a bit error rate requirement of 10⁻¹⁵. Thus, the JTOL expression was:

$$JT\left(e^{-j\omega }\right)=\left(\frac{{\mathit{\phi }}_{IN}}{{\mathit{\phi }}_E}\right)·\left(1-\frac{15.88\sigma }{T_{UI}}\right)=\left(1+L\left(e^{-j\omega }\right)\right)·\left(1-\frac{15.88\sigma }{T_{UI}}\right)$$

(9)

where T_UI is the data cycle and its value is 31.25 ps.

5. Simulation Results

To verify the effectiveness of our proposed DBB-CDR circuit, we implemented a complete 32 Gb/s ADC-based receiver using 28 nm CMOS technology. The ADC-based receiver circuit included a T-coil inductor, injection lock/divider, DCD/QED, DCC/QEC, phase interpolator, CTLE, T/H, delay cell, 32-way time-interleaved SAR ADC, and an additional sub-ADC and time interpolator, implemented using analog circuits. The data demux, DSP, DBB-CDR and skew calibration logic were implemented in the digital domain. The whole 32 Gb/s ADC-based receiver, with the exception of the DSP and DBB-CDR circuit, occupied an area of 0.34 mm × 0.8 mm. According to the simulation results, we determined that the power consumption of the whole 32 Gb/s ADC-based receiver was 233 mW.

We set different frequency offsets to examine the frequency offset tracking ability of the DBB-CDR circuit using AMS digital-analog hybrid simulations. Figure 12a,b show plots of the tracking ability of the DBB-CDR circuit under a 0 ppm and −448 ppm frequency offset, respectively. As can be seen from Figure 12a, when there was no frequency offset, the DBB-CDR circuit converged to the most suitable phase after about 500 ns. When the phase converged, the phase tracking speed was stable around 0, and the error number of the data symbols transmitted throughout the entire system no longer increased. As can be seen from Figure 12b, when there was a −448 ppm frequency offset, the phase tracking speed of DBB-CDR gradually accelerated, and the phase of the DBB-CDR circuit also accelerated between 0 and 127, until the speed of the phase movement caught up with the signal frequency offset. Once the tracking speed of the DBB-CDR circuit gradually stabilized to about −56, the speed of the phase movement could maintain a relatively constant positional relationship between the clock and the signal. At this time, the error number of the data symbols in the whole system also remained unchanged, which reflected the effective frequency offset tracking performance of the DBB-CDR circuit.

According to our linearization analysis of DBBPD and the linearized DBB-CDR model in Section 4, we performed jitter transfer function and jitter tolerance simulations on the DBB-CDR circuit using Equations (8) and (9), and the parameter values were selected from those in Table 3. In order to compare the performance of our DBB-CDR circuit to that of an original MM-CDR circuit, we set the same gains for the MMPD as for the DBBPD. In addition, the other parameters of a MM-CDR circuit were also selected to be consistent with those of the DBB-CDR circuit and only the gain of a decimation module needed to be added.

Figure 13a shows the plots of the jitter transfer function performance of the DBB-CDR and MM-CDR circuits under a 0.04 UI, 0.03 UI and 0.02 UI variance of Gaussian jitter. Different Gaussian jitter deviations were reflected by different PD gains. It can be seen in the figure that the greater the PD gain, the wider the bandwidth of the jitter transfer function and the smaller the jitter peaks. It can also be observed that the bandwidths of the DBB-CDR circuit were 11.39, 14.48 and 20.62 MHz, and the corresponding bandwidths of the MM-CDR circuit were 2.86, 4.06 and 7.08 MHz. Thus, the DBB-CDR circuit could obtain a higher bandwidth under the same phase detection gain compared with the MM-CDR circuit. As can be seen from Figure 13b, the DBB-CDR and MM-CDR circuits readily met the JESD204C jitter tolerance limit. Whether σ was equal to 0.04 UI, 0.03 UI or 0.02 UI, the higher the PD gain, the greater the JTOL margin. Although the JTOL margins of the DBB-CDR and MM-CDR circuits were similar at high frequencies under the same phase detection gain, the JTOL performance of the DBB-CDR circuit was much better than that of the MM-CDR circuit at low frequencies.

Table 4. A performance comparison between state-of-the-art wireline receiver.

Reference	[14]	[19]	[25]	This Work
Technology	10 nm CMOS	65 nm CMOS	7 nm CMOS	28 nm CMOS
RX Architecture	ADC-based	Slicer-based	ADC-based	ADC-based
CDR Architecture	MM-CDR	BB-CDR	MM-CDR	DBB-CDR
Modulation	PAM4	NRZ	PAM4	NRZ
Data Rate (Gb/s)	56	40	1–60	32
Supply (V)	0.75/0.85/1.2	1.2	0.75/0.9	0.9/1.4
JTOL@10MHz (UIpp)	0.072	0.27	0.18	0.42
Min. JTOL (UIpp)	0.07	0.21	0.14	0.362
Area (mm2)	0.72	1.92	0.468	0.272
Power (mW)	226.5	225	244	233

summarizes a performance comparison between our ADC-based wireline receiver circuit and other previously published wireline receivers. Our work achieved an excellent JTOL performance, which showed the benefits of our DBB-CDR circuit. Since we added a low dropout regulator (LDO) to improve the stability of the power supply, the power consumption of our circuits was not greatly reduced, but the compact and reasonable layout still afforded an excellent area advantage.

Lastly, in order to show that our proposed DBB-CDR circuit could optimize the area and power consumption performance, we also performed a back-end synthesis for the DBB-CDR and MM-CDR circuits using the 28 nm technology. Our performance comparison results are shown in

Table 5. The performance comparison between the DBB-CDR and MM-CDR circuits.

Performance	DBB-CDR	MM-CDR
Stability	High	Low
Robustness	High	Low
Signal Amplitude	Not Affected	Affected
Power (mW)	0.02 2.02 *	0.6442
Area (μm2)	64 1114 *	3711

* Including the additional sub-ADC and the time interpolator.

. As can be seen from Table 5, since the structure of DBBPD is simpler than that of MMPD, and our DBB-CDR circuit did not require a decimation module, the area and power consumption of the DBB-CDR circuit were only 64 μm² and 0.02 mW, respectively, which were much smaller than those of the MM-CDR circuit. Considering that an additional sub-ADC and a time interpolator were required for the DBB-CDR circuit, the overall power consumption of the DBB-CDR circuit did not increase too much compared with that of the MM-CDR circuit, but the DBB-CDR structure was not affected by the input signal amplitude, which was easier to set up. In addition, the DBB-CDR structure was more stable and robust than the MM-CDR structure, demonstrating that DBB-CDR circuits could offer a new solution for ADC-based wireline receivers.

6. Conclusions

In this paper, we proposed a digital bang-bang clock and data recovery circuit combined with an ADC-based wireline receiver. Our digital bang-bang clock and data recovery circuit adopted a partial oversampling system, which only needed one extra sub-ADC and a time interpolator. The DBB-CDR circuit combined with a 32 Gb/s ADC-based wireline receiver was implemented using 28 nm CMOS technology. It achieved 0.42 UIpp JTOL@10MHz and the minimum JTOL value was 0.362 UIpp under 0.04 UI variance of Gaussian jitter. The whole 32 Gb/s ADC-based receiver, with the exception of the DSP, occupied an area of 0.34 mm × 0.8 mm and consumed 233 mW of power. Considering the structure of DBBPD is simpler than that of MMPD, the adopted DBB-CDR circuit with the ADC-based wireline receiver did not excessively increase power consumption. Overall, the excellent performance of the circuit in terms of stability, robustness, signal amplitude insensitivity, etc., demonstrated that DBB-CDR circuits could offer a new solution for ADC-based wireline receivers.