Development and Analysis of a Novel High-Gain CUK Converter Using Voltage-Multiplier Units

Abstract

High conversion gain is often required for the grid integration of renewable energy resources such as PV, fuel cells, and wind. It is desired that the stress across switches is lower when higher voltage gain is attained. Similarly, it is also preferred that the converter can achieve high voltage gain without operating at higher duty cycle values. This article presents a novel high-gain CUK converter (HGCC) that uses voltage-multiplier units. The HGCC is a combination of a modified CUK converter and voltage-multiplier units (VMUs). The converter utilizes a boost converter as an input to the modified CUK converter, resulting in an increase in the gain value. The voltage gain of HGCC is increased further by placing VMUs. Based on its overall design, the HGCC inherits various advantages of the CUK converter, such as continuous input and output current, resulting in low input and output current ripples. A mathematical model is developed for the HGCC, which helps calculate its voltage gain at different stages. The model is developed considering ideal elements without conduction and switching losses. Generalized equations for output voltage and gain are derived for $n$ level converter. A simulation study was performed in MATLAB/Simulink that further highlights the advantages of the HGCC. Voltage stresses across different components and the switching of MOSFET and diodes are studied in simulations. An experimental setup is established for hardware prototyping of the converter and validation with the simulation and Mathematical models.

1. Introduction

Renewable energy is clean, environmentally friendly, and sustainable, due to which its utilization has been increasing rapidly over the past few decades [1,2,3]. Recently, renewable energy has become the focal point of research due to its numerous advantages over conventional energy sources. Clean energy sources do not produce air and water pollution, which results in improved public health. To reduce greenhouse gases emission and mitigate climatic changes, power systems around the world are shifting towards the integration of renewable sources [4,5,6]. However, certain challenges need to be addressed while integrating renewable energy resources into the grid. The output of some renewable energy technologies, such as PV and wind turbines, is affected by changes in environmental conditions. Moreover, the output voltage of certain technologies, such as photovoltaic (PV) and Fuel Cells (FCs), is quite low. So, a significant challenge in renewable applications and integration into the grid is the need to increase the low-output voltage of these energy sources to a stable, higher desired value [7,8,9]. Maximum power point tracking (MPPT) is used to extract maximum power from renewable sources under different environmental conditions. To achieve the desired voltage level value, DC-DC converters are utilized for MPPT applications. These converters can change the voltage from one level to another depending on the topology and the duty cycle at which they are operated. In the context of MPPT, these converters help in increasing the efficiency of renewable energy sources [10,11,12,13]. To harness wind energy efficiently, wind energy conversion systems (WECS) also use MPPT techniques that consist of different types of DC-DC converters [14,15,16].

Conventional DC-DC converters serve to change the voltage levels from one value to another, but they exhibit certain disadvantages. One of the drawbacks of these converters is that they do not provide the higher gains that are mostly needed for renewable energy applications. Therefore, it is not feasible to use them alongside renewable sources for high-voltage applications. For instance, a voltage gain value of 10 in a 90–95% duty cycle can be achieved for the boost converter, which is considered insufficient for high-voltage applications [17]. Another issue regarding the boost converter is the higher voltage stress across the switch, which is equal to the output voltage. This is because the switch is directly connected across the output during the switch-off interval. The huge stress across the switch also leads to a decrease in efficiency. In terms of efficiency, most of the devices use a single-inductor multiple-output (SIMO) switching converter, which can generate multiple voltage levels with only one inductor [18,19]. The Buck–Boost converter, which is another conventional converter, provides a maximum voltage gain of 9 in a 90% duty cycle, which is even lower than that of the boost converter. In this case, the voltage stress across the switch equals the sum of the input and output voltages. Both the above converters have high input ripple current that deteriorates the performance and lifetime of the converter and affects the overall system. DC-to-DC converters with continuous input current show better dynamic performance [20]. Besides this, it is also observed that the maximum voltage gains of the above converters occur at high duty cycles where the efficiency of the converters is lower, and the performance and lifetime of the converters are reduced [21,22,23]. Due to the above-mentioned reasons, conventional converters are generally not suitable for high-voltage applications.

There are also interleaved DC-DC converters that are used in various applications [24,25]. These converters generally offer low voltage gain. Other commonly used DC-DC converters topologies are impedance-sourced converters, also referred to as Z-sourced and quasi-Z-sourced DC-DC converters [26,27]. These converters generally offer low voltage gain, high voltage stress across the switches, and discontinuous input current. Other converters, including SEPIC, ZETA, and CUK, offer solutions to some of the above-mentioned problems, such as input ripple current [28,29]. However, the voltage gain of these converters is still lower, due to which they are not suitable for high-voltage applications. Quadratic Boost Converter (QBC) addresses some of the above issues, but it has high voltage stress across the main switch [30]. Another solution is the Modified High-Voltage Cuk converter, which offers higher gain at high duty cycles [31]. Converters with coupled inductors are also used to achieve high voltage gain value [32,33], but the problem with these converters is inductor leakage losses. Switched-capacitor converters can achieve high power density but suffer from problems such as reduced efficiency, complexity, and considerable input current ripple depending upon the type of converter topology [34,35,36]. Various traditional converters extended by combining them with the Cockcroft–Walton voltage multiplier to increase gain are discussed in [37]. To address the aforementioned problems in the existing topologies of DC-DC converters, a novel topology of a high-gain DC-DC converter is proposed by modifying a conventional CUK converter to achieve high gain. The HGCC also inherits the advantages of the conventional CUK converter such as continuous input and output currents. VMUs are integrated with the modified converter. The advantage of adding these VMUs is that they further increase the gain of the system without making changes to the main circuit. The new topology uses a conventional boost converter at the input stage that also helps to increase the voltage gain. The main contributions of this research work are given as follows.

• A new high-gain DC-DC converter topology HGCC was designed and experimentally tested, which is not found in the available literature.
• A mathematical model of a novel HGCC was developed and analyzed that helps in derivations and calculations of voltages at different stages of the proposed topology. Furthermore, a simulation study was performed that further gives insights into the switching and working of the converter. An experimental setup was established that consisted of a newly designed HGCC.
• It is observed that the voltage stress across the MOSFET is much lower compared to the output voltage, especially for high-output voltages. It is seen that the voltage gain can be increased by adding VMUs without disturbing the main circuit. Moreover, higher voltage gain can be achieved even without extreme duty cycles, which results in better performance and longer lifetimes of the novel converter topology.

2. Analytical Model of Proposed Converter

The HGCC is a CUK-based modified converter with VMUs integrated into its structure. Each VMU has two diodes and two capacitors that increase the gain of the converter. Adding $n$ number of VMUs increases the gain by $n$ times. For the simplifications of the analysis, the following assumptions have been made:

• All the capacitors and inductors are large enough so that the ripples in voltages across the capacitors and currents through the inductors can be ignored for the calculation of the voltage gain.
• Semiconductor devices, including MOSFET, and diodes are ideal.

Based on the controlled switching of the MOSFET, the operation of the HGCC is divided into two parts. During the first part, the MOSFET is switched ON; thus, this state is referred to as the ON state. The second part during which the MOSFET is switched OFF is known as the OFF state.

The modified structure uses a conventional boost converter as an input to the rest of the modified circuit. This increases the voltage gain to $-D/{\left(1-D\right)}^2$. The inductor L₃ and capacitor C₅ are added to improve the voltage gain to $-1/{\left(1-D\right)}^2$. Capacitors C₃ and C_4, along with the diodes, give a further boost to the voltage gain of the converter, making it $-2/{\left(1-D\right)}^2$. In the end, $n$ VMUs are connected to increase the total gain by $n$ times. The structure of the HGCC is given in Figure 1.

The converter operation consists of two modes, namely, the ON mode and the OFF mode. The ON mode is between 0 and DT_s, during which time MOSFET remains on. D is the duty cycle, and T_s refers to the switching time period. During this mode, the MOSFET is conducting. Diode D₁ and D₃ are reversed-biased due to capacitors C₁ and C₂, respectively. Diode D₄ is also not conducting as it is reversed-biased by capacitor C₄. Diode D₂ is forward-biased due to input voltage. Diode D₅ conducts in this state. In VMUs, D₆ is in the conduction mode, whereas D₇ is reversed-biased during this time. Inductor L₁ is charged from the input source V_in through the path as (V_in-L₁-D₂-S-V_in). Inductor L₂ is charged from the capacitor C₁ via path (C₁-L₂-S-C₁). Inductor L3 discharges from the capacitor C₅ through the path (L₃-C₅-S-L₃). Inductor L₄ is charged through capacitor C₃. The ON mode is shown in Figure 2.

The OFF mode extends from time DTs to T_s. During this time, MOSFET is not conducting. Diodes D₁, D₃, and D₄ are forward-biased, whereas D₁ and D₅ are reverse-biased and cease to conduct during this mode. In VMU, D₆ and D₈ are reverse-biased, whereas D₇ and D₉ begin to conduct during this time. Inductors L₁, L₂, and L₄ are discharged during this time, whereas inductor L₃ is charged through capacitor C₂. Figure 3 illustrates the OFF mode.

The volt-second balance principle is applied to derive the equations for voltage gain of the HGCC, which states that the average inductor voltage is zero in its steady-state, as given in Equation (1)

$$D{V}_{L\left(ON\right)}+D^{\prime }{V}_{L\left(OFF\right)}=0$$

(1)

where $D^{\prime }=1-D$. The voltage across each inductor is determined in both the ON and OFF modes. Then, the volt-second balance is applied to derive the equation for the desired voltage. For inductor L₁, the voltages in the ON and OFF modes are determined, respectively.

$$V_{L1}=V_{in}$$

(2)

$$V_{L1}=V_{in}-V_{C1}$$

(3)

where $V_{L1}$, $V_{C1}$, and $V_{in}$ is the voltage across inductor L₁, C₁, and input, respectively. Once the voltage in both states is determined, we use the volt-second balance as

$$<V_{L1}>=D{V}_{in}+D^{\prime }\left(V_{in}-V_{C1}\right)=0$$

(4)

Solving the above equation for $V_{C1}$, we obtain

$$V_{C1}=V_{in}/D^{\prime }$$

(5)

The capacitor C₁ is part of the boost portion of the HGCC, so the voltage gain across this capacitor is equal to the boost converter. For inductor L₂, the voltages in both modes are given as

$$V_{L2}=V_{C1}$$

(6)

$$V_{L2}=V_{C1}-V_{C2}$$

(7)

where $V_{L2}$ and $V_{C2}$ are the voltages across L₂ and C₂, respectively. Using the Inductor Volt-second balance and solving for voltage $V_{C2}$, we obtain

$$V_{C2}=V_{C1}/D^{\prime }$$

(8)

Inserting Equation (5) in the above equation, we obtain

$$V_{C2}=V_{in}/{D^{\prime }}^2$$

(9)

Comparing Equations (9) to (5), we can observe that voltage across C₂ is further increased by $1/D^{\prime }$ times. The voltage for inductor L₃ in the ON and OFF modes are, respectively,

$$V_{L3}=-V_{C5}$$

(10)

$$V_{L3}=V_{C2}-V_{C5}$$

(11)

where $V_{L3}$ and $V_{C5}$ are the voltages across L₃ and C₅, respectively. Using the volt-second balance and solving for V_C5, we obtain

$$V_{C5}=D^{\prime }{V}_{C2}$$

(12)

Putting Equation (9) in the above equation,

$$V_{C5}=V_{in}/D^{\prime }$$

(13)

Using another set of equations for inductor L₃ in both modes that involve $V_{C4}$, which is the voltage across capacitor C₄, we obtain

$$V_{L3}=V_{C2}-V_{C4}$$

(14)

$$V_{L3}=V_{C2}-V_{C5}$$

(15)

Using the volt-second balance and solving for $V_{C4}$,

$$V_{C4}=\left(V_{C2}-D^{\prime }{V}_{C5}\right)/D$$

(16)

Substituting Equations (9) and (13) in the above equation,

$$V_{C4}=\left(2-D\right)V_{in}/{D^{\prime }}^2$$

(17)

Another set of equations that can be used for inductor L₃ in both modes containing the term $V_{C3}$, the voltage across capacitor C₃ is

$$V_{L3}=V_{C2}-V_{C4}$$

(18)

$$V_{L3}=V_{C2}+V_{C3}-V_{C4}$$

(19)

Using the volt-second balance and solving for V_C3, we obtain

$$V_{C3}=\left(V_{C4}-V_{C2}\right)/D^{\prime }$$

(20)

Replacing values from Equations (9) and (17) in the above equation

$$V_{C3}=V_{in}/{D^{\prime }}^2$$

(21)

Similarly, we can also use the following set of equations for inductor L₃ containing the term $V_{C6}$ in ON and OFF modes, respectively:

$$V_{L3}=V_{C2}+V_{C3}-V_{C6}$$

(22)

$$V_{L3}=V_{C2}+V_{C3}-V_{C4}$$

(23)

Solving the above equations for $V_{C6}$ by using the volt-second balance, we obtain

$$V_{C6}=\left(2V_{in}/{D^{\prime }}^2-D^{\prime }{V}_{C4}\right)/D$$

(24)

Substituting the value of $V_{C4}$ from Equation (17), we obtain

$$V_{C6}=\left(3-D\right)V_{in}/{D^{\prime }}^2$$

(25)

To obtain an expression for $V_{C7}$, we use the following sets of equations for $V_{L3}$, which contain the term $V_{C7}$

$$V_{L3}=V_{C2}+V_{C3}-V_{C6}$$

(26)

$$V_{L3}=V_{C2}+V_{C3}-V_{C6}+V_{C7}$$

(27)

Using the volt-second balance to solve the above set of equations for $V_{C7}$, we obtain

$$V_{C7}=\left(1-D\right)V_{in}/{D^{\prime }}^3$$

(28)

Which reduces to

$$V_{C7}=V_{in}/{D^{\prime }}^2$$

(29)

To solve for the final output voltage, we use the following equations for inductor $V_{L4}$ containing the term $V_{C0}$ in the ON and OFF modes, respectively:

$$V_{L4}=V_{C0}-V_{C7}-V_{C4}-V_{C3}$$

(30)

$$V_{L4}=V_{C0}-V_{C7}-V_{C4}$$

(31)

To obtain the expression for output voltage, we use the volt-second balance and solve for $V_{C0}$:

$$V_{C0}=3V_{in}/{D^{\prime }}^2$$

(32)

Which can be written as

$$V_{C0}=\left(2+1\right)V_{in}/{D^{\prime }}^2$$

(33)

The above equation gives the output voltage for the 1-level multiplier. A voltage multiplier consists of two diodes and two capacitors. If there are n-level multipliers connected across the topology, as shown in Figure 4, then the general equation becomes

$$V_{C0}=\left(2+n\right)V_{in}/{D^{\prime }}^2$$

(34)

3. Simulation Results and Discussions

A circuit was developed and simulated using MATLAB/Simulink to verify the mathematical model. The results of the simulations were achieved using the parameters given in

Table 1. Simulation parameters.

Simulation Parameters	Values
Switching frequency	50 kHz
Input Voltage	3 V
Capacitors	100 μF
Inductors	10 mH
Duty Cycle	0.5

. Voltages were measured across these components to observe the voltage stresses across the MOSFET and diodes. Capacitor voltages were also measured to verify the voltage gain as obtained from the mathematical model. Finally, the output voltage across capacitor C₀ was measured to verify the total gain of the designed converter according to the mathematical model.

The results of the simulation for the input voltage of 3 V and duty cycle D = 0.5 are given in Figure 5, Figure 6 and Figure 7. Figure 5a shows the voltage across the capacitor C₁, which is the capacitor in our boost part of the converter. The voltage across capacitor C₁ is equal to 6 V, which is equal to the gain of $1/\left(1-D\right),$ which is the same as the boost converter. Figure 5b,c illustrates the voltages across C₂ and C₃, respectively. The voltage gain is further increased by an amount of $1⁄\left(1-D\right),$ so the total gain at this point equals $1/{\left(1-D\right)}^2$. Figure 5d shows the voltage across the capacitor C₄, which is further increased by a factor of $\left(2-D\right)$. Figure 5f,g shows the voltage across the capacitors C₆ and C₇, respectively. These capacitors are part of the VMUs, and they further increase the gain of the HGCC.

The output voltage taken across the capacitor C₀, which is in parallel with the load resistor, is shown in Figure 6. As the HGCC is simulated for 1-level VMU, the final output across the capacitor C₇ reaches a steady state value of 36 V, which is equal to the value obtained from the expression for output voltage in Section 2 for 1-level VMU.

Voltages across different diodes and the MOSFET during the ON and OFF modes are shown in Figure 7. These voltages depict the behavior of the voltage stresses these devices experience. Moreover, we can also observe that during the ON mode, when the MOSFET is conducting, diodes D₁, D₃, D₄, and D₇ are forward-biased, whereas diodes D₂, D₅, and D₆ are reverse-biased.

Output voltages taken across the capacitor C₀ at different duty cycles of D = 0.3, D = 0.5, and D = 0.7 are shown in Figure 8. The voltage at the input is 3V. It can be observed that the output voltage rises sharply when the duty cycle increases. The output voltage at D = 0.7 is equal to 100 V compared to 18 V at D = 0.3. Figure 9 compares the gains of different topologies at different duty cycles. The figure clearly shows an increase in the voltage gain of the HGCC compared to the Boost, CUK, and modified CUK converters. The difference in the voltage gain is big for higher values of D.

4. Experimental Setup and Results

A test setup was developed to verify the performance of the proposed converter, as shown in Figure 10. The setup includes RIGOL DG1022 function generator, ROHDE & SCHWARZ RTA4004 digital oscilloscope, RIGOL DP821A programmable dc power supply, and HGCC. The HGCC consists of capacitors, inductors, diodes (SB340), MOSFET(IRF3808), and a load resistor of 3 kΩ. In the proposed topology, the value of each capacitor is 100 μF, whereas each inductor is equal to 10 mH. The component values of HGCC are the same as those used in simulations. A 3 V DC was supplied to the circuit as an input voltage. A square wave with a frequency of 50 kHz, 10 V peak–peak voltage, and a duty cycle of 50% was generated from the function generator. The output results were measured using the digital oscilloscope.

Output voltage taken across the load resistor, which is in parallel with the capacitor C₀, is shown in Figure 11. Figure 11a,c illustrate output voltages at D = 0.3 and D = 0.4, respectively. Figure 11c shows the output voltage to be around 36 V in the steady state, the value also obtained in the mathematical model and simulations. The slight difference between the values in hardware and simulation results is due to the conduction and switching losses in the converter components of the experimental setup.

Voltages taken across different capacitors in steady-state are shown in Figure 12. The voltages across these capacitors reach the steady-state value predicted by our mathematical model and simulation results with a slight deviation. The deviation is due to the conduction and switching losses across different elements of the HGCC in the hardware setup.

Voltages across different diodes and MOSFET are illustrated in Figure 13. These values are taken in the steady state and match the result predicted by the mathematical model and simulations. The trend of switching is also the same as that given by the mathematical model and simulations. Conduction and switching losses account for the difference between simulation and experimental results.

The efficiency of the proposed topology versus the duty cycle is presented in Figure 14. The efficiency decreases, corresponding to an increase in the duty cycle. There is a sharp decrease in the efficiency of the HGCC at extremely high duty cycles. Since the proposed converter offers higher gain at low duty cycle values, the normal operating duty cycle range of the proposed converter varies from 0.2 to 0.5. Additionally, the efficiency of the proposed converter changes from 90% to 80% for the normal operating range of the duty cycle.

5. Conclusions

A new high-gain DC-DC converter topology HGCC was designed and experimentally tested. A mathematical model was developed to calculate the voltage across different capacitors and derive the general equation for the final output voltage. The HGCC was analyzed using a 1-level voltage unit multiplier. A simulation study was performed to test the working of the converter and obtain a better understanding of the switching scheme. An experimental setup was designed to validate the results obtained from the simulations. It is observed that by increasing the number of VMUs, the voltage gain of the converter can be further increased without disturbing the original topology. Moreover, the stress across the MOSFET is lesser compared to traditional converters, which allows us to use a MOSFET of lower resistance, hence resulting in better performance. The HGCC is also able to achieve higher voltage gain without operating at extreme duty cycles by adding VMUs, thus resulting in a prolonged lifetime of the proposed converter. In future work, a novel control system will be developed for the proposed converter that will improve the response of the voltage gain in transient and steady states.