FPGA-Based Antipodal Chaotic Shift Keying Communication System
, Anna Litvinenko, Deniss Kolosovs, Maris Terauds, Maris Zeltins and Dmitrijs Pikulins
Round 1
Reviewer 1 Report
The paper discusses a system for chaotic shift key modulation. Authors refers to FPGA in both title and abstract, but the manuscript content on this side is very limited. Section 3.1 does not clarify the digital design of the circuit. As it is, the paper lack of fundamental details and cannot really evaluated.
Authors are suggested to add more detail about the FPGA design and to compare their proposal with competitors over the same realization platform.
In the case, Authors have just synthesized simulink model I suggest to significantly moderate their claims.
Author Response
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Reviewer 2 Report
In this paper, authors presented a novel digital chaotic communication system with antipodal chaotic shift keying modulation, which is implemented in a FPGA. The communication system has application value in wireless sensor network systems. It is of reference significance for secure communication system designers. I have the following comments for reference.
1. First of all, in the introduction, authors should clearly highlight the novelty and contribution of the work, preferably with a bulleted or enumerated list.
2. Authors claim that "Such systems provide high security on the physical communication level", but the safety analysis is not highlighted in the paper.
3. Authors adopted Modified Chua circuit as chaos generator. Can the system design method in this paper be extended to other chaotic systems?
4. The performance is evaluated using simulation just with the additive white Gaussian noise channel. It is suggested to add more than one other type of noise channel simulation experiment.
Author Response
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Reviewer 3 Report
Review on “FPGA-based antipodal chaotic shift keying communication system”(ID: 1733337) submitted to Electronics
The manuscript presents a FPGA-based antipodal chaotic shift keying communication system, and studied its performance with the generation of some numerical results. The work seems to be interesting. Some comments are raised as follows:
1) Table 1 gives the summary of some chaos generators and chaotic synchronization implemented in FPGA. It is not sufficient to illustrate the advantages of the proposed communication system.
2) Why choose the step-size h = 1/1024 for solving the system?
3) The results “The white noise resistance of the communication system was evaluated within the 473 simulation—the BER drops below 10-3 at SNR above 5 dB.” is not show in the paper. Maybe more explanations can be given.
4) Some recent corresponding work on secure communication and image encryption can be included, such as Design and analysis of multiscroll memristive Hopfield neural network with adjustable memductance and application to image encryption. IEEE Transactions on Neural Networks and Learning Systems, 2022; Hidden coexisting hyperchaos of new memristive neuron model and its application in image encryption. Chaos, Solitons & Fractals, 2022.
5) Some errors in English writing should be corrected.
Author Response
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Reviewer 4 Report
The topic of the article is very interesting and I think it can make a relevant contribution to the area of study.
Although I am not an expert on the subject, I think I have some contributions in the context of the application of the scientific method:
- Introduction. It may be helpful to include a research question. This research question should fill the gap in the literature.
- Literature review. The introduction seems a bit long to me when compared to other sections. It may be helpful to divide this section and add an independent literature review section.
- Conclusions. It may be useful to divide the conclusions into subsections: contributions to the literature; contributions to practitioners; limitations; suggestions for further research.
Aside from these general comments, I think the article is well prepared.
Congratulations.
Author Response
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Author Response File: Author Response.pdf
Round 2
Reviewer 1 Report
You did not make any significant changes as a consequence of my comment. Furthermore, you wrote "The main contribution of this study is the design of an FPGA-based ACSK communication system, its performance verification, and evaluation of data transfer capabilities". This is simply not true!
The FPGA design must be fully described. In particular, the following items are mandatory:
1) detailed description of the adopted design flow, with specific notes regarding any synthesis/implementation constraints;
2) detailed comparison with state-of-the-art competitors in terms of: used resources (Logic Elements, Registers, RAM, DSPs etc.), power dissipation and throughput.
3) The architecture of the digital system must be clearly illustrated and discussed in comparison with archtectures demonstrated by state-of-the-art competitors to show the novelty of your FPGA design.
Without this information the actual advancement of your poposal cannot be evaluated from the digital design point of view.
Author Response
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Reviewer 2 Report
The authors have made a great work addressing all my concerns. I recommend the paper to be accepted.
Author Response
Thank you for the review. In our second paper revision, more detailed descritptions and illustrations of FPGA implementation structure of the communication system prototype is performed and some grammar mistakes are fixed.
Reviewer 3 Report
My concerns have been addressed.
Author Response
Thank you for the review. In our second paper revision, more detailed descritptions and illustrations of FPGA implementation structure of the communication system prototype is performed and some grammar mistakes are fixed.
Round 3
Reviewer 1 Report
The technical content is generally improved as requested. However, from tables 1 and 2 it is evident that the proposed approach reaches a throughput well below that shown by competitors. Authors have to discuss this behaviour more deeply pointing out this aspect in both introduction and conclusions. The statement "The maximum throughput for master chaos generator output is 1.06 Gbps, which can 236 be increased mainly through the optimization necessary to increase the maximum 237 clock frequency" is somewhat questionable. Do Authors have any space for optimization? Why did not already performed, if any?
Author Response
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