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Article

A Simple and Robust Equalization Algorithm for Variable Modulation Systems

1
Key Laboratory of Electronics and Information Technology for Space System, National Space Science Center, Chinese Academy of Sciences, Beijing 100190, China
2
School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences, Beijing 100049, China
*
Author to whom correspondence should be addressed.
Electronics 2021, 10(20), 2496; https://doi.org/10.3390/electronics10202496
Submission received: 30 August 2021 / Revised: 4 October 2021 / Accepted: 9 October 2021 / Published: 14 October 2021
(This article belongs to the Special Issue 5G and beyond Mobile and Satellite Communications)

Abstract

:
This paper proposes a simple and robust variable modulation-decision-directed least mean square (VM-DDLMS) algorithm for reducing the complexity of conventional equalization algorithms and improving the stability of variable modulation (VM) systems. Compared to conventional adaptive equalization algorithms, known information was used as training sequences to reduce the bandwidth consumption caused by inserting training sequences; compared with conventional blind equalization algorithms, the parameters and decisions of the equalizer were determinate, which was conducive to a stable equalization performance. The simulation and implementation results show that the proposed algorithm has a better bit error rate (BER) performance than that of the constant modulus algorithm (CMA) and modified constant modulus algorithm (MCMA) while maintaining the same level of consumption of hardware resources. Compared to the conventional decision-directed least mean square (DDLMS) algorithm, the proposed algorithm only needs to make quadrature phase shift keying (QPSK) symbol decisions, which reduces the computational complexity. In parallel 11th-order equalization algorithms, the operating frequency of VM-DDLMS can reach up to 333.33 MHz.

1. Introduction

Satellite communications are commonly applied to television program transmissions, Global Positioning System (GPS) navigation and positioning, and weather observation. This paper is mainly based on the data transmission of low earth orbit (LEO) satellites for research. The data transmission time in LEO satellites is very limited due to the fast movement of the LEO satellites. As the equipment grows more sophisticated and diverse, the data transmission amount through the satellite-to-earth link has increased tremendously, achieving a high-efficiency data transmission under the condition of limited hardware resources, but the bandwidth on the satellites has become a core problem that needs to be solved. Variable Modulation (VM) technology is used to improve the data transmission efficiency in the satellite–ground transmission link.
LEO usually uses a fixed modulation method based on the minimum link gain, resulting in a waste of transmit power. The VM system switches among various modulation modes by estimating the gain of the satellite–ground transmission link to make full use of resource allocation and improve the data transmission rate. In satellite communication systems, factors including the doppler shift, multipath effect, and group delay would cause inter-symbol interference (ISI) between transmitted and received symbols. Equalization algorithms are generally used to solve the ISI of the channel to improve the accuracy and stability of the satellite communication system.
In receivers, channel equalization is necessary to reduce ISI. According to the characteristics of equalization algorithms, it can be divided into adaptive equilibrium and blind equilibrium. The conventional adaptive equalization algorithm needs to adjust the filter coefficients by inserting additional training sequences, which increases the transmission bandwidth and reduces the transmission efficiency. The composition of the frame structure was determined in this study; therefore, it cannot be corrected by traditional adaptive equalization. Although the blind equalization algorithm has a worse steady-state convergence error than the adaptive algorithm, it adjusts the filter coefficients without training sequences. Therefore, the blind equalization algorithm was mainly analyzed in this study. The constant modulus algorithm (CMA), which is simple and easy to implement, was proposed in [1,2,3]. However, the convergence speed is slow, the steady-state error is large, and the phase shift cannot be corrected. During the mode switching, the correction parameters need to be modified according to the modulation, which decreases the stability of VM systems. In [4], the modified constant modulus algorithm (MCMA) was proposed to correct the phase shift. Although the MCMA can correct the phase shift, there remains the problem of the convergence speed and steady-state error. The correction parameters need to be modified according to the modulation when the mode is switched, which is not conducive to system stability; hence, it is not suitable for VM systems. In [5], the decision-directed least mean square (DDLMS) algorithm was proposed, which has a fast convergence speed and small steady-state error. However, the DDLMS algorithm needs to switch the decision mode according to the modulation during mode switching, and the implementation of a higher-order modulation is more complex. In [6], the algorithm of DDLMS with aided pre-convergence was proposed, which consists of an improved CMA algorithm with assisted pre-convergence and the DDLMS algorithm, which can further improve the system performance. However, the implementation of this algorithm is more complicated. The variable step size decision-directed LMS (VSS-DD-LMS) algorithm was proposed in [7], which improves the convergence speed by changing the variable-step adjustment algorithm, but it does not apply to systems with large initial errors and a high-order modulation. In [8], an improved CMA blind equalization algorithm was proposed, which modifies the updated equation of the filter coefficients and proposes a new weight calculation equation, thus improving the convergence speed and improving the BER performance. However, it is insensitive to the phase, and it needs to specify the modulation and modify the correction parameters. A blind equalizer composed of a modified algorithm (MA) cascaded with multi-step prediction error filters (MA-MSPEF) was proposed to minimize the mean square error (MSE) in [9]. However, it increases the implementation complexity for the VM system.
In the VM system, the conventional blind equalization algorithm needs to be dynamically adjusted according to the current modulation, but the current modulation method cannot be determined. Therefore, the conventional blind equalization algorithms are not suitable for the VM system. In this study, the advantages and disadvantages of the three conventional blind equalization algorithms of CMA, MCMA, and DDLMS were analyzed, and the data-aided equalization algorithm (VM-DDLMS) was proposed for the VM system. The proposed algorithm utilizes the characteristics of a QPSK-like modulation in the modulated frame header and modulated pilot from the PL frame to perform the equalization decision, updates the filter coefficients using the deviation between the known information and the corresponding received frame, and corrects data through an equalization filter. The VM-DDLMS algorithm only makes QPSK symbol decisions; it is not necessary to adjust the correction parameters and switch the symbol decision method according to the modulation method—this is conducive to the stability of the VM system. The proposed algorithm has the advantages of an easy implementation and good practicability.

2. Conventional Equalization Algorithm

Figure 1 shows a simplified diagram of the VM system. It mainly constructs four variable modulation physical layer (PL) frames, QPSK, 8PSK, 16APSK, and 32APSK, according to the modulation method, and performs mode switching according to the link schedule. The PL frame of the VM system is shown in Figure 2, and it is mainly composed of three parts: the frame header, data block, and pilot block. The frame header consists of 26 symbols of the start of frame (SOF) and 64 symbols of the physical layer signaling (PLS) code. The data block consists of 16 slots; one slot consists of 90 symbols. The pilot block insertion is every 16 slots; the pilot block consists of 36 pilot symbols, and each pilot shall be an un-modulated symbol, identified by I = 1 / 2 , Q = 1 / 2 . The VM system can improve the data transmission efficiency of the inter-satellite link, but it brings in new requirements for the stability and reliability of the equalization algorithm performance. Conventional equalizers can be composed of two parts: a digital filter and an adaptive algorithm. The digital filter is used to improve received signals’ amplitude distortion and phase distortion and to improve the accuracy of symbol decisions. An adaptive algorithm is used to adjust the filter coefficients so that the performance of the equalizer meets the design requirements. In this study, three conventional algorithms, namely CMA, CMMA, and DDLMS, were analyzed, and a new algorithm named VM-DDLMS for VM systems was proposed. The data correction was performed by the VM-DDLMS equalizer using known information from the physical layer frame.

2.1. CMA

The CMA mainly uses the steepest gradient descent method to find the minimum value point of the cost function. In [10], when the value of the cost function is minimal, equalization weight coefficients are stable near the optimal solution.
J 2 k = 1 4 E y k 2 R 2 2 ,
where y k is the output of the equalizer, and the correction parameter R 2 can be defined as:
R 2 = E a k 4 ) / E a k 2 ,
where a k is the input sequence; the correction parameter R 2 is different for different modulations.
The error signal of the CMA can be expressed as:
e k = y k y k 2 R 2 ,
The formula for updating the filter coefficients can be expressed as:
w k + 1 = w k - μ e * k x k ,
where μ is the step factor, x k is the equalizer input sequence, w k is the vector of the filter coefficients, and e * k is expressed as the complex conjugate of e k . The larger the parameter μ , the larger the residual error and the faster the convergence speed.
The CMA is insensitive to the carrier phase shift, which has a slow convergence speed and large steady-state error. The correction parameters need to be adjusted to match different modulations when mode switching is performed in the VM system.

2.2. MCMA

The MCMA is proposed to solve the problems of the CMA phase error. The cost function of the MCMA can be expressed as:
J k = E y R k 2 R 2 , R 2 + E y I k 2 R 2 , I 2 ,
where the real correction parameter R 2 , R and imaginary correction parameter R 2 , I are defined as:
R 2 , R = E a R k 4 ) / E a R k 2 ,
R 2 , I = E a I k 4 ) / E a I k 2 ,
Under different modulations, R 2 , R and R 2 , I have different values. The MCMA error signal can be expressed as:
e k = y R k y R k 2 - R 2 , R + j y I k y I k 2 - R 2 , I ,
The formula for updating the filter coefficients can be expressed as:
w k + 1 = w k - μ e * k x k ,
The MCMA cost function contains amplitude and phase information. It can correct the phase of modulated signals with in-phase and quadrature equal amplitudes, such as QAM modulation, which cannot be corrected without in-phase or quadrature equal amplitudes. In addition, compared with the CMA, the MCMA could not significantly improve the steady-state error and convergence speed. It is also necessary to adjust the real and imaginary correction parameters to match different modulations for VM systems.

2.3. DDLMS Algorithm

The DDLMS algorithm is a further improvement on the LMS algorithm. The algorithm does not require a training sequence, which maintains the advantages of the LMS algorithm without introducing additional computational complexity. The cost function of the DDLMS algorithm can be expressed as:
J k = 1 2 E y ^ k y k 2 ,
where y ^ k is the decision output. The DDLMS error signal can be expressed as:
e k = y ^ k y k ,
The formula for updating the filter coefficients can be expressed as:
w k + 1 = w k + μ e * k x k ,
The DDLMS algorithm needs to judge the output signal of the equalizer one by one and subtract the decision output y ^ k from the equalizer output y k to obtain the error function [11]. The residual error after convergence is small, but the algorithm cannot converge when the decision error of the signal is large. It is usually used in conjunction with other equalization algorithms. In addition, the output of the adjudicator makes a decision based on the known modulation method, and the symbol decision is more complicated in higher-order modulations. In the case of mode switching in the VM system, decision switching is required according to the current modulations. The DDLMS algorithm is not suitable for VM systems. In the VM system, the DDLMS algorithm needs to make a decision switch based on the current modulation, and the modulation mode cannot be determined at this time. Therefore, the DDLMS algorithm is not suitable for VM systems

3. Proposed Equalization Algorithm for VM System

3.1. VM-DDLMS Algorithm

The modulated frame header and the modulated pilot block are similar to QPSK mapping, which can be regarded as known information from the PL frame and used as the training sequence of the equalization algorithm. Therefore, an improved equalization algorithm based on training sequences suitable for VM systems called VM-DDLMS is proposed in this paper. Only when the input signal is the training sequence is the signal valid; the error signal is then calculated, and the filter coefficients are updated. The input signal in the data block is corrected by the trained filter.
According to Equations (3) and (8), CMA and MCMA error signals depend on the correction parameters of the current modulation mode. When the operating mode is switched in VM systems, the correction parameters are changed accordingly, so the CMA and MCMA are not optimal for VM systems. In addition, the performance of CMA and MCMA has not improved based on the training sequence. Therefore, the DDLMS algorithm is improved for VM systems based on the training sequence in this paper. The structure of the VM-DDLMS algorithm is shown in Figure 3. The filter coefficients are updated according to the input signal and error signal where the adjudicator only needs to make the QPSK symbol decision. The QPSK decision output can be expressed as:
r e y k = 0.7071 , r e y ^ k 0 0.7071 , r e y ^ k < 0 i m y k = 0.7071 , i m y ^ k 0 0.7071 , i m y ^ k < 0 ,
where y k is the input of the adjudicator, and y ^ k is the decision output. The cost function of the VM-DDLMS algorithm can be expressed as:
J k = 1 2 E y ^ k y k 2 ,
The VM-DDLMS error signal can be expressed as:
e k = y ^ k y k , e k , e n a b l e = 1 e n a b l e = 0 ,
where the e n a b l e signal is valid, it indicates that the data are the frame header or pilot, and the formula for updating the filter coefficients of the VM-DDLMS algorithm can be expressed as:
e k = y ^ k y k , e k , e n a b l e = 1 e n a b l e = 0 ,
Considering all factors, μ = 0.001 .

3.2. VM-DDLMS Algorithm Parallel Structure

To optimize the structure of the VM-DDLMS algorithm, the VM-DDLMS algorithm is parallelized and divided into four parts: the filter coefficient update module, equalization correction superposition output module, QPSK adjudicator module, and error calculation module. When the signal is the frame header or the pilot, the filter coefficient update module updates the filter coefficients w i ( k ) according to the input signal x i k and the error signal e k , and the filter coefficient update sub-module is controlled by the e n a b l e signal. The equalization correction superposition module will obtain the equalization output y ( k ) by parallel accumulation w 1 ( k ) x 1 ( k ) , w 2 ( k ) x 2 ( k ) , w N ( k ) x N ( k ) . The QPSK adjudicator makes a symbol decision on the equalization output y ( k ) of the training sequence. The error calculation module calculates the error signal e k based on the equalization output y ( k ) and the QPSK decision output y ^ k . To further improve the operating frequency of the VM-DDLMS algorithm, a pipeline design was carried out according to the structure of Figure 4, and registers were inserted between the combinational logic, which was divided into several small combinational logics to further refine the operation process and reduce the delay. As shown in Figure 4, the VM-DDLMS algorithm parallel structure inserting registers for the pipeline design is very clear and less complex.

4. Equalization Algorithm Simulation and Hardware Implementation

4.1. Performance Simulation of Different Equalization Algorithms

To verify the performance of the proposed algorithm in VM systems, four sources, QPSK, 8PSK, 16APSK, and 32APSK, were constructed according to the parameters shown in Table 1. The DDLMS algorithm was not applicable to the VM system. The CMA, MCMA, and VM-DDLMS adaptive equalization algorithms were simulated, respectively, under different signal-to-noise ratio (SNR) conditions, where the channel was a multipath channel plus Gaussian white noise channel. h ( n ) = [ 0.2 ,   0.5 ,   1 , 0.1 ] was the channel impulse response.
Under the 32APSK modulation with an SNR of 25 dB, the constellation diagram received after different equalization algorithms is shown in Figure 5. The equalizer input signal constellation had an obvious ISI after passing through the satellite communication channel. It can be seen from Figure 5b–d that the signal constellation after equalization was more concentrated, and the performance was much better than the signal without the equalization algorithm. Figure 6 shows the residual error diagrams of different equalization algorithms. It can be seen from Figure 6a that the steady-state error of the CMA algorithm stabilized after about 9000 symbols, and the steady-state error value was concentrated below 0.35. From Figure 6b, it can be seen that the steady-state error of the MCMA algorithm stabilized after about 8500 symbols. The error value was concentrated below 0.4. From Figure 6c, it can be seen that the steady-state error of the VM-DDLMS algorithm stabilized after about 6000 symbols, and the steady-state error value was concentrated below 0.15. The part where the steady-state error exceeded 0.15 is mainly because the known information was used as the training sequence to update the tap coefficients.
As shown in Figure 7, the VM-DDLMS algorithm and CMA had a better equalization performance for the QPSK and 8PSK modulation. When the BER was 10 5 , the performance loss of all algorithms was less than 1 dB. In the 16APSK and 32APSK modulation, the VM-DDLMS algorithm outperformed both CMA and MCMA. When the BER was 10 5 , only the performance loss of VM-DDLMS and CMA was less than 1 dB. Therefore, the VM-DDLMS algorithm simulation performance was better compared to CMA and MCMA. The proposed algorithm retained the advantages of the DDLMS algorithm, which reduced the computational complexity without a dynamic adjustment of the correction parameters when the mode switching was performed in the VM system. The proposed algorithm does not require the real-time switching of the symbol decision mode according to the modulation. In addition, the QPSK symbol decision is a low-order modulation so that the proposed algorithm can converge when the decision error of the signal is large. Therefore, the VM-DDLMS algorithm is simple to implement and has a high practicability.

4.2. Performance Analysis of Different Algorithm Implementations

The proposed VM-DDLMS algorithm was implemented on the hardware platform XCKU040-FFVA1156-2-E, and the development environment was Vivado2017.4. The DDLMS algorithm cannot converge when the decision error is large; thus, it was deployed jointly with other blind equalization algorithms. The DDLMS algorithm needs to make a symbol decision based on the different modulation methods, which is highly complex for the VM system. The performance of the CMA, CMMA, and VM-DDLMS algorithms was mainly compared in this study. As shown in Table 2, the resource consumption and operating frequency of the parallel 11th-order CMA, MCMA, and VM-DDLMS algorithms were compared, in which the resource consumption of the parallel 11th-order CMA, MCMA, and VM-DDLMS algorithms was almost the same, and the operating frequency of the VM-DDLMS algorithm was as high as 333.33 MHz, which improved the operating frequency by 26.66% compared with CMA and MCMA. The VM-DDLMS algorithm was more stable in the VM system without adjusting the correction parameters and switching the symbol decision mode in real time according to the modulation, and the algorithm also converged when the decision error was large; it was also simple to implement.

5. Conclusions

The VM-DDLMS adaptive equalization algorithm for the VM system is proposed in this paper, which utilizes the characteristics of the QPSK-like modulation in the modulated frame header and modulated pilot from the PL frame to perform the equalization decision. This algorithm updates the filter coefficients and improves the adaptability and stability of the equalization algorithm for the VM system. In addition, the VM-DDLMS is suitable for various modulation methods, and it is not necessary to adjust the correction parameters and switch the symbol decision according to the modulation mode. The simulation result shows that VM-DDLMS is better than CMA and MCMA among the four modulation methods QPSK, 8PSK, 16APSK, and 32APSK. When the BER is 10 5 , the performance loss of VM-DDLMS is less than 1 dB in the four modulation methods. The implementation result showed that the resource consumption of VM-DDLMS was almost the same as that of CMA and MCMA and that the operating frequency could be as high as 333.33 MHz in the parallel 11th-order, which has a comparatively higher practical value in the VM system.

Author Contributions

Conceptualization, W.H. and Z.W.; methodology, W.H.; software, W.H.; validation, W.H. and R.M.; formal analysis, W.H.; investigation, W.H. and R.M.; resources, W.H.; data curation, W.H.; writing—original draft preparation, W.H.; writing—review and editing, M.L. and R.M.; visualization, R.M.; supervision, W.H. and Z.W.; project administration, Z.W. and W.H. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the Strategic Priority Research Program of the Chinese Academy of Sciences (Class A) (Subject Number: XDA153501, Sub-Subject Number: XDA15350103).

Conflicts of Interest

The authors declare no conflict of interest.

References

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Figure 1. Simplified diagram of the VM system.
Figure 1. Simplified diagram of the VM system.
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Figure 2. PL frame for the VM system.
Figure 2. PL frame for the VM system.
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Figure 3. Structure diagram of the VM-DDLMS algorithm.
Figure 3. Structure diagram of the VM-DDLMS algorithm.
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Figure 4. Structure diagram of the VM-DDLMS algorithm. e*(k) is the conjugate of e(k).
Figure 4. Structure diagram of the VM-DDLMS algorithm. e*(k) is the conjugate of e(k).
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Figure 5. (a) Equalizer input signal constellation; (b) CMA equalizer output signal constellation; (c) MCMA equalizer output signal constellation; (d) VM-DDLMS equalizer output signal constellation.
Figure 5. (a) Equalizer input signal constellation; (b) CMA equalizer output signal constellation; (c) MCMA equalizer output signal constellation; (d) VM-DDLMS equalizer output signal constellation.
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Figure 6. (a) CMA algorithm error convergence curve; (b) MCMA algorithm error convergence curve; (c) VM-DDLMS algorithm error convergence curve.
Figure 6. (a) CMA algorithm error convergence curve; (b) MCMA algorithm error convergence curve; (c) VM-DDLMS algorithm error convergence curve.
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Figure 7. Comparison of the BER curves of three equalization algorithms.
Figure 7. Comparison of the BER curves of three equalization algorithms.
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Table 1. VM system simulation parameters.
Table 1. VM system simulation parameters.
Modulation MethodCode LengthFrame Length
QPSK81604242
8PSK81602846
16APSK81602166
32APSK81601758
Table 2. Parallel 11th-order equalization algorithm resource consumption.
Table 2. Parallel 11th-order equalization algorithm resource consumption.
Equalization AlgorithmCMAMCMAVM-DDLMS
DSP184 (9.58%)184 (9.58%)176 (9.17%)
LUT2364 (0.98%)2286 (0.94%)2300 (0.95%)
Register4542 (0.94%)4539 (0.94%)4440 (0.92%)
Workable Clock (MHz)263.15256.41333.33
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Hu, W.; Wang, Z.; Mei, R.; Lin, M. A Simple and Robust Equalization Algorithm for Variable Modulation Systems. Electronics 2021, 10, 2496. https://doi.org/10.3390/electronics10202496

AMA Style

Hu W, Wang Z, Mei R, Lin M. A Simple and Robust Equalization Algorithm for Variable Modulation Systems. Electronics. 2021; 10(20):2496. https://doi.org/10.3390/electronics10202496

Chicago/Turabian Style

Hu, Wanru, Zhugang Wang, Ruru Mei, and Meiyan Lin. 2021. "A Simple and Robust Equalization Algorithm for Variable Modulation Systems" Electronics 10, no. 20: 2496. https://doi.org/10.3390/electronics10202496

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