# High PSRR Wide Supply Range Dual-Voltage Reference Circuit for Bio-Implantable Applications

^{1}

^{2}

^{3}

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Methods

_{REFP}, is the established voltage across the current source circuit when both the current mirror and current source in the core circuit reach the desired operating point, as shown in Figure 2. However, an undesired operating point should be avoided because I

_{1}= I

_{2}= 0, a start-up circuit guarantees that the proposed circuit is not trapped in the zero-current state by initiating a current in the core circuit. The summation of V

_{GS1}and V

_{GS2}from ${V}_{GS}={V}_{DS,SAT}+{V}_{TH}$ produces V

_{REFP}. The negative reference voltage, V

_{REFN}, indicates the voltage generated when I

_{R}flows into the resistor, R. The three compensation circuits devised in this work are designated as Comp-A, Comp-B, and Comp-C in Figure 2.

_{2}and I

_{REFP1}, leaving a constant current in the core and current mirror circuits. A constant current can be achieved by equalizing the slopes of S

_{1}and S

_{2}, as well as those of S

_{3}and S

_{4}, respectively, for Comp-A and Comp-B. Comp-C generates the current I

_{CC}, which is added to the current mirror circuit. Assuming that I

_{CC}and I

_{REFP}

_{2}are linear currents, they may be written as

_{CC_DC}and I

_{REFP}

_{2_DC}are the DC currents of I

_{CC}and I

_{REFP}

_{2}, respectively. If S

_{5}= S

_{6}, I

_{CC}in Equation (1) can be written as

_{R}(S

_{7}= 0) is obtained if S

_{5}= S

_{6}(the detailed equations are provided in Appendix A). The PSRR performance is also increased by incorporating Comp-A, Comp-B, and Comp-C into the proposed circuit. The small-signal analysis that proves this idea will be presented later.

_{N}

_{2}, denoted as I

_{SA}, which then initiates a voltage at the gate terminals of M

_{P}

_{3}and M

_{P}

_{4}. The current starts flowing through M

_{P}

_{3}and M

_{P}

_{4}, thereby establishing V

_{REFP}. When V

_{REFP}exceeds the threshold voltage of M

_{N}

_{1}, current flows through M

_{P}

_{1}and M

_{P}

_{2}. The decrease in voltage at the drain terminal of M

_{N}

_{1}moves M

_{N}

_{1}into a deep triode region and eventually leads M

_{N2}to operate in a cut-off region. M

_{P6}, M

_{P5}, M

_{P}

_{12}, M

_{N7}, and M

_{P}

_{13}are newly added to the proposed reference circuit that consists of the Comp-A, Comp-B, and Comp-C circuits presented in Figure 2. The slopes of S

_{2}, S

_{4}, and S

_{6}shown in Figure 2 can be adjusted by varying the size of transistors M

_{P}

_{6}, M

_{N}

_{7}, and M

_{P}

_{13}, respectively, as shown in Figure 3. V

_{REFP}can be obtained from the circuit as:

_{N}

_{6}, M

_{P}

_{7}, and M

_{P}

_{9}form a current reference circuit, providing I

_{REFP}

_{1}to M

_{P}

_{8}. The nonlinear current in I

_{REFP}

_{1}is compensated by Comp-B, resulting in I

_{REFP}

_{2}, which is mirrored by M

_{N}

_{10}. The constant current I

_{R}produces V

_{REFN}across R

_{2}, given as:

_{REFN}becomes more negative if I

_{R}increases, the source-gate voltage of M

_{P}

_{13}increases and more current flows into M

_{P}

_{13}. According to Equation (5), the increment in I

_{CC}decreases I

_{R}. Thus, the negative feedback loop returns V

_{REFN}back to its initial value.

_{REFP}) small-signal analysis. v

_{R1}can be approximately equal to v

_{refp}because it is the output of the source follower circuit formed by M

_{N}

_{3}and R

_{1}in Figure 3. Therefore, v

_{g,P2}can be obtained by letting

_{g}

_{,P2}, we obtain ${v}_{g,P2}\approx {v}_{dd}$, resulting in ${g}_{m,P4}\left({v}_{dd}-{v}_{g,P2}\right)\approx 0$. Applying nodal analysis at the node of v

_{m}, the following equation can be derived:

_{refp}/v

_{dd}can be obtained as follows:

_{refp}/v

_{dd}is nearly zero. The proposed Comp-A contributes ${g}_{m,P6}$ in Equation (12), and hence increases the PSRR performance.

_{P}

_{10}and M

_{P}

_{8}is ignored because I

_{REFP}

_{1}is assumed to be an ideal current source. Assuming ${g}_{m,P13},{g}_{m,N8}\gg \frac{1}{{r}_{o,P13}},\frac{1}{{r}_{o,N8}}$, respectively, the r

_{o}of M

_{P}

_{13}and M

_{N}

_{8}can be neglected. From Figure 4b, the total resistance, R

_{TOT}, is extremely high, owing to r

_{o,N7}; hence, we can assume that ${v}_{x}\approx {v}_{y}\approx -{v}_{ss}$, resulting in ${g}_{m,N10}\left({v}_{y}+{v}_{ss}\right)\approx 0$. Applying nodal analysis at the node of v

_{Z}, the following equation is obtained:

_{refn}/v

_{ss}, we can obtain Equation (15).

_{refn}/v

_{ss}is inversely proportional to r

_{o,N10}. In addition, r

_{o,N10}is increased by a factor of g

_{m}

_{,p13}R

_{2}, introduced by Comp-C, which decreases the ratio v

_{refn}/v

_{ss}. g

_{m,p}

_{13}can be further increased by increasing I

_{CC}; however, I

_{R}will be reduced slightly, causing V

_{REFN}to become more positive. Hence, the PSRR is limited by the minimum value of V

_{REFN}.

## 3. Results

_{GS,N}

_{4}decreases, whereas V

_{GS,N}

_{3}increases with increasing V

_{DD}. As I

_{CA}in Comp-A increases rapidly at higher V

_{DD}, V

_{REFP}decreases. Thus, the slope of V

_{GS,N}

_{3}is assigned to be more positive than 3.5 mV/V to compensate for the variations at higher V

_{DD}. M

_{N7}in Comp-B senses the variations in V

_{DD}and produces I

_{CB}, as shown in Figure 5a, which compensates for the current variation in I

_{REFP1}. The slope of I

_{CB}(S

_{4}in Figure 2) can be adjusted by varying the size of M

_{N7}. Comp-C tracks the changes in voltage at node z, as shown in Figure 3, and produces I

_{CC}, which varies in the same manner as I

_{REFP2}, owing to channel-length modulation. I

_{CC}and I

_{REFP}

_{2}vary from 10 µA to 19 µA and 15.7 µA to 24.7 µA, respectively, and consequently, a stable I

_{R}of 5.7 µA is obtained when V

_{SS}ranges from 2.8 V to 12 V.

_{DD}and V

_{SS}are presented in Figure 5b. For bio-implantable applications, that is, retinal prosthetics, it is crucial to generate a negative supply voltage for producing a cathodic waveform in a biphasic pulse [14]. Accordingly, we observed a negative output reference voltage with a supply dependency of 1.583 mV/V. As shown in Figure 5a, the nonlinear I

_{CC}increases in a similar fashion to I

_{CA}; however, V

_{GS,N}

_{3}compensates for the V

_{REFP}variation caused by I

_{CA}. Conversely, V

_{REFN}varies at a high supply voltage owing to unmatched current rate changes in I

_{CC}and I

_{REFP}

_{2}. Thus, the negative reference line regulation is larger than the positive reference line regulation (0.916 mV/V).

_{DD}and V

_{SS}are plotted in Figure 5d, where the maximum PSRRs of −112 and −128 dB were obtained for V

_{REFP}and V

_{REFN}, respectively. The PSRR difference between V

_{REFP}and V

_{REFN}arises from the different factors in the denominator; r

_{o,P}

_{4}in Equation (12) increases by a factor of g

_{m,N4}(g

_{m},

_{p}

_{5}+ g

_{m,p}

_{6}), while r

_{o,N}

_{10}in Equation (15) increases by approximately g

_{m,P}

_{13}.

## 4. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Acknowledgments

## Conflicts of Interest

## Abbreviations

PSRR | Power supply rejection ratio |

LDO | Low-voltage drop regulator |

BJT | Bipolar junction transistor |

CMOS | Complementary metal-oxide semiconductor |

MOS | Metal-oxide semiconductor |

NMOS | N-channel metal-oxide semiconductor |

## Appendix A

_{6}in Figure 2 as

_{3}is obtained as follows

_{5}can be controlled by adjusting S

_{4}. The following derivation is for obtaining S

_{4}. First, I

_{CB}is assumed in the saturation region,

_{4}is obtained from the following equation:

_{N}

_{7}adjusts the slope of S

_{4}.

## References

- Jegadeesan, R.; Nag, S.; Agarwal, K.; Member, S. Enabling Wireless Powering and Telemetry for Peripheral Nerve Implants. IEEE J. Biomed. Health Inform.
**2015**, 19, 958–970. [Google Scholar] [CrossRef] [PubMed] - Lee, B.; Kiani, M.; Ghovanloo, M. A Triple-Loop Inductive Power Transmission System for Biomedical Applications. IEEE Trans. Biomed. Circuits Syst.
**2016**, 10, 138–148. [Google Scholar] [CrossRef] [PubMed] - Kuo, P.-H.; Wong, O.-Y.; Tzeng, C.-K.; Wu, P.-W.; Chiao, C.-C.; Chen, P.-H.; Chen, P.-C.; Tsai, Y.-C.; Chu, F.-L.; Ohta, J.; et al. Improved Charge Pump Design and Ex Vivo Experimental Validation of CMOS 256-Pixel Photovoltaic-Powered Subretinal Prosthetic Chip. IEEE Trans. Biomed. Eng.
**2020**, 67, 1490–1504. [Google Scholar] [CrossRef] [PubMed] - Duan, Q.; Roh, J.; Member, S. A 1.2-V 4.2-ppm C High-Order Curvature- Compensated CMOS Bandgap Reference. IEEE J. Solid-State Circuits
**2014**, 791, 1–9. [Google Scholar] - Andreou, C.M.; Koudounas, S.; Georgiou, J. A novel wide-temperature-range, 3.9 ppm/°C CMOS bandgap reference circuit. IEEE J. Solid-State Circuits
**2012**, 47, 574–581. [Google Scholar] [CrossRef] - Osaki, Y.; Hirose, T.; Kuroki, N.; Numa, M. 1.2-V supply, 100-nW, 1.09-V bandgap and 0.7-V supply, 52.5-nW, 0.55-V subbandgap reference circuits for nanowatt CMOS LSIs. IEEE J. Solid-State Circuits
**2013**, 48, 1530–1538. [Google Scholar] [CrossRef] - Lee, J.M.; Ji, Y.; Choi, S.; Cho, Y.C.; Jang, S.J.; Choi, J.S.; Kim, B.; Park, H.J.; Sim, J.Y. A 29 nW bandgap reference circuit. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Pap.
**2015**, 100–101. [Google Scholar] [CrossRef] - Ji, Y.; Jeon, C.; Son, H.; Kim, B.; Park, H.-J.; Sim, J.-Y. A 9.3 nW all-in-one bandgap voltage and current reference circuit. IEEE Int. Solid-State Circuits Conf. (ISSCC)
**2017**, 100–101. [Google Scholar] [CrossRef] - Lee, I.; Sylvester, D.; Blaauw, D. A subthreshold voltage reference with scalable output voltage for low-power IoT systems. IEEE J. Solid-State Circuits
**2017**, 52, 1443–1449. [Google Scholar] [CrossRef] - Gray, P.; Meyer, R. Analysis and Design of Analog Integrated Circuits; John Wiley and Sons: Hoboken, NJ, USA, 2010. [Google Scholar]
- Zhu, G.; Yang, Y.; Zhang, Q. A 4.6-ppm/°C High-Order Curvature Compensated Bandgap Reference for BMIC. IEEE Trans. Circuits Syst. II Express Briefs
**2019**, 66, 1492–1496. [Google Scholar] [CrossRef] - Zhou, Z.-K.; Shi, Y.; Wang, Y.; Li, N.; Xiao, Z.P.; Wang, Y.K.; Liu, X.L.; Wang, Z.; Zhao, B. A Resistorless High-Precision Compensated CMOS Bandgap Voltage Reference. IEEE Trans. Circuits Syst. I Regul. Pap.
**2019**, 66, 428–437. [Google Scholar] [CrossRef] - Sodagar, A.M.; Najafi, K. A wide-range supply-independent CMOS voltage reference for telemetry-powering applications. In Proceedings of the 9th International Conference on Electronics, Circuits and Systems, Dubrovnik, Croatia, 15–18 September 2002; Volume 1, pp. 401–404. [Google Scholar] [CrossRef]
- Kang, H.; Abbasi, W.H.; Kim, S.-W.; Kim, J. Fully Integrated Light-Sensing Stimulator Design for Subretinal Implants. Sensors
**2019**, 19, 536. [Google Scholar] [CrossRef] [PubMed][Green Version] - Zawawi, R.B.A.; Choi, H.; Kim, J. High-PSRR Wide-Range Supply-Independent CMOS Voltage Reference for Retinal Prosthetic Systems. Electronics
**2020**, 9, 2028. [Google Scholar] [CrossRef] - Kim, M.; Cho, S.H. A 0.0082-mm
^{2}, 192-nW Single BJT Branch Bandgap Reference in 0.18-µm CMOS. IEEE Solid State Circuits Lett.**2020**, 3, 426–429. [Google Scholar] [CrossRef]

**Figure 4.**Small-signal equivalent circuits of the proposed circuit. (

**a**) Positive reference circuit and (

**b**) negative reference circuit.

**Figure 5.**Results of (

**a**) DC responses of V

_{GS,N}

_{3}, V

_{GS,N}

_{4}, I

_{CA}, I

_{CB}, I

_{CC}, and I

_{R}, (

**b**) line regulation at typical condition ($0\mathrm{V}\le {V}_{DD}\le 12\mathrm{V}\mathrm{and}-12\mathrm{V}\le {V}_{SS}\le 0)$, (

**c**) line regulation in different corners, and (

**d**) PSRR.

Component | Parameters | Component | Parameters |
---|---|---|---|

M_{P}_{1}, M_{P}_{2} | W = 0.5 μm, L = 25 μm | M_{N}_{1} | W = 80 μm, L = 1 μm |

M_{P}_{3}, M_{P}_{4} | W = 4 μm, L = 1 μm, m = 50 | M_{N2} | W = 10 μm, L = 1 μm |

M_{P}_{5} | W = 1.15 μm, L = 1 μm | M_{N3} | W = 4 μm, L = 1 μm, m = 10 |

M_{P}_{6} | W = 4 μm, L = 1 μm, m = 9 | M_{N4} | W = 100 μm, L = 3 μm |

M_{P}_{7}, M_{P}_{8} | W = 4 μm, L = 1 μm, m = 4 | M_{N5} | W = 4 μm, L = 1 μm, m = 20 |

M_{P}_{9}, M_{P}_{10} | W = 16 μm, L = 1 μm | M_{N6} | W = 1 μm, L = 10 μm |

M_{P}_{11} | W = 4 μm, L = 1 μm | M_{N7} | W = 4 μm, L = 2 μm, m = 3 |

M_{P}_{12} | W = 1 μm, L = 50 μm | M_{N8}, M_{N9} | W = 5 μm, L = 10 μm |

M_{P}_{13} | W = 4 μm, L = 1 μm, m = 62 | M_{N10}, M_{N11} | W = 1 μm, L = 10 μm |

R_{1} | 70 kΩ | R_{2} | 150 kΩ |

Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. |

© 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Zawawi, R.B.A.; Choi, H.; Kim, J.
High PSRR Wide Supply Range Dual-Voltage Reference Circuit for Bio-Implantable Applications. *Electronics* **2021**, *10*, 2024.
https://doi.org/10.3390/electronics10162024

**AMA Style**

Zawawi RBA, Choi H, Kim J.
High PSRR Wide Supply Range Dual-Voltage Reference Circuit for Bio-Implantable Applications. *Electronics*. 2021; 10(16):2024.
https://doi.org/10.3390/electronics10162024

**Chicago/Turabian Style**

Zawawi, Ruhaifi Bin Abdullah, Hojong Choi, and Jungsuk Kim.
2021. "High PSRR Wide Supply Range Dual-Voltage Reference Circuit for Bio-Implantable Applications" *Electronics* 10, no. 16: 2024.
https://doi.org/10.3390/electronics10162024