# A New VCII Application: Sinusoidal Oscillators

^{1}

^{2}

^{*}

## Abstract

**:**

^{−}). Interestingly, the same analysis shows that no canonic oscillator configuration can be achieved using positive type VCII (VCII

^{+}), since a single VCII

^{+}does not present the correct port conditions to implement such a device. From this analysis, it comes about that, for 5-node networks, the two presented oscillator configurations are the only possible ones and make use of two resistors, two capacitors and a single VCII

^{−}. Notably, the produced sinusoidal output signal is easily available through the low output impedance Z port of VCII, removing the need for additional voltage buffer for practical use, which is one of the main limitations of the current mode (CM) approach. The presented theory is substantiated by both LTSpice simulations and measurement results using the commercially available AD844 from Analog Devices, the latter being in a close agreement with the theory. Moreover, low values of THD are given for a wide frequency range.

## 1. Introduction

^{−}), two resistors and two capacitors, so demonstrating a new practical application of the VCII. The notable advantage of the proposed VCII

^{−}-based oscillator is that it is easily cascadable from port Z of VCII

^{−}, alleviating the need for any extra voltage buffer. Moreover, THD values are low also for higher frequency oscillators. However, the results of this study show that the applied approach does not reach any canonic configuration using positive type VCII (VCII

^{+}). The effect of non-idealities in the VCII has been considered, and the proposed approach has been tested by both simulations and measurement results.

## 2. General Configuration of the VCII-Based Oscillator

^{+}, whereas if β = −1 we have a VCII

^{−}.

_{GC}represents 4-terminal network consisting of only capacitors and conductances.

^{−}and VCII

^{+}respectively. To ensure a pure sinusoidal oscillation, the CE in (7) should be a second-order polynomial with purely imaginary roots. This requires the network N

_{GC}to include at least two capacitors. It has to be noted that, in Figure 2, by using a VCII

^{+}rather than a VCII

^{−}, at least three capacitors are required to provide a phase shift to generate a positive feedback loop. Therefore, no canonic oscillator is possible using VCII

^{+}, and for the following, we will consider the VCII in Figure 2 as a VCII

^{−}. By then assuming a network with only two capacitors, Equation (7) will be in the form:

## 3. Oscillator Circuits

^{−}-based oscillators based on the scheme of Figure 2. The passive N

_{GC}is assumed as a general $n$-node network consisting of b possible branches between two nodes. Each node is a junction where two or more branches are connected, and each branch is an admittance connected between two nodes represented as:

#### N_{GC} as a Five-Node Network

_{GC}as a five-node network. We start analyzing this network by performing KCL at node Y as reported in the following:

_{8}and Y

_{9}, these admittances can be assumed as open circuit (Y

_{8}= Y

_{9}= 0). Routine analysis of Figure 4 results in i

_{3}as:

_{x}results:

_{a}= sC

_{a}+ G

_{a}and Y

_{b}= sC

_{b}+ G

_{b}, (19) can be written as:

_{GC}present non-zero admittance.

_{1}= Y

_{5}= Y

_{6}= 0) or (Y

_{3}= Y

_{5}= Y

_{6}= 0), we have Y

_{2}Y

_{4}= 0, while for (Y

_{2}= Y

_{5}= Y

_{6}= 0) or (Y

_{4}= Y

_{5}= Y

_{6}= 0), we have Y

_{1}Y

_{3}= 0. In both these cases, the CE has the general form of (19).

_{1}= Y

_{2}= Y

_{5}= 0), (Y

_{1}= Y

_{2}= Y

_{6}= 0), (Y

_{1}= Y

_{4}= Y

_{5}= 0), (Y

_{1}= Y

_{4}= Y

_{6}= 0), (Y

_{2}= Y

_{3}= Y

_{5}= 0), (Y

_{2}= Y

_{3}= Y

_{6}= 0), (Y

_{3}= Y

_{4}= Y

_{5}= 0), (Y

_{3}= Y

_{4}= Y

_{6}= 0) the CE has the following form:

_{1}= Y

_{3}= Y

_{6}= 0) and (Y

_{2}= Y

_{4}= Y

_{5}= 0), the CE is obtained as:

_{1}= Y

_{2}= Y

_{3}= 0), (Y

_{1}= Y

_{2}= Y

_{4}= 0), (Y

_{1}= Y

_{3}= Y

_{4}= 0) and (Y

_{2}= Y

_{3}= Y

_{4}= 0), the CE has the following general form:

_{1}= Y

_{3}= Y

_{5}= 0) and (Y

_{2}= Y

_{4}= Y

_{6}= 0), the CEs will be given by (24a) and (24b), respectively:

_{c}and Y

_{a}or Y

_{b}as a capacitance.

_{a}, Y

_{b}, Y

_{c}of the type sC + G; the two remaining admittances will be a capacitance sC, and a conductance G. Inserting all possible combinations of options into (25), two sets of CEs which show imaginary roots are obtained.

_{o}) and oscillation frequency (ω

_{0}) for the two cases are obtained respectively as:

_{1}= Y

_{3}= Y

_{5}= 0) and (Y

_{2}= Y

_{4}= Y

_{6}= 0) and the possible choices for Y

_{a}and Y

_{b}, we obtain a total of four canonic oscillators, corresponding to the following CEs:

_{1}= Y

_{3}= Y

_{5}= 0) and (Y

_{2}= Y

_{4}= Y

_{6}= 0) we obtain two equal oscillators if we exchange the order of the elements which are connected in series. These two configurations are shown in Figure 5, and the corresponding transfer functions, oscillation frequencies ω

_{0}and oscillation conditions are reported in Table 1. The oscillation frequencies and oscillation conditions in (28) show a strong interdependence since they are functions of the same parameters. Since the oscillation condition requires that the sum of the ratios of the capacitances and of the conductances is constant and equal to 1, a possible strategy for frequency tuning requires varying both resistors or both capacitors, maintaining their ratio constant. For example, a ratio of 2 between C

_{a}and C

_{c}can be obtained by using two parallel capacitors equal to C

_{a}to obtain C

_{c}; all three capacitors can be varied together; thus their ratio remains constant unless there are mismatches and the effect of parasitics.

## 4. Analysis of Parasitic Effects: A Case Study

_{A}and Z

_{B}are a series-connected RC network and a parallel-connected RC network; we define t

_{A}= R

_{A}C

_{A}and t

_{B}= R

_{B}C

_{B}as the time constants associated with these networks. The two oscillator topologies shown in Figure 6 correspond to the cases:

_{i}= 1/G

_{i}. From Figure 6, the oscillation condition can be obtained as:

_{A}and Z

_{B}given by (33), and of the port impedances (38)–(40), it is evident that the Type I canonic oscillator should be less affected by non-idealities. In fact, in this case Y

_{x}can be absorbed in Z

_{A}(${G}_{x}$ and ${C}_{x}$ are summed to 1/${R}_{5}$ and ${C}_{5}$, respectively), and Z

_{y}and Z

_{z}in Z

_{B}: a parallel RC network is used in parallel to a port impedance modeled as an RC parallel network, and a series impedance is connected in series to port impedances modeled as RL series networks. In contrast, for the Type II canonic oscillator, a series network is connected in parallel to the parallel RC port impedance, and a parallel RC network is connected in series to LR series port impedances, thus non-ideal port impedances alter Z

_{A}and Z

_{B}more significantly. The Type I canonic VCII-based oscillator seems therefore more suited to a practical realization, and it has been selected for further analysis.

#### 4.1. Resistive Port Impedances

_{x}, R

_{y}and R

_{z}in (39)–(41) are considered, the oscillation condition for the Type I canonic oscillator becomes:

#### 4.2. Single-Pole Transfer Functions

_{y}and R

_{z}and admittance Y

_{x}, as in the previous subsection, and we have

## 5. Experimental Results

_{0}in (49) has been checked for different values of τ and τ

_{x}= τ

_{z}, and errors lower than 1% have been found.

^{−}as shown in Figure 9. A single VCII is realizable using two AD844 ICs, whose Spice model can be found in [45]. The situation is quite different in the case of an integrated design, where a single VCII block can be exploited to design the oscillator, as shown in the previous sections.

_{0}= 10.6 kHz was expected.

_{0}= 10.8 kHz, as shown in Figure 11.

_{x}= 5.5 pF in parallel with a resistor R

_{x}= 3 MΩ. Purely resistive input impedances have been extracted at node Y (R

_{y}= 50 Ω) and Z (R

_{z}= 15 Ω). Finally, a dominant pole has been found for both the transfer function $\alpha \left(s\right)$ at f = 49 MHz (corresponding to ${\tau}_{x}$ = 3.25 ns), and for $\beta \left(s\right)$ at f = 764 MHz (${\tau}_{z}$ = 208 ps).

^{6}) Hz and are reported in Table 3. In agreement with simulation results, the oscillator shows a very low THD value even at 1 MHz (considering 10 harmonics). The average relative frequency error between measured and ideal values is −5.2% and is comparable with tolerances of the passive components.

## 6. Conclusions

^{−}. However, it is shown that, using the systematic approach, no oscillator configuration is possible using VCII+. The two found oscillator configurations are the only possible ones which use only two resistors, two capacitors and a single VCII

^{−}. Compared to Op-Amp-based oscillators, designed using the same systematic approach which employs two capacitors and four resistors, the proposed VCII-based oscillator is preferred in terms of low number of capacitors and resistances. Another interesting feature of the found VCII-based oscillator is that the produced sinusoidal output signal is easily available through the low output impedance Z port, while the CCII-based oscillators designed using the same systematic approach requires an additional voltage buffer for practical use. Simulations and experimental results using AD844 as VCII are reported to validate the theory.

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

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**Figure 3.**Positive feedback system: (

**a**) general schematic; (

**b**) positive feedback in the VCII-based oscillator.

**Figure 5.**VCII-based oscillators obtained in the case NGC is a five-node network. (

**a**)Series-parallel impedances configuration; (

**b**) parallel-series impedances configuration.

**Figure 8.**Relative error on the oscillation frequency vs. the time constant ratio ${\tau}_{par}/\tau $.

**Figure 11.**Simulated output spectrum of the oscillator shown in Figure 10.

**Figure 13.**Output waveform of the canonic VCII-based oscillator of Figure 5a. (

**a**) Time domain, (

**b**) frequency domain for an output frequency of 1 MHz.

Figure 5a | Figure 5b |
---|---|

${T}_{I}\left(s\right)=-\frac{{s}^{2}{C}_{5}{C}_{3}+s\left[{C}_{5}{G}_{1}+{C}_{3}{G}_{5}\right]+{G}_{5}{G}_{1}}{{s}^{2}{C}_{5}{C}_{3}+{G}_{5}{G}_{1}}$ | ${T}_{I}\left(s\right)=$ $\frac{s{C}_{2}{G}_{2}}{{s}^{2}{C}_{4}{C}_{6}+{G}_{2}{G}_{6}}$ |

${\omega}_{0}=\sqrt{\frac{{G}_{5}{G}_{1}}{{C}_{5}{C}_{3}}}$ | ${\omega}_{0}=\sqrt{\frac{{G}_{2}{G}_{6}}{{C}_{4}{C}_{6}}}$ |

C_{o}: $\frac{{G}_{5}}{{G}_{1}}+\frac{{C}_{5}}{{C}_{3}}=1$ | C_{o}: $\frac{{G}_{6}}{{G}_{2}}+\frac{{C}_{6}}{{C}_{4}}=1$ |

C_{3} = 2C_{5}(nF) | R_{5}(kΩ) | R_{1}(kΩ) | f_{0} (Spice)(Hz) | f_{0} (Model)(Hz) | f_{0} Error(%) | THD (%) |
---|---|---|---|---|---|---|

2000 | 15 | 7.3 | 10.8 | 10.74 | 0.6 | 0.7 |

200 | 15 | 7.35 | 107.3 | 107.0 | 0.3 | 0.4 |

20 | 15 | 7.35 | 1.073 K | 1.070 K | 0.3 | 0.4 |

2 | 15 | 7.3 | 10.80 K | 10.70 K | 0.9 | 0.5 |

0.2 | 15 | 6.9 | 108.1 K | 107.2 K | 0.9 | 0.7 |

0.2 | 1.5 | 0.65 | 1.080 M | 1.040 M | 3.7 | 1.7 |

R1 (kΩ) | R5 (kΩ) | C3 (F) | C5 (F) | Ideal Frequency (Hz) | Measured Frequency (Hz) | Error (%) | THD (%) |
---|---|---|---|---|---|---|---|

15 | 6.8 | 2 µ | 1 µ | 11.1 | 10.8 | −3 | 1.12 |

15 | 6.8 | 200 n | 100 n | 111 | 109 | −1.9 | 0.94 |

15 | 6.8 | 20 n | 10 n | 1.11 k | 1.08 k | −2.7 | 0.92 |

15 | 6 | 2 n | 1 n | 11.9 k | 11.5 k | −3.3 | 0.47 |

15 | 6 | 200 p | 100 p | 119 k | 109 k | −7.8 | 0.56 |

15 | 0.64 | 200 p | 100 p | 1.15 M | 1.0 M | −12.9 | 2.24 |

Ref. | ABB Type | ABB Number | C (Grounded) | R (Grounded) | Output Phases | Indep. w_{o}/C_{o} |
---|---|---|---|---|---|---|

[5] | Op-Amp | 1 | 2 (2) | 4 (2) | 1 | NO |

[7] | OTA | 3 | 2 (2) | -- | 2 | YES |

[9] | CCII | 1 | 2 (2) | 2 (1) | 1 | NO |

[9] | CCII | 1 | 2 (1) | 3 (3) | 1 | YES |

[12] | FTFN | 1 | 2 (1) | 5 (1) | 1 | YES |

[13] | CCII | 2 | 2 (2) | 2 (1) | 1 | YES |

[16] | CDTA | 2 | 2 (1) | -- | 2 | NO |

[19] | OTRA | 1 | 2 (0) | 3 (1) | 1 | YES |

[21] | CCCCTA | 1 | 2 (2) | 1 (1) | 1 | YES |

[23] | CCIII | 2 | 2 (2) | 3 (3) | 1 | YES |

[25] | UVC | 1 | 2 (1) | 3 (1) | 1 | YES |

[26] | VDTA | 1 | 2 (2) | -- | 2 | YES |

[29] | CFOA | 1 | 3 (2) | 4 (2) | 1 | YES |

[47] | CFOA | 1 | 2 (2) | 2 (1) | 1 | NO |

[47] | CFOA | 1 | 2 (1) | 3 (1) | 1 | YES |

[48] | OTRA | 1 | 2 (0) | 2 (0) | 1 | NO |

[48] | OTRA | 1 | 2 (0) | 3 (1) | 1 | YES |

[49] | CFOA | 1 | 3 (2) | 3 (3) | 1 | YES |

[50] | CDBA | 2 | 2 (2) | 3 (0) | 2 | YES |

[51] | OTRA | 1 | 3 (1) | 3 (0) | 1 | YES |

This Work | VCII | 1 | 2 (1) | 2 (1) | 1 | NO |

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**MDPI and ACS Style**

Stornelli, V.; Barile, G.; Pantoli, L.; Scarsella, M.; Ferri, G.; Centurelli, F.; Tommasino, P.; Trifiletti, A.
A New VCII Application: Sinusoidal Oscillators. *J. Low Power Electron. Appl.* **2021**, *11*, 30.
https://doi.org/10.3390/jlpea11030030

**AMA Style**

Stornelli V, Barile G, Pantoli L, Scarsella M, Ferri G, Centurelli F, Tommasino P, Trifiletti A.
A New VCII Application: Sinusoidal Oscillators. *Journal of Low Power Electronics and Applications*. 2021; 11(3):30.
https://doi.org/10.3390/jlpea11030030

**Chicago/Turabian Style**

Stornelli, Vincenzo, Gianluca Barile, Leonardo Pantoli, Massimo Scarsella, Giuseppe Ferri, Francesco Centurelli, Pasquale Tommasino, and Alessandro Trifiletti.
2021. "A New VCII Application: Sinusoidal Oscillators" *Journal of Low Power Electronics and Applications* 11, no. 3: 30.
https://doi.org/10.3390/jlpea11030030