Effect of Annealing Temperature on the Structural, Optical, and Electrical Properties of Al-Doped ZrO₂ Gate Dielectric Films Treated by the Sol–Gel Method

Abstract

In this article, we report the preparation of Al-doped ZrO₂ (AZO) thin films by the sol–gel method. The electrical properties, microstructure, and optical properties of AZO high-k gate dielectric films at different annealing temperatures were systematically investigated. XRD results confirm that the AZO film was amorphous at a temperature of 600 °C, and Al doping raises the crystallization temperature of ZrO₂. AFM and FESEM show a smooth surface of AZO film without cracks. As the annealing temperature increased from 600 to 900 °C, all of the films had similar RMS roughness under 1 nm, the film thickness decreased accordingly, the bandgap value increased from 5.77 to 5.82 eV, the valence band shift (ΔE_v) increased, and the conduction band shift (ΔE_c) decreased. XPS analysis showed that silicates were formed at the AZO/Si interfacial layer. Electrical performance tests showed that high-temperature annealing can effectively improve the electrical properties, as shown by the increase in dielectric constant (k) and the decrease in flat-band voltage (ΔV_fb). However, an increase in leakage current density with increasing annealing temperature was observed due to the decrease in ΔE_c and the appearance of crystallization caused by the increase in annealing temperature.

1. Introduction

Oxide semiconductor thin film transistors (TFTs) have attracted interest great because of their better optical transmittance and better mobility [1]. Due to the high dielectric constant (high-k) and associated interface formation with oxide semiconductors, high-k gate dielectrics such as HfO₂, Y₂O₃, Al₂O₃, TiO₂, CuO_, ZnO, and ZrO₂ have been widely used in oxide TFTs [2,3,4,5,6,7]. In addition, among the wide range of applications of high-k materials, zirconium oxide has long been of interest due to its various applications in microelectronics and nanoelectronic devices, making it one of the most valuable alternative materials [8,9,10]. Meanwhile, ZrO₂ is one of the most promising material candidates and can be used for many applications, including semiconductor devices, optical coatings, and fuel cells [11,12,13]. Usually, ZrO₂ exists as monoclinic phase, tetragonal phase, and cubic phases in equilibrium [14,15]. ZrO₂ has a relatively high k-value, and it is reported that the cubic or tetragonal crystalline form of stable ZrO₂ can increase the value of dielectric constant k. The important reason for the increase in dielectric constant is the change of crystal structure inside the film [16,17,18]. To the best of our knowledge, the tetragonal phase has the highest k-value among the different crystalline phases of Hf- and Zr-based oxides, and the most effective way to become a tetragonal phase is to add stable dopants such as Al, Y, or Si to the Hf- and Zr-based oxides [19,20,21,22]. Several authors have reported experimental and theoretical evidence of high k-values for a variety of crystalline forms of ZrO₂; they add elements such as Y, Al, Ge, and La by doping the oxides or during the deposition of thin films [23]. In addition, the phase of the crystalline product can be determined by the type and amount of dopant, and the synthesis route is also an important determinant [14]. The ideal gate dielectric should have a high dielectric constant k, an amorphous structure, and good thermodynamic stability on a silicon substrate. Some researchers have reported that for solution-treated oxide semiconductors, lattice defects in the oxide can be reduced by adding dopants that are easily oxygen-bound. For example, the doping of Ga can effectively reduce the number of oxygen vacancies. For the improvement of the dielectric properties of binary metal oxides as high-k gate dielectrics can be achieved by doping them with a third element. The added dopant causes the original bond structure order to be changed, so it affects the transition from the amorphous state to the crystalline state [4]. At the same time, the crystallization of the gate dielectric film is influenced not only by the doping elements, but also by, for example, the film thickness, the substrate stress, and the diffusion of the substrate elements [16]. Notably, among the ZrO₂ doping elements used for different polycrystalline types, Al is of particular interest because of its compatibility with complementary metal oxide semiconductor (CMOS) technology. Al has a great advantage over rare earth elements in this regard. Recently, gate dielectric films with dopants added to ZrO₂ are being transformed into various types of memory devices, which also makes it a potential candidate for high-performance transistors [24]. The gate dielectric films formed by Al-doped ZrO₂ showed better properties, including a high-quality surface and a steady state structure. In addition, alumina has a large bandgap, high crystallization temperature, and good interface characteristics. Electrical properties also have good characteristics, such as a low leakage current and a large dielectric constant. Al can be used as a stabilizer in the oxide film, so that ZrO₂ has a stable tetra phase, thus obtaining a larger dielectric constant. Therefore, doping Al in ZrO₂ is a suitable method to inhibit crystallization [2]. There are different methods to prepare Al-doped ZrO₂. For example, several research groups have studied Al₂O₃–ZrO₂ laminated films using atomic layer chemical vapor deposition [25]. Yeon Woo Yoo et al. prepared Al-doped HfO₂ and ZrO₂ films using the ALD method [26], and Wooseok Yang et al. prepared zirconium-doped AlO_x gate dielectrics by solution deposition to achieve the high quality and good performance of thin film transistors [4]; however, to our knowledge, there are fewer reports of Al-doped ZrO₂ films prepared by a simple sol–gel method. Although magnetron sputtering and atomic layer deposition have certain advantages in the preparation of thin films, these methods have some of the same disadvantages: the preparation process needs to be carried out under high vacuum, the operation process is complicated, and the preparation cost is high. The sol–gel method is one the most popular choices with the advantages of good homogeneity, high purity, feasibility, and low cost. In addition, such films can be prepared at room temperature and atmospheric pressure, thus eliminating the need for high-vacuum systems [27,28].

Therefore, it is interesting to study the thin films of aluminum-doped ZrO₂ (AZO) prepared by the sol–gel method. In this work, Al was chosen as a dopant for zirconia as a way to increase the crystallization temperature and reduce the annealing temperature in the process of production. A new way of preparing high-k dielectric films with chloride precursors is also provided, which allows the deposition of gate dielectrics on silicon and quartz substrates with high efficiency, simplicity, and speed. The obtained gate dielectric films are characterized by high quality and high dielectric properties. We have investigated the temperature dependence of the film structure, surface, cross-sectional morphology, and optical and device properties. The results indicate that the gate dielectric film has a crystallization temperature of 700 °C, a smooth and uniform surface, high forbidden bandwidth, and excellent electrical characteristics.

2. Materials and Methods

2.1. Thin Film Material and Fabrication

Al-doped ZrO₂ (AZO) films were deposited on n-type Si (100) substrates with resistivity of 1–20 Ω cm and quartz substrates. AZO precursors of 0.3 M were prepared by dissolving zirconium oxychloride octahydrate (ZrOCl₂·8H₂O, Aladdin, Shanghai, China 99%) and aluminum nitrate nonahydrate (Al(NO₃)₃·9H₂O, 99.99%) in anhydrous ethanol, where the molar ratio of Al/(Zr + Al) was 15%. Specific method: firstly, dissolve zirconium oxychloride octahydrate in anhydrous ethanol and put it on a magnetic stirrer for 1 h to make it fully dissolve. At this time, a certain amount of aluminum nitrate nonahydrate was added and stirred on a magnetic stirrer for 1 h to make it fully dissolved. Then add a small amount of hydrogen peroxide and acetylacetone solution as a hydrolysis promoter and stabilizer, respectively, and stir for 5 h at room temperature until fully dissolved. Finally, the stable precursors were obtained by aging at room temperature for 48 h. To obtain an impurity-free sol solution, the precursor solution should be filtered through an injection filter of 0.22 μm in size prior to formal coating. Finally, AZO films of certain thickness were deposited on n-type silicon substrates and quartz substrates by the sol–gel spin coating method. Prior to thin film deposition, the Si substrate and quartz substrate were cleaned using standard RCA (Radio Corporation of America) cleaning techniques to remove all impurity elements from the substrate. The silicon wafer is then intruded into a 1% HF solution to remove the natural oxides remaining on the film surface. Finally, the silicon substrate and quartz substrate are rinsed with deionized water and blown dry to obtain a hydrophilic surface.

AZO films were deposited on Si substrates at room temperature (25 °C) for 30 s at 3000 rpm rotational speed. In addition, thin films of certain thicknesses were deposited on the quartz substrate in the same way to explore its optical properties. Initially, these films were pre-annealed on a heating table for 10 min at a pretreatment temperature of 150 °C. The AZO films were then annealed in a muffle furnace at different temperatures (600, 700, 800, and 900 °C) for 2 h. The film samples were annealed in a muffle furnace and air atmosphere with a heating rate of 5 °C/min and cooled to room temperature with the furnace after completion of annealing.

2.2. Film Characterization

Figure 1 shows the preparation process of AZO films. The structure of the resulting films was characterized by X-ray diffraction (XRD, Bruker, Karlsruhe, Germany) and Cu -Kα radiation with a scan angle range of 20° ≤ 2θ ≤ 60° and a scan rate of 3°/min. The range voltage and current are 30 kV and 40 mA, respectively. Based on the half-height width of the X-ray diffraction peak, the size of the grain was derived using the Debye Scherrer formula. The transmittance of AZO films deposited on quartz substrates was measured by an ultraviolet-visible spectrophotometer (UV-Vis, Lambda 650S, PerkinElmer, Waltham, MA, USA) to analyze their optical properties. The elemental composition of the films and the electronic states of the elements were studied by X-ray photoelectron spectroscopy (XPS, Thermo scalable 250 Xi manufactured by Thermo Fisher Scientific, Waltham, MA, USA) and all data were corrected with the binding energy of the C 1s peak (284.8 eV). The surface was tested by AFM (Bruker Dimension Icon, Billerica, Germany) to obtain morphological and roughness information. The surface morphology and cross-sectional thickness of the films were studied by field emission scanning electron microscopy (FESEM, SU8020 manufactured by Hitachi, Hitachi, Japan).

2.3. Metal Insulator Semiconductor (MIS) Device Fabrication

A systematic study of the electrical properties of the AZO gate dielectric layer is essential. MOS capacitors consisting of Al/AZO/Si/Al structures were fabricated. The top aluminum electrode of size 0.16 mm² was deposited on the AZO film by magnetron sputtering as a metal gate electrode. An aluminum film was deposited on the back side of the sample as a back electrode. The electrical characteristics were analyzed by measuring the capacitance voltage (C-V) and current voltage (I-V) of MOS capacitors. After mounting and linking the semiconductor device analyzer (Agilent B1500A, Palo Alto, CA, USA) to the probe stage. The entire measurement process was carried out at room temperature. A high frequency 1 MHz sinusoidal signal is applied superimposed on the DC voltage between the top and bottom electrodes. All electrical performance tests are performed at room temperature and in a light-proof environment.

3. Results and Discussion

3.1. Structural Analysis

Figure 2 shows the XRD plots of AZO films at 600–900 °C annealing temperatures. We found that no diffraction peaks appear in the AZO film samples at an annealing temperature of 600 °C, indicating that the film does not show crystallization and the film structure is still amorphous. It has been reported that pure ZrO₂ films have crystallized significantly at 600 °C [29,30,31,32]. The crystallization temperature of Al-doped zirconia films was significantly increased, and the thermodynamic stability of the films was improved, thus enhancing the amorphous formation ability of the films. AZO films annealed at 700–900 °C show a clear diffraction peak at 2θ = 30.42°, corresponding to the (1, 1, 1) crystalline plane, indicating that the films are in the crystalline state at this time, and zirconia exists in the form of the tetragonal phase. The diffraction peaks exhibit larger widths and lower intensities, thus indicating that some of the particles are embedded in the amorphous structure [25]. As the annealing temperature increases, the peak intensity of the films increases, and the diffraction peaks move in the lower 2θ direction, which may be due to Al doping with a higher lattice constant, which may be a reasonable result of the smaller ionic radius of Al³⁺ (51 pm) compared to Zr⁴⁺ (72 pm) [26]. The grain size was obtained by Debye Scherrer calculations as follows [30,33,34,35]:

$$D=\frac{0.9\lambda }{\beta \times \cos \theta }$$

(1)

where λ is the X-ray wavelength (λ = 0.154 nm), β is the diffraction peak half-height width, and θ is the diffraction angle. The grain sizes of the samples were 9.2, 9.9, and 10.5 nm for heat treatment temperatures of 700, 800, and 900 °C, respectively.

As in Figure 3, the chemical state and elemental composition of the AZO films were studied using XPS. The XPS measurements of AZO films were scanned in the range of 0–1400 eV. All XPS spectra were carbon-corrected at 284.8 eV. As shown in the figure, no peaks were detected from other elements other than those originating from Zr, C, O, and Al elements. Among them, the presence of the C 1s peak may correspond to impurities in the film. This indicates that the Al element was successfully doped into ZrO₂.

The XPS patterns of the O 1s core energy level are shown in Figure 4a. From the figure, we can see that the O 1s pattern decomposes into two components with peak positions located at 529.8 and 531.6 eV. The oxygen in these two components acts in the formation of silicate and Zr–O–Al bonds. As the annealing temperature rises, the peak shape and peak position do not change significantly, while the intensity of the peaks increases significantly, which may be due to the formation of a silica interfacial layer when annealed in air. There is some oxygen in the film that can diffuse through the grain boundaries, and the metal oxide layer has a higher oxygen diffusion rate than the silicon oxide layer, which strongly inhibits the diffusion of oxygen. Higher annealing temperatures lead to the faster diffusion of oxygen. The XPS spectra of the core energy levels of Zr 3d and Al 2p in AZO at different annealing temperatures are shown in Figure 4b,c. The binding energies of the main peaks of Zr 3d_3/2 and Zr 3d_5/2 are 184.3 and 181.9 eV, respectively, with a mean difference of 2.4 eV. The main peak of Al 2p is located at 72.9 eV. At annealing temperatures from 600 to 900 °C, the intensity of the nuclear energy level spectra of both Zr and Al increases significantly, and the core energy level peak positions move toward the high binding energy, but their peak shapes do not change significantly. Zr 3d_3/2 and Zr 3d_5/2 show a clear shift toward higher binding energy, and the possible reason for this is the generation of more Zr-silicates at the interface between AZO and the silicon substrate during the annealing process. At high annealing temperatures, oxygen diffuses from the AZO gate medium and reacts with the substrate, resulting in the formation of a silicate interfacial layer, while Al 2p shows a significant shift toward high binding energy, which is attributed to the formation of Zr–O–Al bonds [18,36].

3.2. Optical Properties Analysis

Widely distributed light wavelength absorption is an important property that every good photocatalyst should have, and AZO films exhibit continuous transmittance throughout the UV–Vis spectrum. Figure 5 shows the optical characteristics of AZO films at different annealing temperatures. Clearly, in the visible (400–700 nm) region, the transmittance of the annealed AZO films exceeds 80%, showing a high transmittance, which indicates the potential application of AZO films in the field of transparent electronic devices.

Clearly, the determinants of gate leakage current levels in CMOS devices are inextricably linked to bandgap size, valence band, and conduction band offsets and can also be used as physical factors to evaluate high-k gate dielectrics [37]. Based on the transmittance data of AZO films, the standard Tauc plot formula is as follows [38]: αhν = A${\left(\mathrm{h}\mathsf{\nu }-E_g\right)}^{1/2}$, where α is the absorbance index, h is Planck’s constant, ν is the optical frequency, A is a constant, and E_g is the semiconductor forbidden bandwidth. The bandgap size of the AZO film is calculated, and the calculation results are tallied in Figure 6. From the figure, the bandgaps of AZO films at 600, 700, 800, and 900 °C annealing treatments are 5.77, 5.79, 5.80, and 5.82 eV, respectively. Defects in low-temperature oxide films can create localized states in the bandgap, which are usually attributed to impurities, defects, and disorder in the material lattice, thus, the bandgap of AZO films may be reduced [39]. Therefore, high-temperature treatment reduces internal defects and the localized state of the film; the forbidden band width of AZO films gradually increases, which is also attributed to the elimination of oxygen vacancies.

Figure 7 shows the VBMs of AZO films and Si substrates at different annealing temperatures. To better evaluate the potential application of AZO gate dielectric. More attention has been paid to the valence band shift (ΔE_v) of the thin film gate dielectric. The valence band shift (ΔE_v) of AZO thin film samples after annealing can be determined by calculation. Based on the relevant theoretical knowledge, the value of ΔE_v is determined by the following equation [40]:

ΔE_v (AZO/Si) = E_v (AZO) − E_v (Si)

(2)

where E_v (Si) = 0.50 eV. Based on this, the valence band offsets can be calculated as 1.87, 1.96, 2.01, and 2.07 eV for all of the samples annealed at 600–900 °C.

Figure 8 shows the band shifts of AZO films at different annealing temperatures. All of the samples have a conduction band offset higher than 1 eV, which is required for device fabrication. With the bandgap of AZO film and ΔE_v, the conduction band offset (ΔE_c) can be derived by the following equation [40]:

ΔE_c (AZO/Si) = E_g (AZO) − ΔE_v (AZO/Si) − E_g (Si)

(3)

E_g (AZO) and E_g (Si) are the bandgap of AZO film and Si. The resulting conduction band offsets for the films annealed at 600, 700, 800, and 900 °C are calculated to be 2.78, 2.71, 2.67, and 2.63 eV, respectively. It is clear that the valence band offset (ΔE_v) increases and the conduction band offset (ΔE_c) decreases as the annealing temperature increases.

3.3. Surface Topography and Roughness Studies

Figure 9 shows the atomic force microscopy (AFM) image of the AZO film with a scan range of 1 μm × 1 μm. In the figure, the root mean square (RMS) roughness of the AZO films annealed at 600, 700, 800, and 900 °C were 0.290, 0.473, 0.609, and 0.778 nm, respectively. At high temperatures, when the atoms gain enough energy, the atomic clusters first merge further, leading to a decrease in the number of single crystals due to the destruction of the crystals and the film taking on a disordered polycrystalline form, leading to a decrease in film quality and an increase in roughness. In addition, the increased surface roughness with increasing temperature annealing could be attributed to the agglomeration phenomenon driven by the increased thermal absorption [41]. The surface roughness of the film increases, which is thought to be a possible cause of crystallization producing large grains. The roughness of the AZO film is minimal at 600 °C and the film is amorphous at this time, which indicates that the film surface is very smooth. AZO exhibits less roughness than pure ZrO₂ because the small-sized aluminum atoms can easily penetrate the interstitial ZrO₂ lattice sites, resulting in smoother, denser films [42]. It was reported that the crystallization temperature of the ZrO₂ thin film crystallizes over 400 °C. From the analysis of XRD results, it is clear that aluminum doping increases the crystallization temperature of ZrO₂ thin film. Smooth AZO gate dielectric films can effectively reduce the density of defect states and reduce charge traps in the interface layer between the channel and gate dielectric. Better interface quality will suppress the large leakage currents caused by roughness and will also result the in improved electrical performance of the device [43]. The amorphous phase has greater advantages over the crystalline phase, such as a lower leakage current and higher breakdown voltage. The analysis of the above results shows that Al doping has a significant effect on the performance of the gate dielectric films. Therefore, the AZO film is sufficient to be used as a gate insulator in this study.

Figure 10 shows the SEM images of AZO films at different annealing temperatures. The AZO film surface is very uniform and dense without cracks. This means that the Al-doped ZrO₂ films deposited in this work are suitable for making MOS capacitors. In addition, the crystallinity on the film surface was very small at annealing temperatures of 600 and 700 °C. At 800 °C annealing, the irregularity and size of the grains that appeared on the film surface due to crystallization, which also indicates that the high temperature, may have destroyed part of the crystal structure. In addition, at 900 °C annealing, the irregularities of the film grains were more pronounced, and the grain size also increased significantly, which would also lead to the increase in the film roughness, which is consistent with the results of AFM. In addition, it can be seen from the inset of the figure that the thicknesses of AZO films are 75.96, 73.89, 68.29, and 67.98 nm at annealing temperatures of 600 to 900 °C, respectively. This may be due to the strong reaction of residual solvents and impurities, as well as the reduction in film thickness due to the release of volatile gases from acetylacetone groups inside the film during high-temperature annealing. Evidently, SEM and AFM analysis showed that the films were smooth and crack-free, and the whole films were very dense and void-free, so the film quality was good enough to be used for fabricating MOS capacitors and thus furthermore for microelectronic devices.

3.4. Electrical Characterics Analysis

Figure 11 shows the C-V curves of Al/AZO/n-Si MOS capacitors measured at a high frequency (1 MHz) with respect to different annealing temperatures. All of the samples were measured by applying a bias voltage of −4 to +4 V at 1 MHz. The Al/AZO/n−Si MOS structure exhibits good saturation behavior in the accumulation, depletion, and inversion regions. It is obvious that heat treatment has an important effect on the electrical properties of the AZO gate dielectric. The capacitance in the accumulation region increases significantly with the increase in the annealing temperature, which may be due to the different thicknesses of the insulation layer. Alternatively, this may be related to the increase of the dielectric constant. However, there is a hump at ~0 V, which may be related to a slow trap at the interface [44]. To further investigate the electrical properties of the AZO gate dielectric at different annealing temperatures, we calculated the dielectric constant (k), flat-band voltage (V_fb), equivalent oxide thickness (EOT), and border trap charge density (N_bt) based on the C-V curves, as shown in

Table 1. Parameters extracted from C-V curves.

Samples	Cox (pF)	EOT (nm)	k	Cfb (pF)	Vfb (V)	ΔVfb (V)	Nbt (cm−2)
600 °C	183.71	30.06	10.08	127.02	0.78	0.49	3.52 × 1011
700 °C	244.49	22.58	12.85	153.61	1.43	0.12	1.15 × 1011
800 °C	260.42	21.21	12.86	159.53	1.76	0.09	9.16 × 1010
900 °C	294.72	18.74	13.42	171.75	2.13	0.07	8.06 × 1010

. In this work, the values of dielectric constant (k) are determined by the following formula: k = t × C_max/Aε₀. where t is the thickness of AZO thin films, C_max is the accumulation capacitance, A is the Al electrode area, and ε₀ is vacuum permittivity. As the annealing temperature increases from 600 to 900 °C, the dielectric constant (k) increases from 10.08 to 13.42, probably because the dielectric constant depends on the growth temperature, phase change, and stress in the film [45], This may be related to the detection of silicates formed in the interfacial layer by XPS. In addition, the dielectric constant k of all of the samples is lower than the reported value, which is most likely due to the formation of low dielectric constant silica in the interfacial layer during the high-temperature annealing process [46]. The equivalent oxide thickness (EOT) was reduced from 30.06 to 18.74. The increased crystallinity of the AZO layer and the increase in the final grain size are direct evidence of an increase in the dielectric constant. In addition, all of the samples have positive flat-band voltage (V_fb), which may be due to the negative trap charge inside the AZO film or at the interface. It has been reported that oxygen vacancies can capture one or two electrons to become negatively charged centers, causing a positive flat-band voltage [47]. The C-V image shows the presence of flat-band voltage shift (ΔV_fb) in the thin film samples, indicating the presence of charge capture and release processes [48]. This hysteresis phenomenon is caused by the difference in the time of border trap capture and emission of electrons [49]. The border trap density of the sample is calculated by the following equation [46,50]: N_bt = −(C_oxΔV_fb)/qA, where C_ox is the capacitance of the accumulation region, and A and q are the areas of the Al electrode and the amount of electron charge. The films treated at 900 °C have the smallest border trap density of −8.06 × 10¹⁰ cm⁻², which is mainly attributed to its extremely small ΔV_fb. Based on the above analysis, high-temperature annealing can effectively suppress border traps.

Figure 12 shows the characteristic curves of the leakage current density of AZO gate dielectric films concerning MOS gate voltage (J-V) at different annealing temperatures. All of the curves were measured at room temperature with a scan range of −4 to +4 V. It is obvious that there is a significant asymmetry in the leakage current density where the absolute values of the voltages are the same, which is mainly attributed to the different interfaces on both sides of the AZO layer [51]. In addition, the energy bands in different injection modes are different [52,53]. In the positive voltage region is the substrate injection and in the negative voltage region is the gate injection. The leakage current densities are 1.86 × 10⁻⁴, 6.24 × 10⁻⁴, 8.23 × 10⁻⁴, and 2.32 × 10⁻³ A/cm² at different annealing temperatures for a gate voltage of 2 V. The grid media has the lowest leakage current density when annealed at 600 °C, which is probably due to the increase in leakage current caused by the decrease in ΔE_c at higher temperatures [40]. In addition, when the temperature increases, the gate dielectric layer begins to crystallize, which leads to the creation of grain boundaries and provides a channel for electron flow [54]. In conclusion, the increase in leakage current is attributed to crystallization during the high-temperature annealing process, resulting in the appearance of grain boundaries in the AZO films.

The electrical parameters of the MOS manufactured in this study are listed in

Table 2. The related electrical parameters of some dielectric materials are reported in the literature and in this work.

Dielectric Substance	Annealing Temp. (°C)	Dielectric Constant (k)	Leakage Current (A/cm2)	Year	References
Gd-doped ZrO2	400	9.4	1.8 × 10−6	2016	[53]
Yb2O3	500	9.02	5.36 × 10−7	2020	[46]
SrOx	400	12.4	1.0 × 10−3	2017	[41]
Al-doped ZrO2	700	12.85	6.24 × 10−4	This work

and compared with the different dielectric materials previously reported. We found that the AZO films in this work have a high dielectric constant and relatively low leakage current. These excellent properties indicate that AZO films are attractive as candidate materials for CMOS devices.

4. Conclusions

In summary, we have deposited Al-doped ZrO₂ gate dielectric films by the sol–gel method and systematically discussed the possibility of their application in MOS devices. Structural analysis shows that the crystallization temperature of zirconia is greatly increased due to the Al doping and grain size increases. Based on the XPS test results, the interfacial layer of AZO/Si consists mainly of silicate at high-temperature annealing. The optical analysis results show that the AZO film has high transmittance and a large bandgap. In addition, increasing the annealing temperature can effectively reduce the film thickness and make the film denser, but the roughness of the film increases subsequently. The electrical properties show that the effective permittivity of AZO films increases and ΔV_fb decreases with an increasing annealing temperature, and the leakage current density of AZO films treated at high temperatures increases due to E_c reduction and film crystallization caused by high-temperature annealing. Therefore, it can be inferred that a reasonable annealing temperature is necessary to help us obtain better performance for MOS devices.