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Article

A Boundary Scan Test Vectors Optimization Method Based on Improved GA-AO* Approach Considering Fault Probability Model

1
School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China
2
School of Foreign Languages, University of Electronic Science and Technology of China, Chengdu 611731, China
3
Department of Measurement and Control Engineering, School of Mechanical Engineering, Sichuan University, Chengdu 610065, China
*
Authors to whom correspondence should be addressed.
Appl. Sci. 2024, 14(6), 2410; https://doi.org/10.3390/app14062410
Submission received: 27 January 2024 / Revised: 9 March 2024 / Accepted: 10 March 2024 / Published: 13 March 2024

Abstract

:
The generation of test vectors is a key technique that affects the efficiency and fault detection rate of the boundary scan test. Aiming at the local optimal solution problem of the current common test vectors generation algorithm, this paper proposes a test vectors generation algorithm based on improved GA-AO* model, through which the test vectors are generated by using the idea of heuristic search and backtracking correction. In order to speed up the heuristic search, this paper designed a heuristic function with both prior and posterior parameters to describe the influence of typical faults on the failure probability index of the test vectors. At the same time, this paper used a genetic algorithm (GA) to determine the specific values of the posterior parameters iteratively. Finally, through theoretical analysis and physical verification, compared with the test vector generated by the traditional method, the test vector generated by this method is optimized on the prior failure probability index and performs better in the physical experiment.

1. Introduction

The boundary scan test is an advanced technique for digital circuit fault detection, which is widely used in large-scale digital circuit tests due to its fast and efficient testing advantages [1,2,3,4,5]. However, with the increase in IC density and complexity, the scale of boundary scan test vectors also increases rapidly, which leads to a decrease in test efficiency and fault detection precision [6,7]. How to generate a high-performance matrix of test vectors (MTV) for large-scale circuits has become a challenging problem [8,9,10].
In order to improve the quality of the MTV itself and achieve the goal of satisfying both test efficiency and fault isolation rate, many algorithms based on the mathematical characteristics of the test vector itself have been proposed, for example, counting sequence algorithm, modified counting sequence algorithm [11,12], Walking-1/0 sequence algorithm [13], W-test adaptive algorithm [14]. These methods are studied from the perspective of the mathematical characteristics of the MTV to achieve its optimization; they do not take into account the physical characteristics of the circuit under test. In order to bring the characteristics of the circuit itself and circuit fault into the scope of study, the limited fault model is proposed by researchers. Based on the physical distance between the networks in the circuit under test, the limited fault model calculates the prior probability of short-circuit fault and generates the MTV according to the probabilities, so that the MTV is further optimized. Ref. [15] uses the PSO algorithm to optimize the direction of generation for MTV; under the condition of maintaining the optimal test efficiency, the misjudgment rate and confusion rate of MTV are reduced. In Ref. [16], the genetic algorithm is used to optimize the grouping mode of circuit networks under test, and the MTV are optimized by assigning the networks with low probability of short circuit fault to the same test group. Ref. [17] describes the performance of MTV by fitness function and iterates test vectors with excellent performance by the genetic algorithm. Ref. [18] presents a method for optimizing test vectors based on fault information using the idea of heuristic. Ref. [19] provides a way to optimize test vectors by using randomly generated faults.
While keeping the testing efficiency unchanged, the above methods generate MTV by using intelligent iterative algorithm and reduce the misjudgment rate and confusion rate of MTV to some extent. However, the improper design of particle iteration and the difficulty to determine the search direction of these intelligent algorithms leads to the fast convergence in the optimization of misjudgment rate and confusion rate, the result is always trapped in the local optimal solution [20,21,22,23,24,25]. With the increase in the network size of the circuit under test, the local optimal solution of misjudgment rate and confusion rate will lead to a serious decline in the fault detection accuracy of the boundary scan [26,27,28]. A new approach to further optimize MTV is needed.
In this paper, an optimization method of MTV based on GA (Genetic Algorithm) and an improved AO*model is proposed. Firstly, this paper analyzes the mathematical model of interconnected short-circuit fault under the limited fault model and obtains the short-circuit fault mode which has the most influence on the circuit. After modeling the faults, this paper gives the evaluation indexes of misjudgment rate and confusion rate of MTV under these fault modes, and this paper sets the evaluation index of the MTVs to be optimized as the upper bound of the search and generates the MTV within the upper bound of the search by using the improved AO* model, which is an AND/OR graph search algorithm based on heuristic function and backtracking correction [29]; thus, the optimization of MTV is realized. To balance the search speed and the performance of the generated MTV, this paper sets the threshold and the number of threshold searches to improve the AO* model and adjusted the threshold in an adaptive way. At the same time, this paper establishes a heuristic function model combining the characteristics of the boundary scan test and the characteristics of the circuit under test and used a genetic algorithm to generate the parameters of the heuristic function that describe the characteristics of the circuit under test. When using the improved AO* model to generate MTV, this paper determines the generation direction according to the results of the heuristic function so that generation efficiency can be improved. This paper has the following innovations:
  • A probability model of typical fault for the boundary scan test is established, and a new heuristic function is proposed based on this model to balance the test accuracy and the search efficiency of the algorithm.
  • A method is designed to describe the characteristics of the system under test by using several undetermined parameters, which effectively improves the test precision of the complex circuit system.
  • An improved AO* model with adaptive strategy is proposed to improve the MTV generation efficiency of complex circuit system.
This paper is organized as follows: In Section 2, this paper establishes and analyzes the mathematical model of interconnect short-circuit fault, then this paper identifies the most common types of faults. In Section 3, based on these fault characteristics, this paper gives the mathematical form of the heuristic function in AO* mode. Then, this paper uses the genetic algorithm to determine the parameters in the heuristic function, which are used to describe the characteristics of the actual circuit under test. After obtaining the heuristic function and the parameters, this paper uses the improved AO* model to generate the MTV. In Section 4, this paper uses different algorithms to generate MTV and compare them with the MTV generated by our method from the perspective of priori index and actual test results. Finally, the conclusion is wrapped up in Section 5.

2. Constructing the Probability Model of Typical Faults

During the manufacturing process of large-scale integrated circuit (LSI) systems, virtual soldering, de-soldering, and network short-circuit fault caused by soldering can easily occur. For an integrated circuit system with n networks, the probability of short-circuit fault between any two networks can be described by a symmetric matrix, as shown in Equation (1).
0 p 12 p 1 n p 21 0 p 2 n p n 1 p n 2 0  
The values of matrix elements p i j and p j i are equal, indicating the probability of a short-circuit fault occurring between the network numbered i and the network numbered j, and their values are calculated according to Equation (2).
p i j = a 0 · A 1 L i j L 0     L 0 L i j L M 0     o t h e r w i s e
a 0 is the probability of a short-circuit between the nearest two networks, L 0 is the minimum distance between any two networks, L i j is the distance between net N i and net N j , L M is the maximum physical distance between two nets capable of short-circuit failure, and A is an exponential decay function. The above parameters are determined according to the actual conditions of the integrated circuit system.
In this paper, it is called m-order short-circuit fault when the number of networks participating in the short-circuit fault is m. For a circuit with n networks ( m n ) , if each network is treated as a node of an undirected graph, and if a short-circuit fault occurs between networks, there is an edge between the corresponding nodes, the occurrence of an m-order short-circuit fault in this circuit is equivalent to the formation of a connected graph in which the number of nodes is according to the properties of connected graphs, and the minimum number of edges of m-nodes connected graphs is m − 1 [30,31]. Therefore, the number of possible m-order short-circuit faults is the number of connected graphs with m nodes and m − 1 edges, which equals the number of graphs with m nodes and m − 1 edges minus the number of all non-connected graphs with m nodes and m − 1 edges. Let the number of unconnected nodes in these graphs be t ( 1 t < m ) . According to the graph theory, the remaining mt nodes can form C m t 2 edges at most. If the remaining mt nodes form a graph with at least m − 1 edges, it must satisfy that C m t 2 m 1 , so that t must satisfy the following conditions.
1 t 2 m 1 8 m 7 2
If the largest integer value of t which satisfies Equation (3) is t 0 , and this paper defines the number of graphs which have m − 1 edges and m t 0 nodes as K 0 , then K 0 can be calculated as follows:
K 0 = C C m t 0 2 m 1
Likewise, as this paper defines the number of graphs which have m − 1 edges and m t 0 + 1 nodes as K 1 , K 1 can be calculated as follows:
K 1 = C C m t 0 + 1 2 m 1 C m t 0 + 1 1 · K 0
And similarly, as this paper defines the number of graphs which have m − 1 edges and m nodes as K t 0 , K t 0 can be calculated as follows:
K t 0 = C C m t 0 2 m 1 j = 1 t 0 C m t 0 + j j   · K n j
The probabilities of these K t 0 groups of m − 1 short-circuit faults in each group are taken out from Equation (1) and put into matrix Q m , which is shown in Equation (7). Each line of Q m represents a combination of network short-circuit faults that can cause m-order short-circuit faults, and element q i j is the probability of these network short-circuit faults occurring.
q 11 q 12 q 1 ( m 1 ) q 21 q 22 q 2 ( m 1 ) q K t 0 1 q K t 0 2 q K t 0 ( m 1 )
Considering short-circuit faults between each network as independent events, the probability of m-order short-circuits faults ( P m ) is as follows.
P m = 1 i = 1 K t 0 1 j = 1 m 1 q i j
Setting P m a x to the maximum of short-circuit faults probability q i j , we obtain the following relationship:
P m 1 ( 1 P m a x m 1 ) K t 0
Setting P M m to the upper bound of m-order short-circuit faults probability P m , its value is as follows.
P M m = 1 ( 1 P m a x m 1 ) K t 0
P m a x is a value far less than 1. With 0.001 as the step size of P m a x change, P M m varies with m, as shown in Figure 1.
Equations (4)–(10) are the probability models of typical faults established in this paper. By this probability model, the upper bounds of the probability of short-circuit faults of each order can be calculated. According to the calculation results, this paper analyzes and studies those fault modes with high probability, so as to improve the efficiency of the following algorithms while ensuring the test precision.
As shown in Figure 1, the probability of a fault with order greater than 3 approaches 0, so the short-circuit fault model established in this paper only considers short-circuit faults with order no greater than 3.

3. Proposed Method

3.1. Method Overview

The heuristic function is the key of using the GA-AO* approach to generate MTV. If the calculation of heuristic function is much bigger than the true value, the result of AO* will have a bad performance. On the contrary, if the calculation of heuristic function is much smaller than true value, the efficiency of AO* will become too low to solve such an NP-hard question. In order to have an appropriate heuristic function, firstly, this paper established the model of evaluation index— P M T V . Based on the characteristics of P M T V , this paper determined the mathematical form of heuristic function and used both prior and posterior parameters to describe the question. Among them, the prior parameters were obtained by calculation, and the posterior parameters were obtained by the genetic algorithm (GA) based on the characteristics of the system under test. After obtaining the heuristic function, this paper judges whether the relative error of estimated value of P M T V calculated by the heuristic function is lower than the condition proposed by testers. If it meets the condition, this paper uses it to choose the search direction for the AO* and uses the AO* to generate the MTV. In addition, in order to improve the efficiency of the AO* algorithm, the adaptive strategy is used to improve it. The above process is shown in Figure 2.

3.2. Failure Probability of the Matrix of Test Vectors

The process of interconnect test of the integrated circuit system by boundary scan technique is injecting MTV (matrix of test vectors) and reading MRV (matrix of response vectors), by comparing the difference between them to carry out the fault diagnosis process. A schematic of the structure of the boundary scan test is shown in Figure 3. This architecture is proposed by IEEE1149.1 standard, which is based on JTAG (Joint Test Action Group) interface and BSC (Boundary Scan Cell) [32]. The TDI and TDO ports of the JTAG interface of the chip under test are connected in the form of daisy chain. During each test, the test vectors move into the boundary scan test unit through the TDI serial of each chip, motivating the corresponding pins. After the excitation, the response vectors are displaced from the TDO port of the chip. The whole testing process is controlled by TCK and TMS signals in the form of a bus.
The elements of MTV are logical values of 0 or 1. The rows of the matrix which are called STV (Sequential Test Vector) represent the logical values that are applied to the same network in multiple boundary scan test cycles. The columns of the matrix which are called PTV (Parallel Test Vector) represent vectors composed of logical values that are loaded onto each network during a boundary scan test cycle. MTV is as follows.
a 11 a 12 a 1 m a 21 a 22 a 2 m a n 1 a n 2 a n m
The number of MTV’s rows(n) is equal to the number of networks under test. The number of MTV’s rows(m) is called compactness index, which needs to satisfy the following requirements.
m l o g 2 ( n + 2 )
The rows of MRV are called SRV (Sequential Response Vector). Each SRV is a collection of logical values received on a network in the circuit under test. The columns of MRV are called PRV (Parallel Response Vector). Each SRV is a collection of logical values received from a network in one cycle of the boundary scan test. When short-circuit faults occur between networks, the SRVs received from the fault networks are presented as a result of wired-AND of STVs (wired-AND and wired-OR are dual models. There is only one situation in the same circuit, so this paper only discusses wired-AND here). By observing which networks SRV is the result of corresponding STVs wired-AND, testers can judge which networks have a short-circuit fault.
On this basis, the definition of the short-circuit fault diagnosis through the SRV network with the phenomenon of misjudgment and confusion is as follows.
Misjudgment: When an STV injected into one network is the same as the result of wired-AND of STVs injected into another group of networks. It is not possible to judge whether there is a short-circuit failure between this network and this set of networks. At this point, a misjudgment has occurred on the MTV. As an example, shown in Figure 4, the result of wired-AND of the STV injected into net1 and net2 is the same as the STV injected into net3, when a short-circuit fault occurs between net1 and net2, testers cannot determine whether net3 has a short-circuit fault with them (as shown by the red dotted line), so the misjudgment occurred.
Confusion: When the result of wired-AND of a group STVs is the same as the result of wired-AND of another group STVs (There is no overlap between them). It is not possible to judge whether there is a short-circuit failure between these two groups of networks. At this point, a confusion has occurred on the MTV. As an example, shown in Figure 5, the result of wired-AND of the STV injected into net1, net2, and net4 is the same as the result of wired-AND of STV injected into net3 and net5, when a short-circuit fault occurs between net1, net2, and net4, and a short-circuit fault occurs between net3 and net5. Testers cannot determine whether the first group of nets have a short-circuit fault with the second (as shown by the red dotted line), so the confusion occurred.
Based on the analysis in Section 3.1 of this paper, the fault model considered in this paper is 2-order, 3-order short-circuit fault model. At the same time, it is stipulated that the test vectors generated in this paper are all carried out under the optimal compactness index, that is, the number of columns(m) of MTV is an upward rounding of l o g 2 ( n + 2 ) .
Under this premise, we can divide the phenomenon of misjudgment and confusion in MTV into the following kinds of events:
  • Misjudgment caused by 2-order short-circuit: the result of wired-AND of 2 STVs is the same as another STV.
  • Misjudgment caused by 3-order short-circuit: the result of wired-AND of 3 STVs is the same as another STV.
  • Confusion caused by 2-order short-circuit: the result of wired-AND of 2 STVs is the same as the result of wired-AND of other 2 STVs.
Definition: The failure probability of MTV ( P M T V ) is the probability of the above three events in a set of STVs. Let S be the set of STVs. Let power set A 2 S , and A = 2 . Let power set B 2 S , and |B| = 3. Let power set C 2 A , and |C| = 2, it can be calculated by the following equation.
P M T V = 1 S T V i 1 , S T V i 2 A ( 1 k i 1 i 2 · p i 1 i 2 ) · S T V i 1 , S T V i 2 , S T V i 3 B ( 1 k i 1 i 2 i 3 · p i 1 i 2 i 3 ) · ( S T V i 1 , S T V i 2 ) , ( S T V i 3 , S T V i 4 ) C ( 1 k i 1 i 2 i 3 i 4 · p i 1 i 2 · p i 3 i 4 )
p i 1 i 2 is the probability of 2-order short-circuiting fault between networks i1 and i2. p i 1 i 2 i 3 is the probability of 3-order short-circuit fault between networks i1, i2, and i3. When the 2-order short-circuit between i1 and i2 causes misjudgment, k i 1 i 2 is 1, otherwise it is 0. When the 3-order short-circuit between i1, i2, i3 causes misjudgment, k i 1 i 2 i 3 is 1, otherwise it is 0. When the 2-order short-circuit between i1 and i2 and 2-order short-circuit between i3 and i4 causes confusion, k i 1 i 2 i 3 i 4 is 1, otherwise it is 0.
Since different networks have different short-circuit probabilities, and each network corresponds to an STV in MTV, and if each STV in MTV is treated as a unit of a sequence, the whole MTV is treated as a sequence, then the generation of MTV problem with minimum P M T V will transform into the optimal cost sequence search problem.

3.3. Heuristic Function Based on the Characteristics of MTV

The generation of MTV using AO* model includes forward searching and backward tracing. In the forward searching, let the test vector matrix composed of STVs from the first row to row i be a sub-matrix M T V i , as shown in Equation (14).
M T V n M T V i M T V 2 M T V 1 { a 11 a 12 a 1 m a 21 a 22 a 2 m a i 1 a i 2 a i m a n 1 a n 2 a n m
The heuristic function f ( M T V i ) will calculate the P ^ M T V i (estimated P M T V ) of the sub-matrix M T V i , then this paper will choose the M T V i with least P ^ M T V i as a direction of searching. P ^ M T V i is calculated by Equation (15).
It represents an estimate of the P M T V of the MTV after completing the remaining n−i rows if the previous i-row STVs are M T V i .
P ^ M T V i = P M T V i + f M T V i P M T V i · f M T V i
The implication of the f ( M T V i ) is to estimate the P M T V of the MTV after generation based on the information of STVs in former i row, that is, to evaluate the impact of the STVs in former i row in the future. According to the analysis of Section 3.2, for a given STV, its effect on P M T V can be divided into three types of events:
  • The result of wired-AND between it and other STVs is the same as other STVs in latter n−i rows, thus leading to misjudgment.
  • The result of wired-AND of other STVs (at least one of those STVs is from latter n−i row) is the same as it, thus leading to misjudgment.
  • The result of wired-AND between it and another STV is the same as the result of wired-AND of another two STVs (at least one of those three STVs is from latter n−i row), thus leading to confusion.
These events can be divided into 13 cases, depending on whether STVs belong to the former i row or latter n−i row, and the order of wired-AND. For a given STV, each case is independent. Let f j k be the estimate of influence on P M T V of the case k ( 1 k 13 ) of S T V j (the row j of M T V i ). Then, f ( M T V i ) can be represented by the following Equation (16).
f M T V i = j = 1 i k = 1 13 f j k
According to the analysis of the 3.2, the effect of each case on P M T V is represented by P M T V times ( 1 P k ) . Under the premise of randomly assigning STV, P k is the probability that case k will occur according to the classical probability. At the same time, for a given S T V j , there are different random combinations that make the case k occur, and the occurrence of these combinations is independent of each other, If the number of these combinations is D j k , then the effect of P M T V is the product of all the results, which is ( 1 P k ) D j k . Considering the characteristics of the different circuits, it is necessary to add parameters β to describe the characteristics of the circuits in each case, so the final form of f j k is as follows:
f j k = ( 1 β k · P j k ) D j k
For a n × m MTV and each of its sub-matrix M T V i , set N a = 2 m 2 , N a denotes the number of all types of STV with length m, that is, the number of 0/1 sequences with length m. Set N s = 2 m 2 i , N s denotes the number of available STV types left when the former i rows have been set. Set N e = n i , N e denotes the number of STVs waiting to be set. N j 1 is the number of 1 in S T V j , N j 0 is the number of 0 in S T V j , the calculation and range of P j k and D j k in Equation (17) are shown in Table 1. For a sub-matrix M T V i , firstly, this paper calculates its N a , N s , and N e according to i. Then, this paper counts the number of 1 and 0 in each row of M T V i from the row 1 to the row i to obtain N j 1 and N j 0 . Using the parameters above, P j k and D j k can be calculated from Table 1. When out of the range shown in the table below, f j k = 1, indicating that case k cannot occur at this time and has no effect on P M T V .

3.4. Parameter Determination Method of Heuristic Function Based on Improved Genetic Algorithm

After the analysis of Section 3.3, this paper establishes the heuristic function with 13 parameters. These parameters are used to describe the characteristics of the circuit under 13 different fault cases. In this section, this paper will use the improved genetic algorithm to determine the value of these parameters. For circuits under test with network number of n, this paper randomly generates a large number of MTVs. For each MTV, this paper calculates the P ^ M T V i for each of its sub-matrices M T V i   ( 1 i n ) in turn, and averages the P ^ M T V i of all the M T V i , so that this paper can obtain a function F ( i ) which is only related to i. According to Equation (17), P ^ M T V contains 13 undetermined parameters β ; these parameters can be determined by fitting F ( i ) , for F ( i ) includes the P M T V i of the sub-matrix M T V i itself and the estimated impact on P M T V . For each MTV, this paper will calculate its P M T V as well as P M T V n i of its sub-matrix M T V n i , so that we can obtain the objective function G ( i ) that is shown as Equation (18).
G i = 1 1 P ¯ M T V ( 1 P ¯ M T V i ) · ( 1 P ¯ M T V n i )
This paper treats the 13 parameters in F ( i ) as a vector B k , and each B k is treated as an individual of the genetic algorithm. The fitness function of B k is shown in Equation (19).
H ( B k ) = i = 1 n ( F i G ( i ) ) 2
In the iterative process of the genetic algorithm, this paper uses the roulette wheel strategy to extract the offspring and uses the elite retention strategy to avoid the loss of the optimal individuals in the iterative process.
The optimization result of traditional genetic algorithm often depends on the selection of the initial population. Because of the randomness of the initial value selection, it often leads to the problem of the difference of the final optimization result and the slow convergence rate. Therefore, this paper proposed an improved scheme for the iteration termination condition. Because the elite reservation policy is used, the optimal solution of the offspring is always less than or equal to the optimal solution of the parent; if the best individual of the offspring is equal to the best individual of the parent in continuous generation c (initial value of c is 0), then the whole mutation operation is performed on the rest of the offspring. According to the characteristics of the genetic algorithm, the population will converge gradually with the progress of the algorithm, so if the iterated algebra is c a , then the probability of mutation of each individual ( P c ) is shown as Equation (20):
P c = 1 c c a
If the optimal individual is [ β 0 1   , β 0 2   β 0 13   ] and the other is [ β i 1   , β i 2   β i 13   ] , the 13 parameters in another individual are mutated in sequence as shown in Equation (21).
β i j = β i j + | β i j β 0 j | β i j · k i j
Let k i j be a random parameter subject to normal distribution, if β i j β 0 j , the range of k i j is [0, β 0 j ]. Otherwise, the range of k i j is [− β 0 j , 0]. Set the number of termination iterations to c e n d , when c e n d iterations occur, the algorithm is completed. The optimal individual in the final offspring is the value of β k in Equation (17), and the flow of the algorithm is shown in Algorithm 1.
Algorithm 1. The flow of determining parameters of heuristic function by genetic algorithm
Procedure
Step 1Randomly generate n × ( 2 m 2 ) groups of MTVs of n rows and m columns. Then, calculate the f ( M T V i ) for the sub-matrixes M T V i of each MTV from i = 1 to i = n − 1. Average all of the f ( M T V i ) , so that we can obtain F ( i ) in Equation (19).
Step 2Calculate the P M T V i of sub-matrixes M T V i which is consists of the former i rows of each MTV. Calculate the P M T V n i of sub-matrixes M T V n i which is consists of the latter n−i rows of each MTV, Calculate the P M T V of each MTV. Average them in turn, so that we can obtain P ¯ M T V i ,   P ¯ M T V n i and P ¯ M T V in Equation (18), then we can obtain G i .
Step 3Average all the elements in the Equation (1) except diagonal elements and set the result as P ¯ . For the circuit with n networks, randomly generate C n 2 individual, each individual B k is a vector like [ β k 1   , β k 2   β k 10   ] , the value of β k i is a random number in [ 0 ,   P ¯ ] . Calculate H ( B k ) of each B k by Equation (19).
Step 4Randomly cross the 80% of individual in parents to generate the offspring. According to the number of times that the best individual of the offspring is equal to the best individual of the parent generation, calculate the probability of mutation P c , and use P c to judge whether each of individual need mutation. For those which need mutation, this algorithm will operate them by Equation (20).
Step 5sort the offspring and the parent generation and determine whether the best individual of the offspring is equal to the best individual of the parent, If the answer is yes, add c of Equation (20) to 1, otherwise set c to 0.
Step 6When the number of iterations is c e n d , the algorithm terminates, and the best individual in the offspring is the value of β in Equation (17).

3.5. The Generation of MTV by Improved AO* Model

After the parameters β are determined, this paper will use the data of the circuit under test to judge whether the relative error of estimated value of P M T V calculated by the heuristic function meets the condition of the testers. If the result does not meet the condition, this paper will regenerate parameters by setting the initial values to these time results. Otherwise, this paper will use AO* model to search MTV heuristically. In order to improve the generation searching, this paper makes several improvements to the AO* model.
  • Set the P M T V of the MTVs needed to be optimized as P m i n , which is the upper bound of the search. For the search process, the search path with P ^ M T V i bigger than P m i n will not continue to search.
  • In order to avoid the influence of the multi-optimal solution problem, this paper uses adaptive method to consider both search efficiency and low P M T V of the solution. This paper sets the meet-threshold θ according to the upper bound of the search and use the depth-first strategy to search. When the ratio of P M T V of a solution to P m i n is less than or equal to θ , the algorithm ends. At the same time, this paper sets the threshold number of searches to c s . When cumulative number of searches reach c s , this paper adjusts θ according to Equation (22).
    θ = c s + 1 c s · θ
Based on the above improvement, the whole algorithm flow is as follows:
Step 1: According to the P_MTV of the MTVs needed to be optimized, set the P m i n ,   θ and c s .
Step 2: Create the root node of the search tree; the root node contains all possible types of the sub-matrix M T V 1 , each of which corresponds to a search direction.
Step 3: Calculate the f ( M T V 1 ) of each type of M T V 1 , then calculate the P ^ M T V 1 of each type of M T V 1 . Ban the direction of those M T V 1 whose P ^ M T V 1 is bigger than P m i n . Find the M T V 1 with least P ^ M T V 1   and set it as the direction to expand. Create the next node for M T V 2 , as the same model, and so on, until the node for M T V n is reached.
Step 4: When the number of layers of MTV corresponding to a node is n, it means one search is finished and we obtain a solution. Calculate the P M T V of these M T V n s, find the least P M T V , and calculate the ratio of P M T V to P m i n . If the ratio is equal to or less than θ , the algorithm ends, and the M T V n with least P M T V is the final solution. Otherwise, if the cumulative number of searches reaches the c s , this algorithm adjusts the θ by Equation (22).
Step 5: If the algorithm is not finished, trace up the parent node and change the each P ^ M T V i of M T V i type to their next node’s P ^ M T V i + 1 . Find the MTV with the least P M T V , and set its direction as the direction needed to expand. If the direction is not changed, continue to trace up. Otherwise, this algorithm will expand in a new direction. If the search tree traces up to the root node, the algorithm ends and, according to the direction of root node, the M T V n with least P M T V is the final solution.
The above steps can be represented by a flow diagram (Figure 6).
The running process of traditional AO* algorithm is a backtracking search process. In the worst case, its time complexity is close to the enumerated type. For the searching of an n × m -scale MTV, the worst time complexity is O ( n ! ). The method of this paper introduces adaptive method and depth-first strategy, through observing the result of every c s searching, the termination condition of the algorithm is adjusted adaptively. The worst time complexity of each searching is n · ( 2 m 2 ) . Under the optimal compactness index, m is up rounding of l o g 2 n + 2 . So, the time complexity of this method is O ( c s · n 2 ). The paper’s improvement of AO* algorithm speeds up the efficiency of searching of MTV for large-scale questions, and the process is offline, so it does not affect the actual test efficiency.

4. Experiments and Results

To test our method’s optimization for P M T V , this paper used Particle Swarm Optimization Algorithm (PSO), Walk-1 Algorithm, and our method to generate MTVs, and used them to carry out the boundary scan test on the same module under test which is developed by our laboratory. In this test, this paper set the relative error of estimated value of P M T V lower than 10%. The module under test is shown in Figure 7a; it consisted of 3 ICs, including an XC7K325T FPGA, an XC7Z045 FPGA, and a JYCSW1848 CPU. All chips are powered by power modules that allow them to work properly. The circuit under test contains a total of 123 networks and 371 pins. A total of 158 pins of those ICs are connected to the headers, so that testers can inject the shorted-circuit fault they need by using jumper cable to connect the pins of the networks. There are 87 testable networks, covering 71% of all networks. By connecting the JTAG port of the module to our boundary scan test system, which is shown in Figure 7b, testers can do a boundary scan test on it with MTVs generated by this paper.

4.1. PMTV of Different Algorithms

This paper randomly selects 20 networks from all testable networks and numbers them. Then, this paper calculates their probabilities of shorted circuit by Equation (2). The probabilities are arranged into a matrix in the form of Formula (1), which is shown as Table 2.
After the probability of shorted circuit is obtained, according to the description in Section 3.4; this paper used the improved genetic algorithm to determine the parameters β k of the heuristic function in GA-AO* approach. This paper set c e n d to 5000. After iteration, the final value of β k is shown in Table 3.
The estimated P M T V and actual P M T V under each order of sub-matrix is shown in Figure 8, with an average relative error of 6.9%. The results show that our heuristic function has good estimation ability for P M T V .
This paper used these three algorithms to generate MTVs according to the probability of shorted circuit in Table 2. The codes of these algorithms were implemented on MATLAB 2020. The CPU type of the computer running codes was “Intel (R) Core (TM) i7-10750H CPU@2.60 GHz”. All algorithms generated MTVs for the same networks under optimal compactness, which means this paper set the number of columns of MTVs as the rounding up of l o g 2 ( n + 2 ) (n is the number of networks under test). This paper set the P M T V of MTVs which is generated by PSO as the initial value of P m i n . Finally, this paper set θ to 80% and c s to 100. PSO and Walk-1 are implemented according to the ways and parameters provided in reference [16] and reference [17], respectively. Under these conditions, this paper observed the changes of P M T V of the three algorithms by changing the number of networks under the boundary scan test and evaluated the P M T V . When the number of networks is 5, 10, 15, and 20, respectively, the P M T V of the MTVs generated by three algorithms are shown in Table 4.
The P M T V of the MTVs generated by the three algorithms varies with the number of networks as shown as Figure 9.
As can be seen from Table 4 and Figure 9, all three algorithms can generate fault-free MTVs when the number of networks is small. With the increase in network size, the P M T V of MTV generated by Walk-1 algorithm increases significantly because of fixed compactness index, while the MTVs generated by PSO and by our method can still maintain a low P M T V . At the same time, because we take the P M T V of the MTVs generated by the PSO as P m i n of our method, the P M T V of the MTVs generated by our method is always less than or equal to the P M T V of the MTVs generated by the PSO, so our method realizes the optimization. When the number of networks is 20, the running time of the three algorithms is 0.074 s, 248 s, and 1756 s. For the actual test, the generation of MTV for the same type of circuit is one-time and offline, so the generation time of MTV will not affect the test efficiency basically.

4.2. Test Performance of Different Algorithms

In order to test the performance of MTVs generated by three algorithms in the actual boundary scan test, we actually inject these faults into the module under test by connecting the corresponding jumper cables and using the MTVs generated by these three algorithms to do the boundary scan test on it. We use the method of weighted sampling to extract the shorted-circuit fault to be injected from Figure 4. Each time, we will extract one or two faults to simulate the 2-order and the 3-order short-circuit fault. The weight of a 2-order or a 3-order short-circuit fault is the ratio of the probability of it and the sum of all the probabilities of all the 2-order and 3-order shorted faults. After injecting the faults extracted, we connect the JTAG of the module to our boundary scan test system EasyScan-USB IEEE 1149.1 and use the system to inject the MTVs. For each algorithm, we do the 200 experiments. The rates of misjudgment or confusion in the test using MTVs generated by each algorithm are shown in Table 5. The results show that the MTVs generated by our method are less frequently misjudged or confused than those generated by walk-1 and PSO. It shows, from a posterior perspective, that our MTVs have a lower failure rate when tested.

5. Conclusions

In this paper, a method of generating boundary-scan MTV by combining the genetic algorithm and improved AO* model is proposed, which effectively solves the problem of optimizing the P M T V of MTV under the optimal compactness index. We use walk-1, PSO, and our method to generate MTVs for the same module and calculate the P M T V of each MTV. At the same time, we also used these MTVs for the actual boundary scan test. Based on the analysis and experiments, we can draw the following conclusions:
  • Compared with the MTVs generated by Walk-1 and PSO, the MTVs generated by our method have lower PMTV, and MTVs generated by our method have lower apriorism probability of misjudgment and confusion in the boundary scan test.
  • Through the experiment of fault injection based on probability of shorted circuit, it is shown that the MTVs generated by our method have lower fault incidence than those generated by walk-1 and PSO. The MTVs generated by our method have lower failure rate from a posteriori point of view.
Our research can be used to generate MTV in the boundary scan test and to optimize the P M T V of existing MTVs. It has certain practical value. In the future, we will do more research on the generation of larger MTVs and adaptive optimization with failure rate and compactness.

Author Contributions

Conceptualization, Y.S. and X.G.; methodology, X.G. and H.L.; software, X.G. and J.W.; writing—original draft preparation, Y.S. and X.G.; writing—review and editing, H.L. and Z.L.; visualization, H.L. and X.G.; supervision, Z.L.; project administration, Z.L.; funding acquisition, Z.L. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported by the Project of Sichuan Youth Science and Technology Innovation Team, China (Grant No. 2020JDTD0008).

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

The original contributions presented in the study are included in the article, further inquiries can be directed to the corresponding authors.

Conflicts of Interest

The authors declare no conflicts of interest.

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Figure 1. The upper bound of m-order short-circuit fault probability under different P m a x conditions.
Figure 1. The upper bound of m-order short-circuit fault probability under different P m a x conditions.
Applsci 14 02410 g001
Figure 2. The process to establish the heuristic function and generate the MTV.
Figure 2. The process to establish the heuristic function and generate the MTV.
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Figure 3. The structure of the boundary scan test.
Figure 3. The structure of the boundary scan test.
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Figure 4. An example of misjudgment.
Figure 4. An example of misjudgment.
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Figure 5. An example of confusion.
Figure 5. An example of confusion.
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Figure 6. The flow diagram of heuristic search using the improved AO*.
Figure 6. The flow diagram of heuristic search using the improved AO*.
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Figure 7. (a) The module under test; (b) Boundary scan test system.
Figure 7. (a) The module under test; (b) Boundary scan test system.
Applsci 14 02410 g007
Figure 8. The estimated P M T V and actual P M T V under each order of sub-matrix.
Figure 8. The estimated P M T V and actual P M T V under each order of sub-matrix.
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Figure 9. The P M T V of MTVs generated by the three algorithms with the change in number of networks.
Figure 9. The P M T V of MTVs generated by the three algorithms with the change in number of networks.
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Table 1. The calculation and range of P j k and D j k .
Table 1. The calculation and range of P j k and D j k .
k D j k P j k Range
1 C N a 2 N s 2 C N a N s · C N s 2 N e 2 C N s N e t = 1 N j 1 2 C N j 1 t N j 1 3
2 C N a 3 N s 3 C N a N s · C N s 3 N e 3 C N s N e t = 1 N j 1 3 u = 1 N j 1 t 2 C N j 1 t · C N j 1 t u N j 1 4
3 C N a 2 N s 2 C N a N s · C N s 2 N e 2 C N s N e t = 1 N j 0 1 C n t N j 0 3
4 C N a 3 N s 3 C N a N s · C N s 3 N e 3 C N s N e t = 2 N j 0 1 u = 1 t 2 C n t · C t u N j 0 4
5 C N a 4 N s 4 C N a N s · C N s 4 N e 4 C N s N e t = 2 N j 1 1 u = 1 t + N j 1 2 ( C N j 0 t · C t + N j 1 u 1 ) N j 1 1
6 C N a 1 N s 1 C N a N s · C N s 1 N e 1 C N s N e 1 N j 1 < n
7 C N a 2 N s 2 C N a N s · C N s 2 N e 2 C N s N e t = 1 N j 1 2 C N j 1 t 1 N j 1 3
8 C N a 2 N s 2 C N a N s · C N s 2 N e 2 C N s N e t = 1 N j 0 1 C N j 0 t N j 0 2
9 C N a 1 N s 1 C N a N s · C N s 1 N e 1 C N s N e 1 N j 0 1
10 C N a 2 N s 2 C N a N s · C N s 2 N e 2 C N s N e t = 1 N j 0 2 C N j 0 t 1 N j 0 3
11 C N a 3 N s 3 C N a N s · C N s 3 N e 3 C N s N e t = 2 N j 0 1 u = 1 t 2 C n t · C t u N j 0 4
12 C N a 4 N s 4 C N a N s · C N s 4 N e 4 C N s N e t = 2 N j 0 1 u = 1 t + N j 0 2 ( C N j 1 t · C t + N j 0 u 1 ) N j 0 1
13 C N a 1 N s 1 C N a N s · C N s 1 N e 1 C N s N e 1 N j 0 < n
Table 2. The probability of shorted circuit (×10−5).
Table 2. The probability of shorted circuit (×10−5).
Net1234567891011121314151617181920
10.006.378.566.687.983.135.985.185.492.863.243.275.565.898.555.677.665.786.617.92
26.370.004.748.155.971.174.889.604.215.333.768.086.636.477.297.244.833.243.151.85
38.564.740.003.767.763.725.215.751.506.285.895.363.854.657.376.542.734.470.556.37
46.688.153.760.003.475.426.551.893.366.944.133.433.302.436.153.566.095.199.647.08
57.985.977.763.470.006.144.082.853.283.952.164.581.654.595.045.608.756.905.078.08
63.131.173.725.426.140.001.883.573.854.985.104.295.688.114.207.979.314.462.965.08
75.984.885.216.554.081.880.001.085.983.854.464.734.183.903.100.674.098.174.232.83
85.189.605.751.892.853.571.080.006.785.095.991.537.023.495.045.809.946.327.598.55
95.494.211.503.363.283.855.986.780.006.579.104.841.926.491.553.381.831.466.018.25
102.865.336.286.943.954.983.855.096.570.004.654.072.964.944.832.213.164.955.354.57
113.243.765.894.132.165.104.465.999.104.650.003.154.276.891.755.362.694.504.186.34
123.278.085.363.434.584.294.731.534.844.073.150.004.364.505.244.988.536.564.025.77
135.566.633.853.301.655.684.187.021.922.964.274.360.004.385.076.548.512.904.527.18
145.896.474.652.434.598.113.903.496.494.946.894.504.380.004.136.232.954.912.845.36
158.557.297.376.155.044.203.105.044.203.105.041.554.834.130.005.533.814.623.979.25
165.677.246.543.565.607.970.675.607.970.675.803.382.215.365.530.005.041.835.263.31
177.664.832.736.098.759.314.098.759.314.099.941.833.162.698.535.040.002.463.204.03
185.783.244.475.196.904.468.176.904.468.176.321.462.904.914.621.832.460.007.736.83
196.613.150.559.645.072.964.235.072.964.237.596.014.522.833.975.263.207.730.006.09
207.921.856.377.088.085.082.838.558.254.576.345.777.185.369.253.314.036.836.090.00
Table 3. Actual values of β k .
Table 3. Actual values of β k .
k1345678910111213
Value
( 10 4 )
1.1572.0760.2110.0070.2732.6780.0010.0020.0010.0020.0010.001
Table 4. The P M T V of each algorithm under different number of networks under test.
Table 4. The P M T V of each algorithm under different number of networks under test.
Number of NetworksWalk-1PSOOur Method
50 3.47 × 10 5 0
10 6.05 × 10 4 4.10 × 10 4 1.85 × 10 4
150.00240.0016 3.16 × 10 4
200.00680.00300.0021
Table 5. The rates of misjudgment or confusion in the test using MTVs generated by each algorithm.
Table 5. The rates of misjudgment or confusion in the test using MTVs generated by each algorithm.
Number of TestsWalk-1PSOOur Method
5048.3%34.1%27.4%
10044.1%33.2%26.5%
15047.6%34.3%26.6%
20045.7%34.1%26.3%
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Su, Y.; Guo, X.; Luo, H.; Wang, J.; Liu, Z. A Boundary Scan Test Vectors Optimization Method Based on Improved GA-AO* Approach Considering Fault Probability Model. Appl. Sci. 2024, 14, 2410. https://doi.org/10.3390/app14062410

AMA Style

Su Y, Guo X, Luo H, Wang J, Liu Z. A Boundary Scan Test Vectors Optimization Method Based on Improved GA-AO* Approach Considering Fault Probability Model. Applied Sciences. 2024; 14(6):2410. https://doi.org/10.3390/app14062410

Chicago/Turabian Style

Su, Yuanzhang, Xinfeng Guo, Hang Luo, Jingyuan Wang, and Zhen Liu. 2024. "A Boundary Scan Test Vectors Optimization Method Based on Improved GA-AO* Approach Considering Fault Probability Model" Applied Sciences 14, no. 6: 2410. https://doi.org/10.3390/app14062410

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