1. Introduction
The growing diffusion of the Internet of Things (IoT) [
1,
2] involves the embedding of integrated circuits (ICs) into objects to acquire, process, and exchange useful information. This requires the development of mixed-signal ICs that typically integrate a sensor, analog front-end, analog-to-digital converter (ADC), digital processing, and a simple wireless transceiver [
3,
4,
5,
6]. Together with area minimization and reconfigurability, one of the strongest constraints is on power consumption: these systems often have to operate for years from tiny batteries or by harvesting energy from the environment; thus, an extremely low power consumption is required. Since in many applications IoT sensor nodes have to be energy autonomous, they have to scavenge energy from the environment by means of photovoltaic cells, thermoelectric generators, and vibration sensors. Operating with this kind of energy harvesting system requires the minimization of the supply voltage, and circuits operating with supply voltages as low as 0.3 V are suitable to properly operate with such harvesting sources [
7,
8,
9].
The operational transconductance amplifier (OTA) is a fundamental building block to design analog front-ends, allowing for the implementation of amplification and filtering functions needed in IoT and biomedical applications. In this regard, several OTAs have been proposed in recent work, which allow for the attainment of good performance working with supply voltages as low as 0.3 V [
10,
11,
12,
13,
14,
15,
16,
17,
18,
19]. These solutions are almost all based on body-driven (BD) input stages which, at such low supply voltage, allow them to reach rail-to-rail input common mode range (ICMR) and exploit gate-biased techniques in order to assure well-defined dc bias point and good robustness against process, supply voltage, and temperature (PVT) variations. In addition, due to the aggressive supply voltage scaling and due to the effectiveness of the deep sub-threshold region in which the most of these architectures work, the performance of recent ultra-low voltage (ULV) OTAs can be considered state-of-the-art in terms of gain bandwidth product and slew rate normalized to the power consumption.
However, such OTA topologies rely on a full custom design approach and, even if the analog part is often only a small fraction of the whole system, it requires a large design effort, with a negative impact on design times and costs, which are very important aspects in the context of IoT nodes development. This is because both the schematic and the layout design phases are typically carried out manually, iterating each step repeatedly until specifications are met with good robustness under PVT variations and mismatches. To overcome this problem and reduce both costs and time-to-market, a design methodology for analog circuits defined as synthesizable analog design has been introduced in [
20]. In this design approach, all circuit building blocks are implemented through standard-cells taken from the digital library and coded in a hardware description language, which can then be synthesized from commercial standard-cell libraries and automatically placed and routed using electronic design automation (EDA) tools. Compared to conventional analog implementations, standard-cell-based analog implementations significantly shorten the design time and cost [
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32].
In the context of the design of standard-cell-based amplifiers, researchers have recently focused on automatic place-and-route strategies for standard-cell-based circuits, typically adopted in the digital design flow, to implement fully-synthesizable analog circuits and drastically reduce the area usage of analog building blocks [
33]. Research studies are investigating both the use of a digital approach to implement analog functions [
20,
34] and the design of analog blocks exploiting digital standard-cells [
22,
25,
35,
36]. In the latter case, digital gates are used as basic blocks to design analog functions, with the goal of exploiting both the automatic place-and-route steps of the digital design flow and, in particular, a fully automatic synthesis flow of the analog part together with the digital one.
On the one hand, different approaches to mimic the behavior of the OTA through digital-based architectures have been proposed, such as the VCO-based OTA [
37,
38] and the fully-digital OTA (DIGOTA) [
39,
40,
41] approaches. On the other hand, several inverter-based OTA architectures [
42,
43,
44] have been proposed in the literature to allow operation at low supply voltages [
15,
16,
17,
22,
45,
46,
47,
48,
49,
50]. The design of standard-cell based OTAs [
29,
33,
40,
51,
52] is the direct evolution of this approach, with some added constraints due to the fact that optimization at the transistor level is not allowed. Differently from custom-designed inverters, the standard-cell inverter is typically optimized for digital operation, e.g., to achieve symmetrical slew rate, and this results in a systematic offset in the dc transfer function [
52,
53]; moreover, as pointed out in several papers, the performance and even the operation of standard-cell-based analog circuits are severely impaired by PVT and mismatch variations, resulting in incorrect bias, large offsets, and significant performance variations [
46,
47,
53,
54,
55,
56,
57].
To cope with these issues, approaches that exploit body biasing of the standard-cells, together with a custom-designed body bias generator, have been proposed in the literature [
45,
58,
59]. However, these solutions require the availability of the body terminals: this is common in modern technologies, where body biasing is exploited to compensate for PVT variations in digital circuits [
60,
61], but it is not compatible with older technologies often used for analog designs. Moreover, the limited gain of the body input could require control voltages beyond the supply rails to cope with large bias point variations. A different solution has been proposed in [
52], which presents a basic amplifier cell where an auxiliary inverter or one input of a two-input logic gate is driven by a fully-standard-cell replica bias loop to stabilize the bias point.
In this work, we present improvements to two analog building blocks that have been previously presented in [
33,
52]. More specifically, we propose a novel standard-cell-based basic voltage amplifier cell that exploits the same biasing strategy as in [
52], based on a replica loop to control the output dc voltage, but exhibits a gain approximately equal to an integer factor
k (i.e., the number of inverters in parallel) and a low output impedance. We also present a modified version of the D2S introduced in [
33], in which a novel error amplifier topology is adopted in the feedback loop. A further contribution of the present paper is the OTA architecture, which combines all of these building blocks into a multi-stage fully synthesizable amplifier.
The paper is structured as follows:
Section 2,
Section 3 and
Section 4 present the proposed improved standard-cell-based analog building blocks, while the OTA architecture and design guidelines are reported in
Section 5 and
Section 6, respectively. Simulation results are presented in
Section 7, a comparison against other ULV OTAs taken from the literature is presented in
Section 8, and finally some conclusions are reported in
Section 9.
2. Replica Bias Approach to Control the Static Output Voltage of Inverters
This section briefly reviews the standard-cell-based replica-bias control loop presented in [
52] to accurately set the output static voltage of the inverter gates exploited as basic amplifier (BA) cells [
52].
The replica-bias control loop is depicted in
Figure 1 and is composed of an instance (
) of a reference inverter taken from the standard-cell library of the target technology. The input of the inverter
is biased at a voltage equal to the analog ground
(i.e.,
). The output static voltage of
is compared with a reference voltage
(usually equal to
) through the standard-cell-based error amplifier composed of the inverters
(depicted in green in
Figure 1). The generated output voltage, namely
, is used to close the negative feedback loop through another instance
of the reference inverter. Referring to the approach presented in [
52], the BA cell is implemented by the inverters
and
(depicted in pink in
Figure 1). The control voltage
is then applied to all the BA cells exploited for analog design in order to guarantee a well-defined output static voltage of the BA cells in spite of PVT variations [
52]. The reference inverter can be thought to be the minimum-sized inverter taken from the standard-cell library. However, since in the context of analog design, minimum-sized inverters exhibit very high mismatch (resulting in unacceptable offset for most analog applications), the reference inverter is here defined as an inverter gate taken from the standard-cell library whose area is the minimum one that allows it to achieve an acceptable matching performance for the specific analog design. For example, referring to a 130-nm CMOS technology, the area of the reference inverter to be used to design standard-cell-based OTAs is typically 10 times larger than the area of the minimum-sized one (e.g., ×20 instead of ×2).
3. A Standard-Cell-Based Amplifier Cell with Stable Voltage Gain and Well-Defined DC Output Voltage
In this section, we introduce a novel standard-cell-based analog building block that can be easily designed to exhibit a voltage gain, approximately equal to an integer number k, which remains stable over PVT variations. Additional requirements of this basic voltage amplifier are to exhibit a well-defined output static voltage to allow easy cascadability and to provide a low output impedance.
The schematic of the proposed standard-cell-based basic voltage amplifier is depicted in
Figure 2 and is made up of three inverters,
, implemented by a certain number of reference inverters. Symbols ‘1’ and ‘
k’ in the left part of
Figure 2 indicate the number of instances of the reference standard-cell inverter connected in parallel. In particular, the gain is set by inverter
, composed of
k reference inverters in parallel, and the diode-connected inverter
, which is a single instance, whereas inverter
(also a single instance) is exploited to set the static output voltage through the replica-bias loop of
Figure 1. The overall voltage gain
of the cell is thus approximately
, hence we adopt for it the symbol in the right part of
Figure 2, where the label
indicates the voltage gain and where the pin
is the bias control input. We would like to point out that one important feature of the proposed standard-cell-based basic voltage amplifier is that its gain is set (at least as a first order approximation) by the number of reference inverters in parallel used to implement the inverter
in
Figure 2, and it is therefore technology independent.
The proposed basic voltage amplifier can be analyzed by referring to the small-signal equivalent circuit reported in
Figure 3, where:
are the transconductance, the output resistance, the input capacitance, and the output capacitance of the amplifier, respectively. Small-signal parameters
,
,
, and
of the inverter gates are expressed as in [
52].
Remembering that
is implemented as
k instances in parallel in the reference inverter and
is a single instance of the reference inverter, we can write:
where
,
,
, and
denote the transconductance, the output conductance, the gate–source capacitance, and the gate–drain capacitance of the reference inverter, respectively. Now, considering the small-signal equivalent circuit in
Figure 3 and assuming a generic load capacitance
at the output of the amplifier, the transfer function of the proposed basic amplifier can be expressed as:
It has to be remarked that the proposed amplifier shows a low output impedance
whose value is approximately determined by
. The voltage gain of the amplifier is given by
and can be written as:
Assuming
,
can be expressed as:
This condition can be considered true until
k is not high enough to compromise the assumption
. For larger values of
k, the following expression has to be considered:
which, denoting with
the intrinsic voltage gain of the reference inverter, can be rewritten as:
It is evident from the above equation that the voltage gain of the proposed basic amplifier approaches
k only if
. Hence, the limit of the approach is related to the intrinsic gain of the reference inverter, which is technology-dependent and tends to become lower and lower for short-channel CMOS technologies. In order to account for this issue, in the following we consider values of
k that satisfy the relation:
Since
is typically on the order of 10 V/V in modern CMOS technologies, Equation (
14) is not appropriate even for low values of
k, and the more accurate Equation (
12) should be preferred.
Another important feature of the amplifier in
Figure 2 is that, due to its low output resistance, it can be cascaded several times to achieve high voltage gain without requiring frequency compensation, as will be better shown in the following. Indeed, the dominant pole of the proposed amplifier is given by:
and is a high-frequency pole since
,
, and
are low (
coincides with
when several basic amplifiers are cascaded). As a consequence, if the value of
k is appropriately chosen (i.e., to have parasitic poles far from the gain–bandwidth product of the amplifier), the cascade of several instances of the proposed basic voltage amplifier can be compensated through the output load capacitance, without requiring complex frequency compensation approaches needed in conventional multi-stage amplifiers.
4. The Proposed Inverter-Based D2S Converter with Enhanced Common Mode Rejection
Inverter-based OTAs require a differential-to-single-ended (D2S) converter that determines the overall common mode rejection ratio (CMRR) and input common mode range (ICMR) of the amplifier. In the context of inverter-based OTAs, the conventional approach to implement the D2S converter exploits an inverter that drives another inverter whose input and output terminals are connected to each other, thus obtaining a voltage gain approximately equal to −1 [
59]. However, due to the poor matching and the low intrinsic gain of the inverters, this approach results in poor CMRR performance and high sensitivity to PVT variations if the bias point is not properly stabilized. Recently, a novel topology of an inverter-based D2S converter, exploiting an auxiliary, standard-cell-based, error amplifier, and a local feedback loop, was presented by the authors in [
33]. The D2S in [
33] exhibits higher CMRR, improved ICMR, and better robustness with respect to PVT variations than the conventional inverter-based D2S.
In this paper, to further improve the CMRR and robustness to PVT variations, we propose an enhanced version (
) of the D2S in [
33], whose schematic is depicted in
Figure 4. In particular, the proposed
exploits the two-stage standard-cell-based error amplifier reported in
Figure 5 to boost the gain of the feedback loop with respect to the previous version. As further modifications, we have also added the inverters
and
to accurately set the output static voltage of the
and to provide a low-output impedance as discussed in
Section 2 and
Section 3. The factor
h in the inverters
in
Figure 4 denotes the number of reference inverters in parallel used to implement each one of the inverters
, whereas, referring to
Figure 5, the factor
g in the inverters
denotes the number of reference inverters in parallel used to implement each one of the inverters
.
The gain of the proposed improved error amplifier can be computed as:
and, considering the definition of
g, it can be rewritten as:
It has to be remarked that the proposed two-stage error amplifier does not require any internal compensation if its load capacitance (i.e., the sum of the input capacitances of
and
in
Figure 4) is high enough to guarantee a good phase-margin in the range of operation of the OTA.
The frequency response of the proposed
converter can be derived as follows:
and, remembering the definition of the factor
h, the dc differential gain can be simplified as:
By following the same aprroach reported in [
33], the CMRR of the proposed
can be derived as:
8. Comparison
The small-signal and large-signal Figures of Merit (
and
) are very popular metrics for comparing OTAs. However, these metrics do not take into account the area footprint of the amplifiers. Therefore the area-normalized
and
have been proposed in [
39] to allow for a more comprehensive comparison. These FOMs are defined as:
The proposed OTA has been compared against several ULV (i.e., operating with a supply voltage as low as 0.3 V) OTAs from the literature, and the results of this comparison are reported in
Table 5. The proposed amplifier results in the highest
and
outperforming all the other ULV OTAs. In addition, it exhibits the highest dc gain among the standard-cell-based OTAs. Large-signal performance is in line with the state of the art. Indeed, the
and
of the proposed OTA are higher than the ones in [
33,
51], whereas they are comparable with those shown by [
11,
12,
66]. Power consumption of the proposed OTA is relatively high, and this is mainly due to two main reasons: (1) the usage of non-minimum-sized standard cells to minimize the offset standard deviation under mismatch variations; (2) the adoption of a standard-cell library built with the low threshold voltage transistors of the technology (which allow us to achieve the best GBW). If higher offset and lower GBW are acceptable for the application, wherein the minimization of power consumption is the most important design goal, the following strategies can be combined: (1) reduce the size of the reference standard-cell; (2) choose the standard-cell library built with the high-threshold voltage transistors (recent CMOS technologies typically offer two or three threshold voltage options); (3) further reduce the supply voltage.