# FPGA Implementation of a Higher SFDR Upper DDFS Based on Non-Uniform Piecewise Linear Approximation

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## Abstract

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## 1. Introduction

- Proposing a non-uniform PWL approximation method with MAE controlled.
- Implementing a set of DDFS under different MAE based on the above method on FPGA to study the the impact of MAE on SFDR.
- Our proposed DDFS breaks through the SFDR theoretical upper bound of DDFS based on the piecewise linear approximation method represented in Equation (2).
- Implementing multi-core DDFS which can achieve 3.9 GHz sampling rate and 114 dB SFDR.

## 2. Non-Uniform PWL Approximation Method

#### 2.1. PWLMMAE

- Input range discretizationConsidering the hardware implementation, the input range should be discretized. For a given input interval $[X,Y]$, the input x should be defined as a vector$$x=x(1:\mathit{NUM})=X,X+\frac{1}{{2}^{Q}},X+\frac{2}{{2}^{Q}},\dots ,Y$$
- Minimization of MAE for a given width of subintervalThe slope a and intercept b of the subinterval approximation line are first calculated using the least squares method by Equations (6) and (7), and we can use $h\left(x\right)$ to represent the approximation line.$$\mathit{bn}+a\sum x=\sum f\left(x\right)$$$$b\sum x+a\sum {x}^{2}=\sum xf\left(x\right)$$$$\delta =f\left(x\right(j:k\left)\right)-h\left(x\right(j:K\left)\right)$$The corresponding MAE can also be calculated as$$\mathit{MAE}=\mathit{max}\left\{\right|\mathit{max}\left(\delta \right)|,|\mathit{min}\left(\delta \right)\left|\right\}$$To minimize MAE, we shift line $h\left(x\right)$ vertically such that $\left|\mathit{max}\right(\delta \left)\right|=\left|\mathit{min}\right(\delta \left)\right|$, and the distance T moved can be calculated by Equation (10). The MAE after movement is shown in Equation (11).$$T=\mathit{max}\left(\delta \right)-\frac{\mathit{max}\left(\delta \right)-\mathit{min}\left(\delta \right)}{2}=\frac{\mathit{max}\left(\delta \right)+\mathit{min}\left(\delta \right)}{2}$$$$\mathit{MAE}=\frac{\mathit{max}\left(\delta \right)-\mathit{min}\left(\delta \right)}{2}$$
- Segmentation pointsTo obtain the maximum segmentation interval, we determine the segmentation points from right to left. Initially, we set START = $x\left(1\right)$, END = $x\left(\mathit{NUM}\right)$, then perform the PWL method on x(START: END) to calculate MAE by Equations (8) and (9). If $\mathit{MAE}\le {E}_{c}$, where ${E}_{c}$ is a predefined error, approximation succeeds and set $b=b+T$; otherwise END = END − 1 and repeat above step. Once approximation succeeds, we will update START and END to find the next subinterval, where $\mathit{MAE}\le {E}_{c}$. The values of START and END record the segmentation points, the index i records the number of segments.Figure 2 shows the process of finding the ith segment. ${h}_{1},{h}_{2},\dots ,{h}_{i-1}$ represent the approximate lines of the previous $i-1$ segments respectively, $x\left({\mathit{END}}_{i-1}\right)$ is the start point of the ith segment. The end point of first approximation of ith segment is $x\left(\mathit{NUM}\right)$.Continuously move the end point to the left in steps $\frac{1}{{2}^{Q}}$ until the error between the approximate line and the objective curve is less than ${E}_{c}$. Then, we can obtain the end point $x\left({\mathit{END}}_{i}\right)$ of the ith segment and the approximate line ${h}_{i}\left(x\right)={a}_{i}x+{b}_{i}$.

Algorithm 1: PWLMMAE |

#### 2.2. PWL Approximation of the Sin Function

## 3. Hardware Architecture of DDFS

#### 3.1. Single-Core DDFS

#### 3.2. Multi-Core DDFS

## 4. Experimental Result

#### 4.1. Performance Evaluation of Single-Core DDFS

#### 4.2. Performance of Multi-Core DDFS

## 5. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

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**Figure 7.**Spectrum of DDFS output signal under different MAE, FCW = 200, clock frequency is 200 MHz. (

**a**) MAE = 0.01 (

**b**) MAE = 0.001 (

**c**) MAE = 0.0001 (

**d**) MAE = 0.00005 (

**e**) MAE = 0.00002 (

**f**) MAE = 0.00001.

i | a | b | End Point |
---|---|---|---|

1 | 1.54503497834031 | 0.000990880661757787 | 0.2001953125 |

2 | 1.43612208005773 | 0.0227876190983088 | 0.326171875 |

3 | 1.29779670692432 | 0.0679214996797700 | 0.43359375 |

4 | 1.14069314244100 | 0.136030419000189 | 0.5302734375 |

5 | 0.970322027885993 | 0.226383524844325 | 0.62109375 |

6 | 0.790355834163542 | 0.338143580690051 | 0.70703125 |

7 | 0.604027272905406 | 0.469880462191978 | 0.7900390625 |

8 | 0.412863639934916 | 0.620903909462291 | 0.87109375 |

9 | 0.218415511777311 | 0.790288325648528 | 0.951171875 |

10 | 0.0602097594473886 | 0.940157596611038 | 1 |

$\{{\mathit{sign}}_{\mathit{s}}:{\mathit{sign}}_{2}\}$ | Index |
---|---|

$s-1$’b111…111 | index1 |

$s-1$’b111…110 | index2 |

… | … |

$s-1$’b000…000 | indexs |

MAE | Segments | SFDR (dB) |
---|---|---|

0.01 | 4 | 44.94 |

0.001 | 10 | 69.64 |

0.0001 | 31 | 91.41 |

0.00005 | 44 | 96.58 |

0.00002 | 70 | 105.47 |

0.00001 | 100 | 114.04 |

DDFS Design | SFDR (dB) | Max Clock Frequency (MHz) | Target Device | Output Bits | Resource Utilization |
---|---|---|---|---|---|

Proposed | 114.04 | 244 | AXU15EG | 20 | 399LUTs, 66FFs, 3DSPs |

[6] | 110 | 250 | Artix-7 | 16 | 332LUTs, 216FFs |

[9] | 72.2 | 251 | Virtex-6 | 16 | 498LUTs, 206FFs |

[12] | 96.31 | 107.216 | XC3S500E | 16 | 967LUTs, 788FFs, 487 slices * |

[14] | 120 | 1000 | Virtex-7 | 16 | 46slices, 3DSPs |

[25] | 95 | 192 | Spartan-2 | 16 | 566slices |

[32] | 104.1 | 281.7 | Virtex-5 | 16 | 158slices |

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**MDPI and ACS Style**

Liao, X.; Zhang, L.; Hu, X.; Peng, Y.; Zhou, T.
FPGA Implementation of a Higher SFDR Upper DDFS Based on Non-Uniform Piecewise Linear Approximation. *Appl. Sci.* **2023**, *13*, 10819.
https://doi.org/10.3390/app131910819

**AMA Style**

Liao X, Zhang L, Hu X, Peng Y, Zhou T.
FPGA Implementation of a Higher SFDR Upper DDFS Based on Non-Uniform Piecewise Linear Approximation. *Applied Sciences*. 2023; 13(19):10819.
https://doi.org/10.3390/app131910819

**Chicago/Turabian Style**

Liao, Xuan, Longlong Zhang, Xiang Hu, Yuanxi Peng, and Tong Zhou.
2023. "FPGA Implementation of a Higher SFDR Upper DDFS Based on Non-Uniform Piecewise Linear Approximation" *Applied Sciences* 13, no. 19: 10819.
https://doi.org/10.3390/app131910819