# Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip

^{1}

^{2}

^{*}

## Abstract

**:**

## 1. Introduction

- A virtual coordinate system for numbering nodes in the circulant topology is proposed;
- The principle of greedy promotion in circulant topology is formulated;
- The rules for constructing the shortest routes between the two nodes based on a virtual coordinate system are formulated;
- A technique for calculating optimal network configurations is described;
- The comparison of communication stability in mesh and circulant topologies in the conditions of the failure of network nodes is made;
- NoCs with mesh and circulant topologies under load and failures are modeled and investigated.

## 2. Topological Approach

## 3. Circulant Versus Mesh and Torus

- There are many symmetry groups for 2D torus and circulant topologies. The circulant is completely invariant with respect to any of its nodes. A transformation that transfers one of the nodes to another completely preserves the original topology configuration. These properties allow us to significantly upgrade our earlier approach [7] based on the use of virtual coordinates for the 2D mesh topology.

- Only the node itself is located in the zero neighborhood;
- There are four nodes in the first neighborhood;
- There are eight nodes in the second neighborhood;
- There are 12 nodes in the third neighborhood;
- Etc.

## 4. Virtual Coordinate System

Algorithm 1 Address Assignment Algorithm | |

1 | define center node |

2 | i = 1 |

3 | while (at least one node in $i$-neighborhood exist) |

4 | build i-neighborhood relative to the central node |

5 | assign coordinates to nodes from the $i$-neighborhood |

6 | i = i + 1 |

7 | end while |

8 | stop partitioning process |

## 5. Routing Methods in a Network with a Circulant Topology with a Virtual Coordinate System

## 6. Evaluation and Discussion

## 7. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Acknowledgments

## Conflicts of Interest

## References

- Ansari, A.Q.; Ansari, M.R.; Khan, M.A. Performance Evaluation of Various Parameters of Network-on-Chip (NoC) for Different Topologies. In Proceedings of the 12th IEEE International Conference Electronics, Energy, Environment, Communication, Computer, Control: (E3-C3), INDICON 2015, New Delhi, India, 17–20 December 2015. [Google Scholar] [CrossRef]
- Stensgaard, M.B.; Sparsø, J. ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology. In Proceedings of the Second IEEE International Symposium Networks-on-Chip, NOCS 2008, Newcastle, UK, 7–11 April 2008; pp. 55–64. [Google Scholar] [CrossRef]
- Bhanu, P.V.; Govindan, R.; Kumar, R.; Singh, V.; Soumya, J.; Cenkeramaddi, L.R. Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA. IEEE Access
**2021**, 9, 76759–76779. [Google Scholar] [CrossRef] - Dhanapala, D.C.; Jayasumana, A.P. Topology Preserving Maps-Extracting Layout Maps of Wireless Sensor Networks from Virtual Coordinates. IEEE/ACM Trans. Netw.
**2014**, 22, 784–797. [Google Scholar] [CrossRef] - Huang, P.; Wang, C.; Xiao, L. Improving End-to-End Routing Performance of Greedy Forwarding in Sensor Networks. IEEE Trans. Parallel Distrib. Syst.
**2012**, 23, 556–563. [Google Scholar] [CrossRef] - Dhanapala, D.C.; Jayasumana, A.P. Anchor Selection and Topology Preserving Maps in WSNs—A Directional Virtual Coordinate Based Approach. In Proceedings of the 43rd Annual IEEE Conference on Local Computer Networks, LCN, Maui, HI, USA, 31 July–4 August 2011; pp. 571–579. [Google Scholar] [CrossRef]
- Romanov, A.; Myachin, N.; Sukhov, A. Fault-Tolerant Routing in Networks-on-Chip Using Self-Organizing Routing Algorithms. In Proceedings of the IECON 2021—47th Annual Conference of the IEEE Industrial Electronics Society, Toronto, ON, Canada, 13–16 October 2021; pp. 1–6. [Google Scholar] [CrossRef]
- Venkateswara Rao, M.; Krishna, T.V.R.; Yasaswini, G. A Frame Work on AMBA Bus Based Communication Architecture to Improve the Real Time Computing Performance in MPSoC. IJCA
**2014**, 91, 1–5. [Google Scholar] [CrossRef] - Jayshree, S.G.; Pati, D.; Jayshree, S.G.; Pati, D. Design and Area Performance Energy Consumption Comparison of Secured Network-on-Chip with PTP and Bus Interconnections. JIEIB
**2022**, 103, 1479–1491. [Google Scholar] [CrossRef] - Sparsø, J.; Kasapaki, E.; Schoeberl, M. An Area-Efficient Network Interface for a TDM-Based Network-on-Chip. In Proceedings of the DATE’24: Design, Automation and Test in Europe, Grenoble, France, 18–22 March 2013; pp. 1044–1047. [Google Scholar] [CrossRef]
- Abbaszadeh, M.; Mazraeli, M.; Rahmati, D.; Attarzadeh-Niaki, S.H. ANDRESTA: An Automated NoC-Based Design Flow for Real-Time Streaming Applications. In Proceedings of the RTEST 2020—3rd CSI/CPSSI International Symposium on Real-Time and Embedded Systems and Technologies (RTEST), Tehran, Iran, 10–11 June 2020. [Google Scholar] [CrossRef]
- Bjerregaard, T.; Mahadevan, S. A Survey of Research and Practices of Network-on-Chip. ACM Comput. Surv.
**2006**, 38, 71–121. [Google Scholar] [CrossRef] - Das, M.S. Architecture of Multi-Processor Systems Using Networks on Chip (NoC): An Overview. CVR J. Sci. Technol.
**2022**, 22, 7–15. [Google Scholar] [CrossRef] - Howser, G. The OSI Seven Layer Model. In Computer Networks and the Internet; Springer: Cham, Switzerland, 2020; pp. 7–32. [Google Scholar] [CrossRef]
- Horro, M.; Kandemir, M.T.; Pouchet, L.N.; Rodríguez, G.; Touriño, J. Effect of Distributed Directories in Mesh Interconnects. In Proceedings of the 56th Annual Design Automation Conference, Las Vegas, NV, USA, 2–6 June 2019. [Google Scholar] [CrossRef]
- Marcelli, A.; Graziano, M.; Ugarte-Pedrero, X.; Fratantonio, Y.; Mansouri, M.; Balzarotti, D.; Balzarotti Eurecom, D. Don’t Mesh Around: {Side-Channel} Attacks and Mitigations on Mesh Interconnects; USENIX Association: Boston, MA, USA, 2022; ISBN 978-1-939133-31-1. [Google Scholar]
- Ditzel, D.; Espasa, R.; Aymerich, N.; Baum, A.; Berg, T.; Burr, J.; Hao, E.; Iyer, J.; Izquierdo, M.; Jayaratnam, S.; et al. Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip. In Proceedings of the 2021 IEEE Hot Chips 33 Symposium (HCS), Palo Alto, CA, USA, 22–24 August 2021. [Google Scholar] [CrossRef]
- Paccagnella, R.; Luo, L.; Fletcher, C.W. Lord of the Ring(s): Side Channel Attacks on the {CPU} {On-Chip} Ring Interconnect Are Practical; USENIX Association: Boston, MA, USA, 2021; ISBN 978-1-939133-24-3. [Google Scholar]
- Papazian, I.E. New 3rd Gen Intel
^{®}Xeon^{®}Scalable Processor (Codename: Ice Lake-SP). In Proceedings of the 2020 IEEE Hot Chips 32 Symposium (HCS), Palo Alto, CA, USA, 6–18 August 2020. [Google Scholar] [CrossRef] - Chethan Kumar, H.B.; Ravi, P.; Modi, G.; Kapre, N. 120-Core MicroAptiv MIPS Overlay for the Terasic DE5-NET FPGA Board. In Proceedings of the FPGA 2017—2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, 22–24 February 2017; pp. 141–146. [Google Scholar] [CrossRef]
- Bononi, L.; Concer, N. Simulation and Analysis of Network on Chip Architectures: Ring, Spidergon and 2D Mesh. In Proceedings of the Design Automation & Test in Europe Conference, Munich, Germany, 6–10 March 2006; p. 6. [Google Scholar] [CrossRef]
- Romanov, A.Y. Development of Routing Algorithms in Networks-on-Chip Based on Ring Circulant Topologies. Heliyon
**2019**, 5, e01516. [Google Scholar] [CrossRef] - Alimi, I.A.; Patel, R.K.; Aboderin, O.; Abdalla, A.M.; Gbadamosi, R.A.; Muga, N.J.; Pinto, A.N.; Teixeira, A.L.; Alimi, I.A.; Patel, R.K.; et al. Network-on-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction. In Network-on-Chip—Architecture, Optimization, and Design Explorations; IntechOpen: London, UK, 2021. [Google Scholar] [CrossRef]
- Bhowmik, B. Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networks. IEEE Trans. Very Large Scale Integr. Syst.
**2021**, 29, 1009–1021. [Google Scholar] [CrossRef] - Pai, K.J.; Yang, J.S.; Chen, G.Y.; Chang, J.M. Configuring Protection Routing via Completely Independent Spanning Trees in Dense Gaussian On-Chip Networks. IEEE Trans. Netw. Sci. Eng.
**2022**, 9, 932–946. [Google Scholar] [CrossRef] - Bhanu, P.V.; Kulkarni, P.V.; Soumya, J. Butterfly-Fat-Tree Topology Based Fault-Tolerant Network-on-Chip Design Using Particle Swarm Optimisation. J. Exp. Theor. Artif. Intell.
**2019**, 31, 781–799. [Google Scholar] [CrossRef] - Zhang, H.; Wang, X. KGT: An Application Mapping Algorithm Based on Kernighan–Lin Partition and Genetic Algorithm for WK-Recursive NoC Architecture. In Intelligent Computing Theories and Application. ICIC 2021. Lecture Notes in Computer Science; Springer: Cham, Switzerland, 2021; Volume 12836 LNCS, pp. 86–101. [Google Scholar] [CrossRef]
- Rzaev, E.; Ryzhov, A.; Romanov, A. The New Promising Network-on-Chip Topologies Development Using Hierarchical Method. In Proceedings of the 2022 International Conference on Industrial Engineering, Applications and Manufacturing (ICIEAM), Sochi, Russia, 16–20 May 2022; pp. 819–824. [Google Scholar] [CrossRef]
- Ali, M.N.M.; Rahman, M.M.H.; Nor, R.M.; Behera, D.K.; Sembok, T.M.T.; Miura, Y.; Inoguchi, Y. SCCN: A Time-Effective Hierarchical Interconnection Network for Network-On-Chip. Mob. Netw. Appl.
**2019**, 24, 1255–1264. [Google Scholar] [CrossRef] - Liu, H.; Li, X.; Wang, S.; Liu, H.; Li, X.; Wang, S. Construction of Dual Optimal Bidirectional Double-Loop Networks for Optimal Routing. Mathematics
**2022**, 10, 4016. [Google Scholar] [CrossRef] - Huang, X.; Ramos, A.F.; Deng, Y. Optimal Circulant Graphs as Low-Latency Network Topologies. J. Supercomput.
**2022**, 78, 13491–13510. [Google Scholar] [CrossRef] - Xiao, W.; Dey, A.; Son, L.H. A Study on Regular Picture Fuzzy Graph with Applications in Communication Networks. J. Intell. Fuzzy Syst.
**2020**, 39, 3633–3645. [Google Scholar] [CrossRef] - Mohanta, K.; Dey, A.; Pal, A.; Long, H.V.; Son, L.H. A Study of M-Polar Neutrosophic Graph with Applications. J. Intell. Fuzzy Syst.
**2020**, 38, 4809–4828. [Google Scholar] [CrossRef] - Meng, Y.; Liu, X.; Dai, L.; Huang, H. Graph Similarity-Based Maximum Stable Subgraph Extraction of Information Topology from a Vehicular Network. IEEE Trans. Intell. Transp. Syst.
**2022**, 23, 355–367. [Google Scholar] [CrossRef] - Zhang, Y.; Wang, H.; Jia, M.; Wang, J.; Li, D.; Xue, G.; Tan, K.L. TopoX: Topology Refactorization for Minimizing Network Communication in Graph Computations. IEEE/ACM Trans. Netw.
**2020**, 28, 2768–2782. [Google Scholar] [CrossRef] - Jayasumana, A.P.; Paffenroth, R.; Mahindre, G.; Ramasamy, S.; Gajamannage, K. Network Topology Mapping from Partial Virtual Coordinates and Graph Geodesics. IEEE/ACM Trans. Netw.
**2019**, 27, 2405–2417. [Google Scholar] [CrossRef] - Chemodanov, D.; Esposito, F.; Calyam, P.; Sukhov, A. REBATE: A REpulsive-BAsed Traffic Engineering Protocol for Dynamic Scale-Free Networks. Futur. Gener. Comput. Syst.
**2020**, 108, 624–635. [Google Scholar] [CrossRef] - Kunthara, R.G.; James, R.K.; Sleeba, S.Z.; Jose, J. Traffic Aware Routing in 3D NoC Using Interleaved Asymmetric Edge Routers. Nano Commun. Netw.
**2021**, 27, 100334. [Google Scholar] [CrossRef] - Halavar, B.; Pasupulety, U.; Talawar, B. Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal Evaluation of 3D NoC Architectures. Simul. Model. Pract. Theory
**2019**, 96, 101929. [Google Scholar] [CrossRef] - Beivide, R.; Arruabarrena, A.; Herrada, E.; Balcazar, J.L. Optimal Distance Networks of Low Degree for Parallel Computers. IEEE Trans. Comput.
**1991**, 40, 1109–1124. [Google Scholar] [CrossRef] - Moscibroda, T.; Wattenhofer, M.; O’Dell, R.; Wattenhofer, R. Virtual Coordinates for Ad Hoc and Sensor Networks. In Proceedings of the 2004 Joint Workshop on Foundations of Mobile Computing, DIALM-POMC’04, Philadelphia, PA, USA, 1 October 2004; pp. 8–16. [Google Scholar] [CrossRef]
- Lim, H.; Lim, C.; Hou, J.C. A Coordinate-Based Approach for Exploiting Temporal-Spatial Diversity in Wireless Mesh Networks. In Proceedings of the Annual International Conference on Mobile Computing and Networking, MOBICOM 2006, Los Angeles, CA, USA, 23–29 September 2006; pp. 14–25. [Google Scholar] [CrossRef]
- Romanov, A.Y.; Starykh, V.A. Routing in Triple Loop Circulants: A Case of Networks-on-Chip. Heliyon
**2020**, 6, e04427. [Google Scholar] [CrossRef] - Monakhova, E.A.; Monakhov, O.G.; Romanov, A.Y. Routing Algorithms in Optimal Degree Four Circulant Networks Based on Relative Addressing: Comparative Analysis for Networks-on-Chip. IEEE Trans. Netw. Sci. Eng.
**2022**, 10, 413–425. [Google Scholar] [CrossRef] - Montanana, J.M.; De Andres, D.; Tirado, F. Fault Tolerance on NoCs. In Proceedings of the 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013, Barcelona, Spain, 25–28 March 2013; pp. 138–143. [Google Scholar] [CrossRef]
- Dijkstra, E.W. A Note on Two Problems in Connexion with Graphs. In Edsger Wybe Dijkstra: His Life, Work, and Legacy; Association for Computing Machinery: New York, NY, USA, 2022; pp. 287–290. [Google Scholar] [CrossRef]
- Romanov, A.Y.; Myachin, N.M.; Lezhnev, E.V.; Ivannikov, A.D.; El-Mesady, A. Ring-Split: Deadlock-Free Routing Algorithm for Circulant Networks-on-Chip. Micromachines
**2023**, 14, 141. [Google Scholar] [CrossRef] - Catania, V.; Mineo, A.; Monteleone, S.; Palesi, M.; Patti, D. Noxim: An Open, Extensible and Cycle-Accurate Network on Chip Simulator. In Proceedings of the International Conference on Application-Specific Systems, Architecture, and Processors, Toronto, ON, Canada, 27–29 July 2015; pp. 162–163. [Google Scholar] [CrossRef]
- Gaffour, K.; Benhaoua, M.K.; Benyamina, A.H.; Zahaf, H.E. A New Congestion-Aware Routing Algorithm in Network-on-Chip: 2D and 3D Comparison. Int. J. Comput. Appl.
**2019**, 45, 27–35. [Google Scholar] [CrossRef]

**Figure 11.**Modeling connection breaks in $C(256;\text{}1,\text{}92)$ with routing based on the proposed Greedy Promotion Algorithm.

**Figure 13.**Simulation of broken connections in mesh16x16 with routing based on the Greedy Promotion Algorithm.

**Figure 14.**Comparison of the results of the simulation of broken connections in the topologies $C(256;\text{}1,\text{}92)$ and mesh16x16 for different routing algorithms.

Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content. |

© 2024 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Sukhov, A.M.; Romanov, A.Y.; Selin, M.P.
Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip. *Symmetry* **2024**, *16*, 127.
https://doi.org/10.3390/sym16010127

**AMA Style**

Sukhov AM, Romanov AY, Selin MP.
Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip. *Symmetry*. 2024; 16(1):127.
https://doi.org/10.3390/sym16010127

**Chicago/Turabian Style**

Sukhov, Andrei M., Aleksandr Y. Romanov, and Maksim P. Selin.
2024. "Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip" *Symmetry* 16, no. 1: 127.
https://doi.org/10.3390/sym16010127