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Article

MOSs-String-Triggered Silicon-Controlled Rectifier (MTSCR) ESD Protection Device for 1.8 V Application

by
Ruibo Chen
1,
Hao Wei
1,
Hongxia Liu
1,*,
Fei Hou
2,
Qi Xiang
1,
Feibo Du
2,
Cong Yan
1,
Tianzhi Gao
1 and
Zhiwei Liu
2,*
1
Key Laboratory for Wide-Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian University, Xi’an 710071, China
2
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610056, China
*
Authors to whom correspondence should be addressed.
Micromachines 2023, 14(3), 632; https://doi.org/10.3390/mi14030632
Submission received: 17 January 2023 / Revised: 5 March 2023 / Accepted: 7 March 2023 / Published: 10 March 2023
(This article belongs to the Section D1: Semiconductor Devices)
Browse Figures
Versions Notes

Abstract

:
In this work, a new low voltage-triggered silicon-controlled rectifier named MTSCR is realized in a 65 nm CMOS process for low voltage-integrated circuits electrostatic discharge (ESD) protections. The MTSCR incorporates an external NMOSs-string, which drives the internal NMOS (INMOS) of MTSCR to turn on, and then the INMOS drive SCR structure to turn on. Compared with the existing low trigger voltage (Vt1) ESD component named diodes-string-triggered SCR (DTSCR), the MTSCR can realize the same low Vt1 characteristic but less area penalty of ~44.3% reduction. The results of the transmission line pulsing (TLP) measurement shows that the MTSCR possesses above 2.42 V holding voltage (Vh) and a low Vt1 of ~5.03 V, making it very suitable for the ESD protections for 1.8 V input/output (I/O) ports in CMOS technologies.

1. Introduction

With the scaling down of CMOS processes, the challenges of the electrostatic discharge (ESD) protection for integrated circuits (IC) become more severe [1]. The gate-grounded NMOS (GGNMOS), which was previously one of the most widely used ESD protection devices in CMOS processes, is invalid in advanced CMOS technologies due to its inadequate robustness [2,3,4]. Therefore, the researchers began to turn their attentions to the lateral silicon-controlled rectifier (LSCR) thanks to its higher level of robustness. However, the conventional LSCR shows a deep snap-back in its I-V characteristic, which violates the ESD design window of most IC processes. Improved designs have been constantly proposed to enable SCR structure to be applied in practical projects [5,6], such as the modified lateral SCR (MLSCR) [7,8] and the diodes-string-triggered SCR (DTSCR) [9,10,11,12,13,14]. As such, the DTSCR is particularly well-suited for lower voltage domain with benefit from its lower and adjustable trigger voltage [9]. Moreover, the improved structures based on DTSCR have been continually proposed. For example, in [15], a novel device called thermal-stable DTSCR (TSDTSCR) is proposed to offer an improved ESD protection stability at elevated temperatures, which is realized by optimizing the 3D layout of the DTSCR. In another work, researchers embedded current gain amplifier modules into DTSCR and achieved faster turn-on speed and superior I-V properties [16].
Nevertheless, the DTSCR structures are used to protect the circuits that operate below 1.8 V. For 2.5 V or above circuits ESD protections, the DTSCR structures will incorporate more than four triggering diodes for voltage clamp, and will have enlarged leakage current due to the enhanced Darlington effects. In addition, the area consumption will also increase with more numbers of the triggering diode. In recent years, a SCR structure called directly connected SCR (DCSCR) has been reported [17], which is independent of external diodes-string to trigger. However, the DCSCR is aimed at the ESD protection of core circuit and the rail-based ESD protection scheme. For the local-based ESD protection scheme of input/output (I/O) circuit, DCSCR has the issues of mis-trig risk and high leakage. At this point, low voltage-triggered SCR (LVTSCR) has exhibited sufficient area-efficiency for low voltage ESD protections in deep sub-micron technologies, but it will be invalid in advanced processes due to its intolerable I-V characteristics [18,19,20,21]. Many new structures based on LVTSCR have been proposed with higher holding voltage [22,23], and there are also studies focusing on improving the on-resistance of LVTSCR structure [24]. However, the high trigger voltage of LVTSCR structure is still a critical issue for its application in advanced processes.
This paper proposed a MOS-string-triggered SCR (MTSCR) as a more appropriate ESD protection solution for the 1.8 V circuits, with less area consumption and immunity on the Darlington effect compared to the DTSCR structures.

2. Methods

Figure 1a shows the cross-sectional view of MTSCR, and its equivalent circuit is presented in Figure 1b. The MTSCR incorporates an internal NMOS (INMOS) within the PWELL, with its drain spanning the boundary between NWELL and PWELL. In addition, an external NMOS (ENMOS) string is paralleled to the SCR structure. The gate and drain of ENMOS are tied together. Moreover, the gate of the INMOS is connected to the drain of one ENMOS in ENMOSs-string. When an ESD event arrives, it will force the ENMOSs-string path to conduct, then the INMOS will turn on as the voltage on its gate exceeds the threshold voltage. Meanwhile, the emitter-base junctions of Q1 and Q2 can be charged, and eventually, the SCR path is triggered. It should be noted that the INMOS acts as a similar current-trigger assistance effect as the diodes-string of the DTSCR, whereas the ENMOSs-string merely dominates the turn on of the INMOS rather than the parasitic bipolar transistors Q1 and Q2 of the inherent SCR. Therefore, the ENMOSs-string can be designed with a much smaller equivalent width to realize a larger resistance, which will prompt more current to the INMOS current-trigger path.

3. Results and Discussion

In this paper, the proposed MTSCR with different numbers and different widths of ENMOS (WN) transistors are realized and evaluated in a 65 nm CMOS logic technology. All ENMOS transistors of the ENMOSs-string and INMOS introduce the 1.1 V standard specification with the channel length L of 0.28 µm, and their Vth are ~0.345 V. With the consideration of 1.8 V circuits ESD protection applications, the MTSCR with six ENMOS transistors and the conventional DTSCR with three trigger-diodes are compared. Their layouts are as shown in Figure 2a,b, where the inherent SCRs of the two types devices have the same area of ~770 μm2 and the same width (WSCR) of 55 μm. In order to realize acceptable trigger characteristics of the DTSCR, the diodes-string is always kept the same to the equivalent width of the inherent SCR. While the ENMOSs-string of the MTSCR is designed with a much smaller width of 5 μm, it will not worsen the trigger characteristics. Eventually, the total area consumption of MTSCR is 1040 μm2, which is ~50% lower than the 2000 μm2 area consumption of DTSCR. The innovativeness of MTSCR is that it incorporates an ENMOSs-string on the basis of the LVTSCR, thus eliminating the Darlington effect that was brought by the diodes-string in the DTSCR and also reducing area consumption. The quasi-static I-V characteristics of the proposed devices are measured using Hanwa TED-T5000 transmission line pulsing (TLP) tester with 10 ns rise time and 100 ns pulse width, and their CDM ESD characteristic were evaluated by ESDEMC MODEL ES620 Very Fast TLP (VF-TLP) tester with 200 ps rise time and 5 ns pulse width.
Four different MTSCRs with varying numbers (N = 3, 4, 5, 6) of ENMOSs are labeled as MTSCR1, MTSCR2, MTSCR3, and MTSCR4. The TLP I-V characteristics of these devices are shown in Figure 3a, and the extracted parameters are compared in Table 1. It can be observed from Figure 3a that all devices exhibit two stages during their trigger processes. For MTSCR1, the first stage commences at about 1.92 V (Von), which is caused by the INMOS being turned on by ENMOSs-string. Then, the second stage occurs at about 5.65 V, where the SCR path is triggered. It can also be observed that as N increases from 3 to 6, the Von is increased from 2.8 V to 4.05 V, while the Vtl is decreased from 5.65 V to 5.47 V. Indeed, the ENMOSs-string only dominates the conduction of INMOS’s channel by controlling the gate voltage of the INMOS. Since the INMOS turned on, the current will be discharge by the ENMOS path and INMOS path, while the trigger voltage of the MTSCR is actually determined by the turn-on of the SCR path, which is dominated by its parasitic transistors Q1 and Q2. As the number of the ENMOS (N) increased, more current will be prompted from the ENMOS path to the INMOS path. As discussed in the Section 2 Methods, the real current trigger path of MTSCR is the INMOS path, thus the increased N will urge more current flow to the INMOS path, and consequently both the total trigger current and trigger voltage of MTSCR are lowered. It should be noted that the Vh, and It2 of MTSCRs remain consistent. Hence, it is anticipated that MTSCR can suit various ESD design windows by modifying the number of ENMOSs accordingly.
Figure 3b presents the VF-TLP test results of the four MTSCRs. Parameters are extracted into Table 1. From Table 1, an interesting phenomenon can be observed: the Vtl of TLP and VFTLP show the opposite trend. This is because the rise time and duration of VF-TLP pulse are far shorter than that of TLP [25]; therefore, when the time reaches the 70% of one VF-TLP pulse, the device has not reached steady state and the voltage is still on the process of lowering, that is to say, the turn-on time can affect the Vtl of the device under VF-TLP test. If the number of ENMOS is increased, lower voltage will be coupled to the gate of the INMOS, and consequently the INMOS path will be turned on later, showing an increased trigger voltage under VF-TLP test.
Figure 4 shows the leakage of MTSCRs at 25 °C, which indicates that the leakage decreases with the increase in the number of ENMOS. For 1.8 V applications in 65 nm CMOS process, the MTSCR4 with the leakage of ~10 nA can satisfy the ESD design window, which is between 1.98 V and 8.1 V. However, it is worth noting that the leakages of the MTSCRs are dominant by the total Vth of the ENMOSs-string, and consequently incorporating higher Vth ENMOS transistors instead of 1.1 V standard specification might optimize the leakage characteristic without increasing the ENMOS’s number.
Static latch-up evaluation has been checked with DC I-V characteristic of the proposed devices at 150 °C, which is shown in Figure 5. The current was restricted to below 0.1 A to protect the tested devices. The results shows that the Vh of all devices exceed 1.98 V. Therefore, the proposed MTSCR can provide steady ESD protection for 1.8 V of supply voltage circuits without latch-up risk.
The MTSCR devices with different width of ENMOSs WN are evaluated by TLP measurement as shown in Figure 6. It is clearly observed that the It2 of the devices has no reduction with the WN decreased. This is because the ENMOSs-string of the MTSCR dominates the gate voltage bias of the INMOS. Since the INMOS turned on, the inherent SCR of the MTSCR will be triggered by the INMOS current assistance, and then most of the ESD current will shunt to the inherent SCR path.
In modern technology, the epitaxy is getting thinner and thinner, and the sheet resistance of WELL is also increasing with it. Thus, the impact of D1 (shown in Figure 1a) on well resistance will be significant. Figure 7 presents the TLP test results of MTSCRs with various D1. As D1 was increased from 0.5 μm to 4.0 μm, the Vt1 decreased from 6.92 V to 5.03 V. The trigger current also decreased from 892 mA to 467 mA, while the It2 increased from 2.72 A to 2.97 A. This phenomenon is related to the current distribution among the current within the MTSCR. The increased D1 means larger equivalent resistance of INMOS path and N+/NWELL/PWELL/P+ diode path, resulting in more current flow to the SCR path, which leads to the decreasing Vtl and trigger current, and increasing It2.
For 2.5 V circuits ESD protections, the holding voltage of the MTSCR can be further improved by adjusting the dimension of D2 as shown in Figure 1a. As it is shown in Figure 8, when increasing D2, the well resistance in SCR path will be enlarged, and consequently both the Vh and Vt1 will be increased.
Table 2 summarizes the ESD characteristics of the proposed MTSCR and the structures in [24,26,27]. The DCSCR possesses a very high It2, but the low trigger voltage determines that it cannot satisfy the ESD design window of 1.8 V circuit. As for the improved LVTSCR, although it has high holding voltage, its trigger voltage is exorbitant. Both the DTSCR and the MTSCR can be adjusted to fit the 1.8/2.5 V circuits, but MTSCR consumes less area and possesses much higher It2 than the DTSCR. Thus, the MTSCR has advantages for the ESD protection of 1.8/2.5 V circuit.

4. Conclusions

In this paper, a novel and improved low-triggered ESD protection structure called MTSCR has been designed and fabricated in a 65 nm CMOS process. When compared with the DTSCR, the MTSCR is able to achieve a low trigger voltage as well as ~44.3% reduction in area consumption. The MTSCR also possesses tunable trigger voltage and low leakage that is nA-level, which makes it more advantageous in the ESD protection of 1.8 V voltage domain. Moreover, the MTSCR can suit the ESD design window of 2.5 V voltage domain by adjusting D1 and the number of ENMOS transistors.

Author Contributions

Formal analysis, R.C. and H.W.; resources, Z.L.; data curation, R.C.; writing—original draft preparation, H.W.; writing—review and editing, R.C.; visualization, F.H.; investigation, F.D.; funding acquisition, H.L.; validation, C.Y., Q.X. and T.G. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by National Natural Science Foundation of China, grant number U2241221.

Data Availability Statement

Not applicable.

Acknowledgments

The authors would like to thank J.J. Liou and Zhi-Hua Zhu from Zhengzhou University for their valuable technical support.

Conflicts of Interest

The authors declare no conflict of interest.

References

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Figure 1. The proposed MTSCR device: (a) cross-sectional view and (b) equivalent circuit.
Figure 1. The proposed MTSCR device: (a) cross-sectional view and (b) equivalent circuit.
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Figure 2. Layouts of (a) the conventional DTSCR and (b) the proposed MTSCR device.
Figure 2. Layouts of (a) the conventional DTSCR and (b) the proposed MTSCR device.
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Figure 3. (a) TLP and (b) VF-TLP test results of MTSCRs with N = 3, 4, 5, and 6. The rise time of the TLP and VFTLP pulse are 10 ns and 200 ps, respectively.
Figure 3. (a) TLP and (b) VF-TLP test results of MTSCRs with N = 3, 4, 5, and 6. The rise time of the TLP and VFTLP pulse are 10 ns and 200 ps, respectively.
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Figure 4. DC sweep of MTSCR1, MTSCR2, MTSCR3, and MTSCR4 at 25 °C.
Figure 4. DC sweep of MTSCR1, MTSCR2, MTSCR3, and MTSCR4 at 25 °C.
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Figure 5. DC sweep of MTSCR1, MTSCR2, MTSCR3, and MTSCR4 at 150 °C.
Figure 5. DC sweep of MTSCR1, MTSCR2, MTSCR3, and MTSCR4 at 150 °C.
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Figure 6. TLP test results of MTSCRs with different widths of the ENMOS transistors (WN).
Figure 6. TLP test results of MTSCRs with different widths of the ENMOS transistors (WN).
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Figure 7. TLP test results of MTSCRs with four different D1.
Figure 7. TLP test results of MTSCRs with four different D1.
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Figure 8. TLP test results of MTSCRs with four different D2.
Figure 8. TLP test results of MTSCRs with four different D2.
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Table
Table 1. TLP and VF-TLP test results of MTSCRs.
Table 1. TLP and VF-TLP test results of MTSCRs.
Device NameNumber of NMOS (N)TLP Measurement ResultsVF-TLP Measurement Results
Von (V)Vt1 (V)Vh (V)It2 (A)Von (V)Vt1 (V)Vh (V)It2 (A)
MTSCR131.925.652.422.723.146.032.857.86
MTSCR242.805.512.502.714.256.372.608.09
MTSCR353.445.422.212.714.996.623.238.18
MTSCR464.055.472.352.735.396.753.687.43
Table
Table 2. Comparison among the DTSCR, DCSCR, improved LVTSCR, and the proposed MTSCR.
Table 2. Comparison among the DTSCR, DCSCR, improved LVTSCR, and the proposed MTSCR.
SCR CategoryTechnology ProcessTrigger
Voltage (V)		Area (μm2) FOM (mA/um2)Applicable Voltage
Domain
DTSCR with 3 diodes [26]0.18 μm CMOS2.625271.581.8 V
DCSCR [27]0.18 μm
CMOS		1.615513.670.8–1.2 V
Improved LVTSCR [24]0.18 μm BCD9.1429522.465 V
This work65 nm CMOS5.4710402.621.8–2.5 V
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MDPI and ACS Style

Chen, R.; Wei, H.; Liu, H.; Hou, F.; Xiang, Q.; Du, F.; Yan, C.; Gao, T.; Liu, Z. MOSs-String-Triggered Silicon-Controlled Rectifier (MTSCR) ESD Protection Device for 1.8 V Application. Micromachines 2023, 14, 632. https://doi.org/10.3390/mi14030632

AMA Style

Chen R, Wei H, Liu H, Hou F, Xiang Q, Du F, Yan C, Gao T, Liu Z. MOSs-String-Triggered Silicon-Controlled Rectifier (MTSCR) ESD Protection Device for 1.8 V Application. Micromachines. 2023; 14(3):632. https://doi.org/10.3390/mi14030632

Chicago/Turabian Style

Chen, Ruibo, Hao Wei, Hongxia Liu, Fei Hou, Qi Xiang, Feibo Du, Cong Yan, Tianzhi Gao, and Zhiwei Liu. 2023. "MOSs-String-Triggered Silicon-Controlled Rectifier (MTSCR) ESD Protection Device for 1.8 V Application" Micromachines 14, no. 3: 632. https://doi.org/10.3390/mi14030632

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