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Article

Role of CdTe Interface Structure on CdS/CdTe Photovoltaic Device Performance

by
Niva K. Jayswal
,
Dipendra Adhikari
,
Indra Subedi
,
Ambalanath Shan
and
Nikolas J. Podraza
*
Department of Physics and Astronomy, Wright Center for Photovoltaics Innovation and Commercialization, The University of Toledo, Toledo, OH 43606, USA
*
Author to whom correspondence should be addressed.
Materials 2023, 16(20), 6812; https://doi.org/10.3390/ma16206812
Submission received: 21 September 2023 / Revised: 15 October 2023 / Accepted: 17 October 2023 / Published: 23 October 2023
(This article belongs to the Section Thin Films and Interfaces)
Browse Figures
Versions Notes

Abstract

:
Glancing angle deposition (GLAD) of CdTe can produce a cubic, hexagonal, or mixed phase crystal structure depending upon the oblique deposition angles (Φ) and substrate temperature. GLAD CdTe films are prepared at different Φ at room temperature (RT) and a high temperature (HT) of 250 °C and used as interlayers between the n-type hexagonal CdS window layer and the p-type cubic CdTe absorber layer to investigate the role of interfacial tailoring at the CdS/CdTe heterojunction in photovoltaic (PV) device performance. The Φ = 80° RT GLAD CdTe interlayer and CdS both have the hexagonal structure, which reduces lattice mismatch at the CdS/CdTe interface and improves electronic quality at the heterojunction for device performance optimization. The device performance of HT CdS/CdTe solar cells with Φ = 80° RT with 50 to 350 nm thick GLAD CdTe interlayers is evaluated in which a 250 nm interlayer device shows the best device performance with a 0.53 V increase in open-circuit voltage and fill-factor product and a 0.73% increase in absolute efficiency compared to the HT baseline PV device without an interlayer.

1. Introduction

Cadmium telluride (CdTe) is a photovoltaic (PV) absorber layer material with an absorption coefficient > 105 cm−1 in the visible spectral range and a bandgap of ~1.5 eV which is well suited for single-junction PV devices [1,2,3,4,5,6,7]. CdTe-based PV devices have achieved 22.1% efficiency and have captured ~5% of the current world PV market [8]. CdTe can be deposited using different deposition methods such as close-space sublimation [9,10], electrochemical deposition [11], close-space vapor transport deposition [12,13], and sputtering [2,3,4,5,6]. Sputtered CdTe solar cells are widely studied in laboratory research as they can be fabricated at comparatively low temperatures (<250 °C), whereas close-space sublimation and vapor transport deposition require high processing temperatures (>500 °C) for the best CdTe cells, while electrochemical deposition requires acidic or basic media. Previously, all sputtered CdS/CdTe heterojunction solar cells with up to 14% efficiency have been reported [6]. The efficiency of CdTe solar cell devices can be increased by improving the conductivity of the front contact with novel transparent conducting oxides with higher conductivity and low resistance. Other potential measures include barrier-free back contacts and fewer defects at the CdS/CdTe interface by reducing the high lattice mismatch between the n-type hexagonal CdS window layer and the p-type cubic CdTe absorber layer [14,15]. The lattice mismatch between hexagonal wurtzite-structured CdS and cubic zinc blende CdTe can be reduced by optimizing the interdiffusion of CdS and CdTe at the CdS/CdTe interface or controlling the microstructure of CdTe at the interface to improve the electronic quality [16,17,18]. The optimized interdiffusion of CdS and CdTe at the interface reduces the lattice mismatch due to the decreased interatomic distance by the substitution of lower atomic radii sulfur onto tellurium sites. The crystallite orientation and size can be controlled by manipulating the microstructure at the interface, which can be used to reduce the lattice mismatch at the CdS/CdTe heterojunction interface to improve the structural and electronic quality, leading to better PV device performance.
Glancing angle deposition (GLAD) can be employed to produce polycrystalline thin films with different microstructures for use at the CdS/CdTe interface. In GLAD, the substrate normal and target normal are at an oblique source flux angle (Φ). Microstructural control of the CdTe films by oblique angle deposition can engineer different crystal structures and crystallite orientations of the polycrystalline thin films. In previous studies, an X-ray diffraction (XRD) analysis of room temperature (RT) GLAD CdTe has been shown to exhibit cubic [19,20,21,22], mixed phase [20], or hexagonal CdTe crystal structures for the films prepared by varying source flux angles from Φ = 0° to 80° using different physical vapor deposition techniques, such as thermal evaporation and sputtering [23,24,25,26]. The presence of overlapping cubic and hexagonal phase diffraction peaks implies the mixed phase, with the dominant peaks being the cubic phase.
The metastable hexagonal wurtzite phase of CdTe is produced when sputtered at an oblique angle (Φ = 80°) deposition at RT, as opposed to the more stable cubic zinc blende CdTe [23]. However, XRD patterns of 250 °C GLAD CdTe films exhibit only a cubic or mixed phase structure at any oblique source flux angle [26]. The Φ = 40° GLAD CdTe thin film fabricated at 250 °C shows the highest preferential crystallite orientation and has the largest crystallite size among the high-temperature (HT) GLAD polycrystalline CdTe films [26]. More preferential crystallite orientations and the strong preference for the formation of the stable cubic phase over the metastable wurtzite phase occur at high-temperature CdTe in general due to additional thermal energy increasing the diffusion length of precursors on the surface and facilitating the formation of the more thermodynamically stable crystal structure compared to the material deposited at room temperature. The largest crystallite size and most preferential orientation are observed for high-temperature GLAD CdTe prepared at Φ = 40°, possibly as an effect of a slightly lower nucleation density. Hexagonal and mixed phase CdTe produced by higher deposition angles exhibit a crystal structure more comparable with hexagonal CdS than the zinc blende cubic phase of CdTe. When applied at the CdS/CdTe interface, PV device performance can be optimized by reducing lattice mismatch at the n/p heterojunction interface. Previously, an RT-deposited CdTe solar cell with an RT GLAD CdTe interlayer demonstrated a 0.9% increase in absolute efficiency [23].
This work investigates the role of interfacial tailoring of the phase structure and the resulting effect on the HT CdS/CdTe solar cell device performance. GLAD is used to produce interlayers with wurtzite and mixed phase crystal structures as well as strongly preferentially oriented cubic CdTe, which are then applied between the thin (~100 nm) wurtzite hexagonal CdS window layer and thicker (~2000 nm) zinc blende cubic CdTe absorber. GLAD interlayer deposition conditions are chosen to modify the phase structure (hexagonal and mixed phase), degree of preferential crystallite orientation, and crystallite size. As a result, the impacts of tailoring the phase structure and crystallite orientation at the CdS/CdTe heterojunction interface on device performance are studied using interlayers prepared at Φ = 80° RT with the hexagonal structure and at Φ = 40° HT with the largest crystallite size and most preferentially oriented cubic phase crystallites.
Here, we have incorporated 50 to 350 nm thick Φ = 80° RT GLAD CdTe interlayers and a 150 nm thick Φ = 40° HT GLAD interlayer in CdS/CdTe PV devices with the remainder of the bulk CdTe fabricated at 250 °C, and we have compared the device performance with the baseline PV devices without interlayers fabricated at 250 °C and RT. The hexagonal phase GLAD CdTe interlayers adjacent to the hexagonal CdS heterojunction partner reduce the lattice mismatch between it and cubic CdTe. This enables better tailoring of the phase structure resulting in improved electronic quality at the interface and is expected to enhance PV device performance. PV device performance parameters are determined for all the devices discussed in this work in terms of efficiency, open-circuit voltage (Voc), short-circuit current density (Jsc), fill-factor (FF), and Voc × FF product. The ideality factors of baseline devices, the best performance device, and the Φ = 40° HT GLAD interlayer device are determined to evaluate the diode behavior of these devices. The PV device efficiency, Voc, and FF have been improved and are the highest with the incorporation of a 250 nm Φ = 80° RT GLAD CdTe interlayer between CdS and bulk CdTe layers of an otherwise standard HT CdS/CdTe solar cell due to the reduced lattice mismatch and strain at the interface. Also, the important device parameter, the Voc × FF product, is the highest for the 250 nm Φ = 80° RT GLAD CdTe interlayer device due to better tailoring of the phase structure improving the electronic quality of the interface. An optimized morphology of the GLAD CdTe interface has been identified to improve the PV device performance due to an improved n/p heterojunction interface.

2. Materials and Methods

2.1. Standard CdS/CdTe Solar Cell Fabrication

Standard CdS/CdTe heterojunction solar cells have been fabricated with and without GLAD CdTe interlayers in the superstrate configuration (TEC-12D/CdS/GLAD CdTe-interlayer/CdTe/Cu/Au) as shown in Figure 1. TEC-12D (NSG Pilkington North America, Northwood, OH, USA) [23] is a commercial soda lime glass coated with 300 to 400 nm fluorine-doped tin oxide (SnO2:F) and a 50 nm high-resistivity transparent (HRT) SnO2 layer on top of SnO2:F. Prior to the CdS/CdTe solar cell fabrication, the TEC-12D glass superstrate is ultrasonically cleaned in two steps with and without detergent for 45 min, and then rinsed with deionized water followed by drying with nitrogen gas. The 100 nm n-type CdS window layer is prepared on TEC-12D followed by p-type CdTe absorber layer deposition using RF magnetron sputtering at normal incidence to fabricate all CdS/CdTe cells, with or without a GLAD CdTe interlayer. For standard baseline CdS/CdTe solar cells without interlayers, a 2.2 to 2.5 μm thick bulk CdTe is deposited at HT and RT following CdS deposition, but for cells with an interlayer, the bulk CdTe is deposited after the GLAD CdTe interlayer. After the application of the CdTe bulk layer, CdCl2 treatment is carried out for 30 min in dry air at 387 °C, followed by a methanol wash and nitrogen drying as has been previously optimized [2,23,27,28,29]. To complete the solar cell, a back contact of 3 nm Cu and 40 nm Au is deposited at RT using thermal evaporation onto the CdCl2-treated CdS/CdTe stack with a dot shadow mask. A 4″ × 4″ superstrate is used to fabricate 144 individual dot solar cells, each with an area of 0.126 cm2.
To increase the p-type conductivity of the CdTe absorber layer, Cu diffusion is performed by annealing the complete solar cell device at 150 °C for 30 min in air, enabling the Cu to diffuse into bulk CdTe rather than remaining as a thin layer. The details of the deposition parameters for each layer of the solar cell are listed in Table 1.

2.2. Interlayer CdTe Deposition

GLAD CdTe thin films of different thicknesses are produced at different oblique angles (Φ = 80° and 40°) using RF magnetron sputtering with the schematic shown in Figure 2. Both the GLAD CdTe interlayer and bulk CdTe films are deposited using a 7.62 cm diameter CdTe target (99.999% pure, Kurt. J. Lesker Co., Jefferson Hills, PA, USA) in 15 mTorr Ar gas pressure at 100 W target power. At the normal incidence (Φ = 0°) deposition, the distance between the substrate and target centers is 13.4 cm. Previously, RT GLAD CdTe prepared at Φ = 80° has been shown to have a hexagonal wurtzite crystal phase [23]. Also, a 0.9% increase in absolute efficiency of the RT CdS/CdTe solar cell has been shown by incorporating such a film of 100 nm thickness as an interlayer compared to a standard baseline RT CdS/CdTe solar cell without an interlayer [23]. The hexagonal structure of Φ = 80° RT CdTe has been used as an interlayer due to its similar crystal structure to hexagonal CdS, reducing the lattice mismatch between hexagonal CdS and cubic bulk CdTe, with the resulting phase structure improving the electronic quality at the n/p heterojunction interface and increasing device performance. HT GLAD CdTe prepared at Φ = 40° has the highest preferential crystallite orientation and larger crystallite size relative to normal incidence cubic CdTe and is used to generate a more ordered material present at the heterojunction than the baseline. The Φ = 40° HT GLAD CdTe device has been studied as it has the greatest degree of preferential crystallite orientation and largest crystallite size among the GLAD films studied which reduce grain boundaries with the potential to reduce the photo-generated charge carrier recombination at the interface leading to improved device performance. Here, Φ = 80° RT GLAD CdTe interlayer films prepared under the same conditions with different thicknesses of 50, 100, 150, 200, 250, 300, and 350 nm and a 150 nm Φ = 40° HT GLAD CdTe interlayer have been incorporated between the wurtzite hexagonal n-type CdS window layer and zinc blende cubic p-type CdTe bulk absorber prepared at HT. The 50 to 350 nm thick Φ = 80° RT GLAD CdTe films are expected to have a hexagonal crystal structure, as was indicated previously for >1000 nm films made under the same conditions before and after the CdCl2 treatment [23]. The Φ = 40° HT GLAD CdTe > 1000 nm [26] has a predominately cubic mixed phase structure with preferential orientation of H(002)/C(111) and C(222) crystallites; therefore, a 150 nm GLAD CdTe film is deposited in the same manner. The structural properties of CdTe films can tune the optoelectronic properties of PV device optimization resulting from the GLAD CdTe tailoring of the material structure between hexagonal CdS and cubic CdTe at the interface. The deposition rate of the target material at the center of the substrate is ~31 nm/min for Φ = 0° HT CdTe, ~15 nm/min for Φ = 80° RT GLAD CdTe, and ~28 nm/min for Φ = 40° HT GLAD CdTe. For the PV device characterization, the current density versus voltage (J-V) has been measured using a Keithley 2440 digital source meter in the dark and under one sun AM1.5 (100 mW/cm2) illumination with a 450 W Xenon light source (Oriel, Model 9119, Newport, CA, USA) [15,23,25,27,29].

3. Results and Discussion

Standard CdTe devices without GLAD CdTe interlayers are fabricated with the bulk CdTe deposited at HT and RT and having the device structure shown in Figure 1. HT bulk CdTe films have pronounced crystallinity and more preferentially orientated crystallites with larger grain sizes when compared to RT bulk CdTe films. The larger grains of HT bulk CdTe reduce grain boundaries and defect state density, leading to reduced photo-generated carrier recombination. As expected, the device efficiency of the standard HT CdTe cell without the interlayer is higher than the standard RT CdTe cell without an interlayer. Jsc, Voc, and FF increase from 21.36 mAcm−2, 0.767 V, and 58.62% for the RT baseline device to 22.15 mAcm−2, 0.825 V, and 64.22% for the HT baseline device. The standard HT CdTe device shows a 3.2% absolute increase in efficiency when compared to the standard RT CdTe device, increasing from 9.59 to 12.76%.
Building from the baseline device structure, CdS/CdTe solar cells have been fabricated incorporating Φ = 80° RT GLAD CdTe interlayers with different thicknesses from 50 to 350 nm and a Φ = 40° HT GLAD CdTe interlayer for comparison with devices incorporating bulk CdTe deposited at 250 °C without interlayers. To investigate whether a hexagonal crystal structure interlayer may improve the performance of typical HT CdS/CdTe solar cells by minimizing strain and lattice mismatch, the Φ = 80° RT GLAD hexagonal structured CdT interlayer of different thicknesses, dn, (n = 1 to 7) = 50, 100, 150, 200, 250, 300, and 350 nm is incorporated between the wurtzite hexagonal CdS n-type heterojunction partner and zinc blende cubic CdTe p-type absorber. Previously, it had been observed that the hexagonal structured RT GLAD CdTe interlayer reduces the lattice mismatch between hexagonal CdS and cubic bulk CdTe, reducing the defect density and carrier recombination at the heterojunction n/p interface in devices with RT CdTe bulk absorbers and improving the device performance by a 0.9% absolute increase in efficiency [23]. The potentially mixed phase but predominately cubic HT GLAD CdTe interlayer prepared at Φ = 40°, having the largest crystallite size and highest preferential crystallite orientation with only H(002)/C(111) and C(222) diffraction peaks [26], is incorporated in standard HT CdS/CdTe solar cells to investigate the impact of the reduced grain boundaries and preferential crystallite orientation of the HT GLAD interlayer on PV device performance.
Figure 3 and Figure 4 show the statistical distribution (best 20 performing cells) of device efficiency, Voc, Jsc, FF, and the product of Voc and FF (Voc × FF) for the different device configurations tested and comparison of device performance parameters are shown in Table 2. These devices are fabricated with varying deposition parameters as those (I, II) without interlayers fabricated at RT and 250 °C as baselines; (III) with a 250 °C deposited bulk absorber and a Φ = 40° mixed phase interlayer also deposited at a high temperature, which exhibits highly preferential orientation; and (dn, n = 1–7) with 250 °C deposited bulk absorbers and different Φ = 80° RT interlayers of different thickness which exhibit a hexagonal crystal structure. The device with a 250 nm Φ = 80° RT GLAD CdTe interlayer shows the highest efficiency and Voc × FF increasing from 12.76 to 13.49% (absolute 0.73% increase) and 0.53 to 0.58 V (9.4% increase), respectively, when compared to the best performing standard HT baseline device. The Voc × FF product is the key factor for voltage at the maximum power point as the solar cells are designed to be operated at the maximum power point in commercial use [30]. Practically, this also enables a more direct comparison of device performance when subtle differences in absorber layer thickness impact Jsc and the resulting device efficiency, while Voc and FF may be less strongly impacted. Previous studies have shown that some portion of metastable hexagonal CdTe remains after the higher temperature CdCl2 process, so these improvements in device performance may be attributed to a similar effect whereby hexagonal phase crystallites are present in sufficient quantities to reduce lattice mismatch at the CdS/CdTe interface, but not to the extent that the electronic performance of the bulk layer is reduced. Reducing the lattice mismatch improves the n/p interface, making it less defective with a higher electronic quality which also reduces carrier recombination and increases the device performance [31,32].
When comparing the device performance with different thicknesses of this interlayer, the average Jsc initially decreases and then increases with the increasing interlayer thickness. The initial decrease in Jsc with small interlayer thicknesses can be attributed to the recombination of the photo-generated charge carriers in the bulk CdTe absorber. Although recombination may also occur in these thin GLAD interlayers, devices with thicker GLAD interlayers show increased Jsc, implying that the electronic quality of the bulk CdTe may be compromised when deposited upon thin GLAD interlayers. The latter increase in Jsc with increasing interlayer thickness can be attributed to the increased total CdTe thickness of the bulk and the GLAD interlayer, which consistently increases by ~0.2 mA/cm2 per each 50 nm increase in the interlayer and total thickness. Previously, it has been shown that the Jsc of CdS/CdTe solar cells increases with increasing CdTe thickness up to ~3 or 4 μm [33,34,35,36]. The total thickness of the CdTe absorber, consisting of both the bulk and GLAD interlayer, in any of these devices does not exceed 4 μm, which may have led to a slight increase in Jsc when the interlayer is incorporated to increase the total absorber layer thickness.
The device with a 250 nm Φ = 80° RT GLAD CdTe interlayer device shows the highest Voc due to a reduction in the lattice mismatch from tailoring the phase structure at the interface. The FFs of all interlayer devices except the device with the 250 nm interlayer are comparable to or less than the FFs of HT baseline devices, which may be due to the presence of parasitic resistance leading to reduced diode characteristics of the solar cell. The reduced Voc and FF for devices with GLAD interlayers greater than or less than 250 nm show that interface modification is not optimized. The device incorporating the 250 nm GLAD interlayer shows the highest FF among all devices, which can be attributed to lower parasitic resistive losses. The optimization observed when incorporating a 250 nm thick Φ = 80° RT GLAD CdTe interlayer compared to thinner interlayers may be due to a decreasing strain gradient in the GLAD CdTe with increasing thickness, and it is the highest when in contact with CdS [23,37,38]. However, structural defects also increase with the interlayer thickness due to the relatively low density and pronounced columnar structure of the GLAD interlayer compared to bulk CdTe upon which bulk CdTe grows. Here, a device incorporating a 250 nm GLAD interlayer may be optimized by the reduction of strain at the interlayer/bulk CdTe interface with an interlayer that is not sufficiently thick to negatively impact the subsequent growth of bulk CdTe.
Implementing the Φ = 40° HT GLAD CdTe interlayer in a standard HT CdTe device does not show improvement in device performance. In previous work, the XRD patterns of Φ = 40° HT GLAD CdTe did not exhibit diffraction peaks that can be attributed solely to the hexagonal phase. Predominant diffraction peaks are C(222) for Φ = 40° HT GLAD CdTe and C(400) and C(331) for Φ =0° HT CdTe. The lattice mismatch between the crystal planes of C(222)-oriented crystallites found predominately in Φ = 40° HT GLAD CdTe and hexagonal CdS might be higher than that between those associated with C(400) or C(331)-oriented crystallites found in the more randomly oriented Φ = 0° of HT CdTe. Hence, a larger lattice mismatch between the Φ = 40° HT GLAD CdTe interlayer and CdS than the HT CdTe and CdS causes an increase in carrier recombination at that interface due to the presence of increased strain, unpassivated bonds, or both, and a decrease in Voc, Voc × FF, and PV device efficiency for the Φ = 40° HT GLAD CdTe interlayer PV device compared to the HT baseline device. Jsc of the Φ = 40° HT GLAD CdTe interlayer is higher than that of the HT baseline device, which can be attributed to the greater sum of the bulk and GLAD CdTe interlayer leading to increased photo-generation and collection of carriers. The FF of the Φ = 40° HT GLAD CdTe interlayer is higher than the HT baseline device due to improved diode characteristics, as observed from an improved ideality factor. These results indicate that the most preferentially oriented HT GLAD CdTe interlayer is not beneficial to improving the PV device performance, primarily by its negative effect on Voc. Based on this observation, varying the Φ = 40° HT GLAD CdTe interlayer thickness would not be expected to optimize the device; however, a complete series, as for those based on the Φ = 80° RT GLAD CdTe interlayer, has not be produced. For the Φ = 40° HT GLAD CdTe interlayer device, the highest strain and lattice mismatch occurs at the CdS/GLAD interlayer interface. The greater level of preferential orientation in this GLAD interlayer than in the baseline is likely responsible for the lower Voc. Although the strain will decrease with the increasing interlayer thickness, the structural defects occurring with the increasing GLAD interlayer thickness due to the relatively low density of the GLAD interlayer compared to bulk CdTe upon which bulk CdTe grows will reduce the FF [23,37,38].
Figure 5 shows the light and dark J-V characteristics of the highest efficiency RT and HT baseline PV devices without interlayers and Φ = 40° HT and 250 nm Φ = 80° RT GLAD CdTe interlayer devices. The J-V behavior of the solar is described by the diode equation [39,40,41]:
J = J 0 exp [ q A k B T ( V − J R S ) ] + G S H V − J L ,
where J0 is the reverse saturation current, A is the diode ideality factor, q is the electronic charge, kB is Boltzmann’s constant, T is the temperature, Rs is series resistance, GSH is shunt conductance, and JL is the load current density = Jsc = 0 for dark conditions. From the experimental dark J-V, the solar cell diode ideality factors and series resistances are determined from the behavior of dV/dJ as a function of 1/J as shown in Figure 6. The slope and the intercept of the linear fit of dV/dJ as a function of 1/J are used to find the ideality factor and series resistance, respectively. The series resistances are found to be 4.3 and 4.7 Ωcm2 for the RT and HT baseline devices with ideality factors of 2.2 and 1.5, respectively. Similarly, the series resistances are 6.0 and 2.7 Ωcm2 for the Φ = 40° HT and 250 nm Φ = 80° RT GLAD CdTe interlayer devices with ideality factors of 1.2 and 1.5, respectively. Similar values of A and Rs had been reported previously for these types of device structures [23,39,41,42]. The lower values of A and Rs for the HT CdTe baseline device compared to the RT CdTe baseline device clearly indicate improvement in the diode performance parameters and increased solar cell device performance parameters due to larger crystallite size and reduced grain boundaries, lowering the defect density and reducing the charge carrier recombination in the HT bulk CdTe cell. The almost equal ideality factor and series resistance values for the Φ = 80° RT GLAD CdTe interlayer device compared to the HT baseline device indicate the enhancement in the diode performance parameter due to the improved n/p heterojunction interface, and the improved electronic quality of the n/p interface leading to the increase in Voc, FF, and the overall device performance parameters [30,33,36]. Comparable values for the Φ = 40° HT interlayer device with the HT baseline device indicate the similar diode performance parameters and similar device performance.

4. Conclusions

CdS/CdTe PV devices are fabricated incorporating GLAD interlayers with varying deposition parameters such as temperature, source flux angle, and interlayer thicknesses. Device performance is compared in terms of efficiency, Voc, Jsc, FF, and the product of Voc and FF. RT and 250 °C standard CdS/CdTe solar cells are fabricated without the GLAD CdTe interlayer as the baseline PV devices. The HT standard CdTe PV device incorporating a 250 nm Φ = 80° RT GLAD hexagonal CdTe interlayer shows a 0.73% absolute increase in efficiency when compared to the HT baseline CdTe solar cell without an interlayer. This optimization may be due to a reduction of strain at the interlayer / bulk CdTe interface without negatively impacting the growth of bulk CdTe due to a structural defect from the columnar structure of the underlying GLAD CdTe. This device performance indicates the presence of some hexagonal CdTe to reduce the lattice mismatch at the interface with CdS without reducing the electronic performance of the bulk CdTe absorber layer. Moreover, a ~0.53 V increase in Voc × FF has been found when comparing the 250 nm interlayer device to the HT CdTe baseline solar cell, which could be attributed to better interfacial tailoring at the CdS/CdTe heterojunction interface in the PV device.

Author Contributions

Conceptualization, N.K.J. and N.J.P.; formal analysis, N.K.J.; funding acquisition, N.J.P.; investigation, N.K.J.; resources, N.J.P.; writing—original draft, N.K.J.; writing—review and editing, N.K.J., D.A., I.S., A.S. and N.J.P. All authors have read and agreed to the published version of the manuscript.

Funding

This work is supported by the National Science Foundation (NSF) Grant No. 1711534 and Air Force Research Laboratory under agreement number FA9453-19-C-1002. The U.S. Government is authorized to reproduce and distribute reprints for governmental purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the Air Force Research Laboratory or the U.S. Government.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

The data presented in this study are available on request from the corresponding author.

Conflicts of Interest

The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as potential conflict of interest.

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Materials 16 06812 g001
Figure 1. CdS/CdTe solar cell structure with a thin GLAD CdTe (hexagonal, cubic, or mixed phase) interlayer between hexagonal wurtzite CdS and cubic zinc blende CdTe bulk layer.
Figure 1. CdS/CdTe solar cell structure with a thin GLAD CdTe (hexagonal, cubic, or mixed phase) interlayer between hexagonal wurtzite CdS and cubic zinc blende CdTe bulk layer.
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Materials 16 06812 g002
Figure 2. Schematic of glancing angle deposition (GLAD) sputtering at an oblique angle Φ.
Figure 2. Schematic of glancing angle deposition (GLAD) sputtering at an oblique angle Φ.
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Materials 16 06812 g003
Figure 3. (a) Efficiency, (b) open-circuit voltage (Voc), (c) short-circuit current density (Jsc), and (d) fill-factor (FF) for the 20 best CdTe photovoltaic devices with and without GLAD CdTe interlayers prepared with varying temperatures, source flux angles, and thicknesses.
Figure 3. (a) Efficiency, (b) open-circuit voltage (Voc), (c) short-circuit current density (Jsc), and (d) fill-factor (FF) for the 20 best CdTe photovoltaic devices with and without GLAD CdTe interlayers prepared with varying temperatures, source flux angles, and thicknesses.
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Figure 4. The product of Voc and FF for the 20 best (highest efficiency) CdTe photovoltaic devices with and without GLAD CdTe interlayers prepared with varying temperatures, source flux angles, and thicknesses.
Figure 4. The product of Voc and FF for the 20 best (highest efficiency) CdTe photovoltaic devices with and without GLAD CdTe interlayers prepared with varying temperatures, source flux angles, and thicknesses.
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Materials 16 06812 g005
Figure 5. Dark and light current-voltage characteristics of CdTe solar cells with GLAD HT interlayer (Φ = 40° and 80°) and without (RT and HT bulk CdTe) GLAD CdTe interlayers.
Figure 5. Dark and light current-voltage characteristics of CdTe solar cells with GLAD HT interlayer (Φ = 40° and 80°) and without (RT and HT bulk CdTe) GLAD CdTe interlayers.
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Materials 16 06812 g006
Figure 6. Dark J-V characteristic for the best performing CdTe solar cells plotted as dV/dJ as a function of 1/J to determine ideality factors and series resistances: (I) bulk RT CdTe device without an interlayer, (II) bulk HT CdTe device without an interlayer, (III) Φ = 40° HT GLAD interlayer device, and (IV) Φ = 80° RT 250 nm GLAD interlayer device.
Figure 6. Dark J-V characteristic for the best performing CdTe solar cells plotted as dV/dJ as a function of 1/J to determine ideality factors and series resistances: (I) bulk RT CdTe device without an interlayer, (II) bulk HT CdTe device without an interlayer, (III) Φ = 40° HT GLAD interlayer device, and (IV) Φ = 80° RT 250 nm GLAD interlayer device.
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Table 1. Deposition parameters for CdS/CdTe solar cell component. RT indicates room temperature.
Table 1. Deposition parameters for CdS/CdTe solar cell component. RT indicates room temperature.
LayerDeposition TechniqueTemperatureThickness (nm)Deposition Parameters
Φ (°)Target Power (W)Pressure (mTorr)Ar Flow (sccm)
CdSRF sputtering250 °C100 2001523
GLAD CdTe interlayerRF sputteringRT50–350 801001523
250 °C150 401001523
Bulk CdTeRF sputteringRT2.2–2.4 μm01001523
250 °C2.2–2.4 μm01001523
CuThermal evaporationRT3 --10−3-
AuThermal evaporationRT40--10−3-
Table 2. Comparison of device performance parameters of 20 highest efficiency CdTe solar cells with and without GLAD interlayers prepared as functions of deposition temperature, source flux angle (Φ), and interlayer thicknesses.
Table 2. Comparison of device performance parameters of 20 highest efficiency CdTe solar cells with and without GLAD interlayers prepared as functions of deposition temperature, source flux angle (Φ), and interlayer thicknesses.
CdTe DepositionDevice ParametersBest Cell
Bulk
CdTe Temperature		Interlayer CdTe TemperatureΦInterlayer Thickness (nm) Voc (V)Jsc (mAcm−2)FF (%)Efficiency (%)Voc × FF (V) (× 10−2)
RTw/o interlayer--Best cell0.76721.3658.629.5944.96
Average of 20 cells0.741 ± 0.01719.9 ± 1.455.4 ± 2.38.2 ± 0.8
HTw/o interlayer--Best cell0.82522.1564.2212.7652.98
Average of 20 cells0.797 ± 0.02222.2 ± 0.367.8 ± 1.612.3 ± 0.2
HT40°150Best cell0.75122.9570.2512.1152.76
Average of 20 cells0.757 ± 0.01522.5 ± 0.369.3 ± 1.111.8 ± 0.1
RT80°50Best cell0.77822.2863.6611.0449.53
Average of 20 cells0.761 ± 0.01522.1 ± 0.362.0 ± 1.410.5 ± 0.2
80°100Best cell0.78322.2268.6511.9453.75
Average of 20 cells0.756 ± 0.01222.3 ± 0.466.7 ± 1.611.2 ± 0.3
80°150Best cell0.80822.0669.3712.3656.05
Average of 20 cells0.778 ± 0.02821.9 ± 0.368.7 ± 1.311.7 ± 0.3
80°200Best cell0.80122.4668.3312.2954.73
Average of 20 cells0.765 ± 0.02522.6 ± 0.367.7 ± 1.211.7 ± 0.3
80°250Best cell0.82623.1570.5413.4958.26
Average of 20 cells0.821 ± 0.00522.77 ± 0.469.29 ±1.312.9 ± 0.4
80°300Best cell0.80023.6967.1012.71753.68
Average of 20 cells0.786 ± 0.01123.0 ± 0.565.2 ± 1.011.8 ± 0.3
80°350Best cell0.79323.1366.0112.1152.35
Average of 20 cells0.784 ± 0.00723.2 ± 0.263.2 ± 1.211.5 ± 0.2
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Jayswal, N.K.; Adhikari, D.; Subedi, I.; Shan, A.; Podraza, N.J. Role of CdTe Interface Structure on CdS/CdTe Photovoltaic Device Performance. Materials 2023, 16, 6812. https://doi.org/10.3390/ma16206812

AMA Style

Jayswal NK, Adhikari D, Subedi I, Shan A, Podraza NJ. Role of CdTe Interface Structure on CdS/CdTe Photovoltaic Device Performance. Materials. 2023; 16(20):6812. https://doi.org/10.3390/ma16206812

Chicago/Turabian Style

Jayswal, Niva K., Dipendra Adhikari, Indra Subedi, Ambalanath Shan, and Nikolas J. Podraza. 2023. "Role of CdTe Interface Structure on CdS/CdTe Photovoltaic Device Performance" Materials 16, no. 20: 6812. https://doi.org/10.3390/ma16206812

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