PV Powered High Voltage Pulse Converter with Switching Cells for Food Processing Application

Abstract

In recent years, industries in the suburb have retrofitted their power supply units with solar power supply systems. Using solar power supply systems for various applications, such as food processing, enables energy expense saving. A promising opportunity in the food industry is solar-powered Pulsed Electric Field (PEF) used in the treatment of fruits and their by-products. For this application, a converter is proposed in this paper with a combination of a passive switched inductor cell and a switched capacitor cell. Furthermore, the derived topology possesses an extendable feature. This topology generates high voltage repetitive pulses with a single semiconductor switch and a reduced component count. Dynamic study of the converter is also performed with the derivation of the transfer function. Cost effective, reliable, and simple circuitry are the critical features of this topology. The circuit topology can generate high voltage pulses by increasing the number of switched inductors and switched capacitor cells. A correlation study on the impact of the switched inductor/capacitor cell is also performed and analyzed, which is not usually performed. A 50 W prototype is designed and tested to validate the performance of the converter

1. Introduction

Recently, modern technologies have been introduced to the food processing industries to retain the nutrients in the food when it is processed. For example, moisture extraction processes to inhibit the deterioration and dehydration of vegetables and fruits have been modernized. Thermal drying, osmotic dehydration and vacuum infusions are some of the methods of dehydration. As a substitution to traditional food processing methods, non-thermal food processing techniques have gained a wide range of popularity and serve as a potential tool in fruit preservation. As a non-thermal method in food preservation, Pulsed Electric Field technology involves short electric pulses for the inactivation of micro-organisms and the dehydration of fruits and the preservation of their vital quality and nutrition. Pulsed Electric Field (PEF) stands as a low cost and low energy technology for the cell membrane permeabilization of fruit tissues [1,2]. The PEF maintains the basic structure of food without thermal degradation and a significant temperature rise [3,4]. The benefits of PEF in large scale food industry application as a standalone process, and also as a combination with various methods for the acceleration of fermented food are discussed [1].

The PEF method of microorganism inactivation is found to increase the temperature while food processing. The selection of PEF with nano second pulses can effectively minimize the temperature rise in the food process [5]. Figure 1a illustrates the magnitude of pulses used in the treatment and preservation of various forms of food. The effects of pulse parameters are discussed in the literature, such as kV/cm, pulse frequency and pulse width in the pre-treatment of food, along with conventional methods in the preservation of pine apple, coconut milk—30 kV/cm, square wave pulses, [6]; apple juice—40 kV/cm, 100 pulses per second with 1 μs pulse width [7]; tomato peeling—7.5 kV/cm, 1 kJ/kg, 1 min at 50–70 °C [8]; juice preservation—2.7 kV/cm, 15–1000μs pulses [9]; kiwi fruit dehydration—100 v/cm, 10 μs to 100 s pulses repetitive rectangular pulses [10]; sour cherry juice, apricot and peach nectars preservation—2.4 kV/cm, 210 μs [11]; frozen dry apples—1.07 kV/cm, [12]; and frozen strawberries—850 v/cm, 100μs pulses [13] in various food processing in the industry. Similarly, the energy needed in kJ/kg for the tissue drying of strawberry [14], potato [15], pepper [16], mango [17], apple [18] and carrot [19] is presented in Figure 1b. Figure 1c shows the building blocks of PEF, the compatibility of renewable energy usage in the food processing industry as the source for converters making it a stand alone hybrid system and highlighting the significance of the high voltage converter based pulse generators.

Table 1. Non thermal processing methods—limitations and advantages.

Processing Kinds	Advantages	Limitations
Irradiation [20,21,22]	For several foods it is very effective Gamma rays and electron beam are the other sources available	Public acceptance is limited 7 kilo gray of radiation dose is sanctioned
UV radiation [6,7]	Non thermal method Non usage of chemicals	Harmful to workers in industries when exposed on long term
Super critical carbon dioxide [3,22]	Can be used in process batch (or) continuous batch	Solid foods does not show successful results
HPP(high pressure processing) [22,23]	Can be used of treatment of both solid and liquid samples	Food quality changes
PEF(pulsed electric field) [20,21]	Short duration pulses applied on short term leading to less energy usage and no heat generation	Not suitable for foods unable to withstand higher electric fields. Well suited for liquid samples treatment.

Table 1. Non thermal processing methods—limitations and advantages.

Processing Kinds	Advantages	Limitations
Irradiation [20,21,22]	For several foods it is very effective Gamma rays and electron beam are the other sources available	Public acceptance is limited 7 kilo gray of radiation dose is sanctioned
UV radiation [6,7]	Non thermal method Non usage of chemicals	Harmful to workers in industries when exposed on long term
Super critical carbon dioxide [3,22]	Can be used in process batch (or) continuous batch	Solid foods does not show successful results
HPP(high pressure processing) [22,23]	Can be used of treatment of both solid and liquid samples	Food quality changes
PEF(pulsed electric field) [20,21]	Short duration pulses applied on short term leading to less energy usage and no heat generation	Not suitable for foods unable to withstand higher electric fields. Well suited for liquid samples treatment.

There are converters developed widely with applications based on renewable energy though pertaining to higher efficiencies, control strategies and switching operations. Isolated and non-isolated converters are the two main divisions of DC converters. When developing isolated DC converters, a high-frequency transformer is utilized to create an electrical isolation amid the converter’s input and output. Despite having a programmable positive or negative polarity for the converter’s output and being intended to safeguard sensitive loads, this feature has a severe noise interference characteristic. Table 1 gives the comparison of the PEF method of food processing with the other non-thermal methods adapted in the food processing industry to show its superiority over other non-thermal methods of food processing.

Minimum pulsed electric field voltages in the range of 0.3 kV–5 kV is effective in food processing [24,25,26,27,28,29,30] which implies that even a conventional single stage boost converter output without multiplier stages can be employed in food preservation directly. The low voltage produced by the DC–DC generators generally needs high gain DC–DC converters to meet the requirements of the DC load [31,32]. Other than the conversion of renewable energy, DC–DC converters are used in varied applications such as uninterrupted power supply backup systems, discharge lamps of high intensity for head lamps in automobiles and some equipment in electric traction [33,34,35,36,37].Generally, the voltage stress posed on switches is equal to the output voltage in the high boost DC–DC converters conventionally used in recent years. However, to meet the stress due to high voltage, switches are selected with higher voltage ratings, resulting in high conduction loss. Also, the selection of high duty ratio switches also results in high voltage spikes, increased conduction loss and serious reverse recovery problems in diodes [38,39,40]. The desired high voltage gain can be achieved from various DC–DC isolated converter topologies proposed in the literature [41,42,43]. Saturation of the core is the problem in this type of isolated converter. Moreover, the introduced leakage inductance by the coupled inductors and transformers necessitates the need for a snubber circuit [41], voltage-clamp diode [42] and active-clamp circuit [43,44].

DC–DC converters of the non-isolated type are therefore used where the galvanized isolation is not in need. A high voltage gain is also achieved with a reduced cost and size. Quadratic boost [45], voltage shift [46], capacitor-diode voltage multiplier [47], switched-inductor and switched capacitor [48] based boost converters are some of the non-isolated boost topologies with high gain. The efficiency of a boost converter can be increased in many ways. The cascading of converter stages can increase the voltage gain. An issue of instability and control circuit complexity occurs due to an increase in the component count in cascaded cycling [49]. The gain can be increased by increasing the number of switched inductor and switched capacitor cells. Though there is an increase in the component count in this combination of switched inductor and switched capacitor, they have their own advantages. The leakage reactance stored energy can be absorbed by switched capacitors. No additional snubber circuit is required. To reduce conduction loss, MOSFET with low on-state resistor is suggested for selection [50]. A suitable converter topology efficiently boosting a low input voltage to a high output bus voltage is discussed and experimentally verified in [51,52]. To alleviate the reverse recovery problems and stress on diodes, Schottky diodes are used and a prototype designed for 40 W is experimentally verified for the converter performance [53]. With a simple topology, a high output voltage obtained with a low duty ratio can be easily obtained just by increasing the number of inductor cells of the circuit topology. The results are analyzed experimentally [54]. Another topology, applying the same gating pulses for the two switches, is proposed efficiently to obtain a high conversion ratio with a reduced loss on the converter and experimentally validated [20,21,22,23,55,56,57,58,59].

Substantial attention has been drawn over the past few years by high step ratio dc–dc converters due to their wide range of utilization. In this paper, a new improved converter is presented with an appreciable voltage gain for PEF. It is fed from an isolated DC source of low voltage with a switching inductor (SL) cell and switching capacitor (SC) cell. The output stage of the configuration has a high voltage switch which in turn stands as the main disadvantage of the circuit owing to its high voltage chopping functionality and capacity in turn. High voltage unipolar pulses are produced by the chopping of DC voltage elevated by the high voltage switch. The gain can be increased to a very high value by increasing the number of SL and SC cells.

The advantages of the proposed converters are as follows:

(i)

Single switch topology;

(ii)

Scalable;

(iii)

Regulated output voltage;

(iv)

High efficiency;

(v)

Less stress on semiconductor devices;

(vi)

High voltage output.

The above advantages are verified suitably using simulation results, mathematical derivations and a prototype. The simulation and hardware specifications are tabulated and the results are provided in the following sections.

2. Passive Switched Inductor Switched Capacitor (PSLSC) Converter

The boosted voltage level is achieved by combining a switched inductor cell and a switched capacitor cell, as shown in Figure 2a,b. The boost converter proposed is a combination of switched inductor and switched capacitor cells, as shown in Figure 2c. The proposed converter comprises of a dynamic switch (SW), an output capacitor (C₀₎, output inductor (L₀), load resistance (R_L), a switched inductor cell and a switched capacitor (SC) cell.

3. PSLSC Converter CCM Analysis

In this segment, the operating principle of a PSLSC converter with a SL and SC cell is discussed. The proposed converter shown in Figure 3 is effective in food processing applications. Figure 3 depicts the circuit of the PSLSC converter and further analysis will be carried out with this circuit. The switched inductor (SL) cell consists of two diodes (D_SL1 and D_SL2), an inductor (L and L_SL1) and a capacitor (C_SL1). The SC cell consists of two diodes (D_SC1 and D_SC2) and two capacitors (C_SC1 and C_SC2). The SL cell charges during the ON period and discharges to the load during the OFF condition of the dynamic switch.

3.1. Operating Modes of Converter Proposed in CCM

Mode 1:

The switch ‘SW’ conducts at t = t0. Diodes D_SL1 and D_SL2 are forward biased. The inductors ‘L’ and ‘L_SL1’ are excited by the input DC source Vg. The inductors ‘L’ and ‘L_SL1’ are connected in parallel with capacitor C_SL1. The DC energy source is transferred to the inductor ‘L’. The current Ig is equal to the accumulation of the currents I_L, I_LSL1 and I_CSL1. The capacitors C_SC1 and C_SC2 are connected in series with inductors L₀ as the two diodes D_SC1 and D_SC2 are reverse biased and supply the load resistance R_L. Figure 4 shows the flow of current in the converter circuit during this interval.

Considering the ‘ON’ stage of the switch ‘SW’ in the main circuit and applying the principle of inductor voltage-second balance, the following equations are obtained:

$${{\displaystyle \int }}_0^{{\mathrm{DT}}_{\mathrm{s}}}{\mathrm{V}}_{\mathrm{L}}\mathrm{dt}={{\displaystyle \int }}_0^{{\mathrm{DT}}_{\mathrm{s}}}{\mathrm{V}}_{\mathrm{SL}1}\mathrm{dt}={{\displaystyle \int }}_0^{{\mathrm{DT}}_{\mathrm{s}}}{\mathrm{V}}_{\mathrm{CSL}1}\mathrm{dt}={{\displaystyle \int }}_0^{{\mathrm{DT}}_{\mathrm{s}}}{\mathrm{V}}_{\mathrm{g}}\mathrm{dt}$$

(1)

$${{\displaystyle \int }}_0^{{\mathrm{DT}}_{\mathrm{s}}}{\mathrm{V}}_{\mathrm{LO}}\mathrm{dt}={{\displaystyle \int }}_0^{{\mathrm{DT}}_{\mathrm{s}}}\left(2{\mathrm{V}}_{\mathrm{CSC}1}-{\mathrm{V}}_0\right)\mathrm{dt}$$

(2)

On the application of the principle of capacitor current-second balance to the main circuit while the switch ‘SW’ is in ON state, the following relationships are obtained:

$${{\displaystyle \int }}_0^{{\mathrm{DT}}_{\mathrm{s}}}{\mathrm{I}}_{\mathrm{CSL}1}\mathrm{dt}={{\displaystyle \int }}_0^{{\mathrm{DT}}_{\mathrm{s}}}\frac{{\mathrm{I}}_{\mathrm{g}}}{3}\mathrm{dt}$$

(3)

$${{\displaystyle \int }}_0^{{\mathrm{DT}}_{\mathrm{s}}}{\mathrm{I}}_{\mathrm{CSC}1}\mathrm{dt}={{\displaystyle \int }}_0^{{\mathrm{DT}}_{\mathrm{s}}}{\mathrm{I}}_{\mathrm{CSC}2}\mathrm{dt}=-{{\displaystyle \int }}_0^{{\mathrm{DT}}_{\mathrm{s}}}{\mathrm{I}}_{\mathrm{L}0}\mathrm{dt}$$

(4)

$${{\displaystyle \int }}_0^{{\mathrm{DT}}_{\mathrm{s}}}{\mathrm{I}}_{\mathrm{C}0}\mathrm{dt}={{\displaystyle \int }}_0^{{\mathrm{DT}}_{\mathrm{s}}}\left({\mathrm{I}}_{\mathrm{L}0}-{\mathrm{I}}_0\right)\mathrm{dt}$$

(5)

Mode 2:

During the instant the switch ‘SW’ is turned off, the inductor ‘L’ capacitor C_SL1 and inductor L_SL1 are connected in series as the diodes D_SL1 and D_SL2 are reverse biased. The diodes D_SC1 and D_SC2 are forward biased and they connect the capacitors C_SC1 and C_SC2 in parallel. This makes the voltage boosted to a high value and available across C0 and RL. The current flow path of the converter circuit during this interval is shown in Figure 5.

On the application of the principle of inductor voltage-second balance, to the PSLSC circuit while the switch ‘SW’ is in OFF state, the following relationships are obtained:

$${{\displaystyle \int }}_{{\mathrm{DT}}_{\mathrm{s}}}^{{\mathrm{T}}_{\mathrm{s}}}{\mathrm{V}}_{\mathrm{L}}\mathrm{dt}={{\displaystyle \int }}_{{\mathrm{DT}}_{\mathrm{s}}}^{{\mathrm{T}}_{\mathrm{s}}}\frac{\left({\mathrm{V}}_{\mathrm{g}-}{\mathrm{V}}_{\mathrm{CSC}1}\right)}{3}\mathrm{dt}={{\displaystyle \int }}_{{\mathrm{DT}}_{\mathrm{s}}}^{{\mathrm{T}}_{\mathrm{s}}}{\mathrm{VL}}_{\mathrm{SL}1}\mathrm{dt}$$

(6)

$${{\displaystyle \int }}_{{\mathrm{DT}}_{\mathrm{s}}}^{{\mathrm{T}}_{\mathrm{s}}}{\mathrm{V}}_{\mathrm{L}0}\mathrm{dt}={{\displaystyle \int }}_{{\mathrm{DT}}_{\mathrm{s}}}^{{\mathrm{T}}_{\mathrm{s}}}({\mathrm{V}}_{\mathrm{CSC}1}-{\mathrm{V}}_{\mathrm{CO}})\mathrm{dt}$$

(7)

On the application of the principle of capacitor current-second balance to the PSLSC circuit while the switch ‘SW’ is in OFF state, the following relationships are obtained:

$${{\displaystyle \int }}_{{\mathrm{DT}}_{\mathrm{s}}}^{{\mathrm{T}}_{\mathrm{s}}}{\mathrm{I}}_{\mathrm{CSL}1}\mathrm{dt}=-{{\displaystyle \int }}_{{\mathrm{DT}}_{\mathrm{s}}}^{{\mathrm{T}}_{\mathrm{s}}}{\mathrm{I}}_{\mathrm{L}}\mathrm{dt}$$

(8)

$${{\displaystyle \int }}_{{\mathrm{DT}}_{\mathrm{s}}}^{{\mathrm{T}}_{\mathrm{s}}}{\mathrm{I}}_{\mathrm{CSC}1}\mathrm{dt}={{\displaystyle \int }}_{{\mathrm{DT}}_{\mathrm{s}}}^{{\mathrm{T}}_{\mathrm{s}}}{\mathrm{I}}_{\mathrm{CSC}2}\mathrm{dt}={{\displaystyle \int }}_{{\mathrm{DT}}_{\mathrm{s}}}^{{\mathrm{T}}_{\mathrm{s}}}\frac{{\mathrm{I}}_{\mathrm{L}}-{\mathrm{I}}_{\mathrm{L}0}}{2}\mathrm{dt}$$

(9)

$${{\displaystyle \int }}_{{\mathrm{DT}}_{\mathrm{s}}}^{{\mathrm{T}}_{\mathrm{s}}}{I}_{C0}\mathrm{dt}={{\displaystyle \int }}_{{\mathrm{DT}}_{\mathrm{s}}}^{{\mathrm{T}}_{\mathrm{s}}}(I_{LO}-I_0)dt$$

(10)

3.2. Derivation of PSLSC Converter Voltage Gain

The waveforms related to the voltage and the current of active and passive components of the PSLSC converter in CCM mode are given in Figure 5. On simplifying (1), (2), (6) and (7) the following voltage equations are obtained.

$${\mathrm{V}}_{\mathrm{CSL}1}={\mathrm{V}}_{\mathrm{g}}$$

(11)

$${\mathrm{V}}_{\mathrm{CSC}1}={\mathrm{V}}_{\mathrm{CSC}2}={\mathrm{V}}_{\mathrm{g}}\frac{\left(1+2\mathrm{D}\right)}{\left(1-\mathrm{D}\right)}$$

(12)

The voltage gain ratio of PSLSC converter is

$$\frac{{\mathrm{V}}_0}{{\mathrm{V}}_{\mathrm{g}}}=\frac{\left(1+2\mathrm{D}\right)\left(1+\mathrm{D}\right)}{\left(1-\mathrm{D}\right)}$$

(13)

On simplifying (3), (4), (5), (8), (9) and (10) the following current equations are obtained.

$${\mathrm{I}}_{\mathrm{L}}={\mathrm{I}}_{\mathrm{LSL}1}=\frac{{\mathrm{I}}_0\left(1+\mathrm{D}\right)}{1-\mathrm{D}}$$

(14)

$${\mathrm{I}}_{\mathrm{LO}}={\mathrm{I}}_{\mathrm{O}}$$

(15)

Equation (13) is the voltage ratio of the proposed converter. When the numbers of SL and SC cells are increased, the gain of the converter increases. The increase in the number of switched inductor cell increases the voltage ratio and makes no change with respect to the gain ratio with respect to odd (or) even numbers of switched inductor cells. Whereas the addition of switched capacitor cells in odd (or) even numbers makes considerable changes of the voltage boost ratio. The generalized voltage boost ratio with ‘M’ number of cells added is given below.

$${\mathrm{G}}_{\mathrm{V}\left(\mathrm{M}=1,3,5,\dots \mathrm{..}\right)}=\frac{{\mathrm{V}}_0}{{\mathrm{V}}_{\mathrm{g}}}=\frac{\left[1+2{\mathrm{M}}_{\mathrm{SL}}\mathrm{D}\right]\left[{\mathrm{M}}_{\mathrm{SC}}+\mathrm{D}\right]}{\left[1-\mathrm{D}\right]}$$

(16)

$${\mathrm{G}}_{\mathrm{V}\left(\mathrm{M}=2,4,6,\dots \mathrm{..}\right)}=\frac{{\mathrm{V}}_0}{{\mathrm{V}}_{\mathrm{g}}}=\frac{\left[1+2{\mathrm{M}}_{\mathrm{SL}}\mathrm{D}\right]\left[{\mathrm{M}}_{\mathrm{SC}}+1\right]-\mathrm{D}]}{\left[1-\mathrm{D}\right]}$$

(17)

The proposed topology waveforms are given in Figure 6a,b. Figure 6a shows the wave forms of voltages depicting the gate pulse of switch ‘SW’, V_CSL1, V_DSL1, V_DSL2, V_CSC1, V_CSC2 and V_SW from top to bottom. Figure 6b shows the wave forms of currents that are related to gate pulse of switch ‘SW’, I_LSC1, I_L0, V_g and V_OUT from topmost to bottom.

A correlation table is made with the increase in odd and even number of switched inductor and switched capacitor cells and is shown in

Table 2. Correlation for 1, 2…M_SLn switched-inductor cell (M_SL) with single Switched-capacitor cell.

Switched-inductor ell (MSL)	Number of SL Cell	Voltage Ratio	Switch Stress in Terms of Vg	Switch Stress in Terms of Vo
	1	$\frac{(1+2D)(1+D)}{1-D}$	$\frac{V_g(1+2D)}{1-D}$	$\frac{V_O}{1+D}$
	2	$\frac{(1+4D)(1+D)}{1-D}$	$\frac{V_g(1+4D)}{1-D}$
	3	$\frac{(1+6D)(1+D)}{1-D}$	$\frac{V_g(1+6D)}{1-D}$
	N	$\frac{(1+2M_{SL}D)(1+D)}{1-D}$	$\frac{V_g(1+2M_{SL}D)}{1-D}$

and

Table 3. Correlations for 1, 2…M_SCn Switched-capacitor cell (M_SC) with single Switched-inductor cell.

Switched-capacitor cell (MSC)	Number of SC Cell	Voltage Gain	Switch Stress in Terms of Vg	Switch Stress in Terms of Vo
	1	$\frac{(1+2D)(1+D)}{1-D}$	$\frac{V_g(1+2D)}{1-D}$	$\frac{V_O}{1+D}$
	2	$\frac{(1+2D)(3-D)}{1-D}$		$\frac{V_O}{3+D}$
	3	$\frac{(1+2D)(3+D)}{1-D}$		$\frac{V_O}{3+D}$
	n odd	$\frac{(1+2D)(M_{SC}+D)}{1-D}$		$\frac{V_O}{M_{SC}+D}$
	n even	$\frac{(1+2D)((M_{SC}+1)-D)}{1-D}$		$\frac{V_O}{(M_{SC}+1)-D}$

.

It is observed from Table 2 and Table 3 that the increase in switched capacitor cells gives more gain when compared with the gain obtained with an increase in switched inductor cells. The increase in odd or even numbers of switched capacitor cells poses no change in switch stress in terms of V_g as can be found from Table 3. Increase in number of switched capacitors further decreases the switch stress in terms of V₀. The voltage stress on switch in terms of V₀ remains constant irrespective of the increase in switched inductor cells in odd (or) even numbers as can be observed from Table 2. The voltage stress on the switch in terms of V_g is considerably high with an increase in the number of cells of the switched inductor. A proper selection of M_SC and M_SL can give a very high voltage gain suitable for the generation of high voltage pulses with minimal stress on the switch.

4. Analysis of PSLSC Converter in DCM (Discontinuous Conduction Mode)

When a converter is designed for an application, it is necessary to study the operation of the converter in DCM and BCM conditions. This section elaborates on the operation of the proposed PSLSC converter in discontinuous conduction.

Figure 7b shows the current flow in inductor during D₁T_S, D₂T_S and D₃T_S. The average current through the inductor L₀ is found. From Figure 7a, the current in inductor is obtained as

$$i_{L0}\left(t\right)=i_{C0}\left(t\right)+\frac{v\left(t\right)}{R_0}$$

(18)

$$\mathrm{Average}\mathrm{current}=\langle {\mathrm{i}}_{L0}\rangle =\frac{1}{T}{{\displaystyle \int }}_0^{T_S}{i}_{L0}\left(t\right)dt=\frac{V_0}{R_0}$$

(19)

The area of the triangle also gives the average current through the inductor L₀.

$$\mathrm{Area}\mathrm{of}\mathrm{Triangle}=\frac{1}{2}\left[\frac{2V_C-V_0}{L_0}\right]D_1{T}_S\ast \left[D_1+D_2\right]$$

(20)

Equating (19) and (20), the (21) is obtained.

$$\frac{V_0}{R_0}=\frac{1}{2}\left[\frac{2V_g-V_0}{L_0}\right]D_{1 }{T}_S\left[D_1+D_2\right]$$

(21)

Considering Figure 7b, the gain of the converter is determined. The volt-second balance expression in ON mode is obtained as

$$V_g{D}_1{T}_S+\frac{\left(V_g-V_C\right)}{3}{D}_2{T}_S=0$$

(22)

Simplifying (22), the following expression is obtained as

$$V_C=\left[1+\frac{3D_1}{D_2}\right]V_g$$

(23)

Similarly, the volt-second balance law is applied on the non-conducting period of the converter in DCM mode and the obtained expression is

$$2V_C{D}_1-V_0{D}_1+V_C{D}_2-V_0{D}_2=0$$

(24)

After simplifying the gain of the converter under DCM is given as

$$V_0=\left[1+\frac{3D_1}{D_2}\right]\left[\frac{2D_1+D_2}{D_1+D_2}\right]V_g$$

(25)

where $K=\frac{2L_0}{R_0{T}_S}$.

5. Analysis of PSLSC Converter Topology in BCM (Boundary Conduction Mode)

The boundary between CCM and DCM is BCM. While the converter proposed operates in BCM, the gain of CCM and DCM are equal. The critical value of ‘K’ obtained is given in Equation (29). Figure 8 shows the curve of ‘Kcrit’ in terms of ‘D’. At the boundary of DCM and CCM, the converter operates in a condition where K=Kcrit. When K>Kcrit, the converter functions in CCM ($I_L>∆i_L)$ and when K<Kcrit the converter functions in DCM $(I_L<∆i_L)$.

The inductor current ripple is given as

$$∆i_L=∆i_{LSL1}=\frac{V_{g}D{T}_S}{2L}$$

(26)

Considering the operation of the converter at the boundary condition

$$\frac{I_0\left(1+D\right)}{1-D}>\frac{V_{g}D{T}_S}{2L}$$

(27)

On substituting (26) in (27) and rearranging the Kcrit value is obtained as

$$\frac{2L{f}_s}{R_0}>\frac{\left(1-D\right)D}{G_{VCCM}}$$

(28)

$$K_{crit}\left(D\right)=\frac{D\left(1-D\right)}{G_{VCCM}}$$

(29)

From Figure 8 it is observed that at D = 0.2, the value of Kcrit is 0.07619. When K > 0.07619, the PSLSC functions in CCM and when K < 0.07619 it functions in DCM.

6. Design of PSLSC Converter and Stress Analysis

a 

Inductors Design

The input inductor ‘L’ of the converter proposed is calculated in the CCM as follows:

$$L=\frac{R_{L }{(1-D)}^{2}D}{2\left(2D^2+3D+1\right)\left(1+D\right)f_s}$$

(30)

The inductor of switched inductor cell is found to be same as that of input inductor. It is expressed as

$$L_{SL1 }=\frac{R_{L }{(1-D)}^{2}D}{2\left(2D^2+3D+1\right)\left(1+D\right)f_s}$$

(31)

whereas the fs represents the switching frequency and R0 is the load resistance. The input inductor is also a function of frequency, load resistance and duty ratio. It is expressed as

$$L_0=\frac{R_L\left(1-D\right)D}{2\left(1+D\right)f_s}$$

(32)

b 

Capacitor Design

The average current passing through the capacitors during their conduction period is considered and the relationship of the capacitors is obtained as follows using the Equations (11) and (12). The ripple voltage is considered as 10% of the capacitor voltage. The various capacitor expressions are as follows:

$$C_{SL1}=\frac{\left(2D^2+3D+1\right)I_{0}D}{∆V_{cSL1}{f}_s\left(1-D\right)}$$

(33)

$$C_{SC1}=C_{SC2}=\frac{I_{0}D}{∆V_{CSC1}{f}_s}$$

(34)

$$C_0=\frac{I_{0}D}{∆V_{C0}{f}_s}$$

(35)

c 

PSLSC converter Switch Stresses

Based on the analysis of the PSLSC converter in CCM, the switch stresses on the components are calculated and tabulated in

Table 4. Switch stresses of PSLSC converter.

Parameters		PSLSC Converter
Voltage stress of the diodes in switched inductor cell	DSL1	$\frac{V_g}{\left(1-D\right)}$
	DSL2
Voltage stress of the diodes in switched capacitor cell	DSC1	$\frac{V_g}{{\left(1-D\right)}^2}$
	DSC2
Voltage stress on switch	SW	$\frac{V_g}{{\left(1-D\right)}^2}$
RMS current of diodes in SL cell	DSL1	$\frac{I_0\left[1+2D\right]\left[1+D\right]}{3\left[1-D\right]} .\sqrt{D}$
	DSL2
RMS current of the diodes in SC cell	DSC1	$\frac{2I_0}{\sqrt{1-D}} .D$
	DSC2
RMS current of the switch	SW	$\frac{I_0\left[1+2D\right]\left[1+D\right]}{\left[1+D\right]} .\sqrt{D}$
RMS value inductor current of the PSLSC topology	L	$\frac{I_0\left[1+D\right]}{\left[1-D\right]}$
	LSL1
	L0	$\frac{\left(1-D\right)I_g}{\left[2D^2+3D+1\right]}$
RMS value capacitor current of the PSLSC topology	CSL1	$I_0\frac{\left(1+2D\right)}{\left(1+D\right)\left(1-D\right)}\sqrt{\frac{3-2D}{3}}$
	CSC1	$I_0\sqrt{\frac{D}{1-D}}$
	CSC2
	C0	$I_0\sqrt{D}$
Average load current	RL	$\frac{\left(1-D\right)I_g}{\left[2D^2+3D+1\right]}$

. The parasitic factors are ignored for the convenience of calculating the voltage current stress. All the stress depends on the duty ratio and by the proper selection of the duty ratio the efficiency can be maintained high with nominal stress on the components.

7. Dynamic Analysis of PSLSC Converter

The state space equations are used to obtain a piecewise linear model in order to describe the behavior of the converter proposed. State space equations are obtained resulting in electrical trajectories, owing to the turn ON/OFF conditions of switch and diodes. V_g and V₀ are the input and output variables, respectively. The inductor currents i_L, i_LSL1 and i_L0 and capacitor voltages V_CSL1, V_CSC1, V_CSC2 and V_C0 form the variables of the state space equations. The inductors L and L_SL1 are selected to be of the same value while all the capacitors in the circuit are selected to be of the same value. The same value components usage results in same voltage and current across them when they are connected in series and parallel with respect to the ON/OFF condition of the switch. The inductor currents and capacitor voltages are treated as single variable with the assumption that there is no generality loss. From Figure 5, it can be observed that the inductors L and L_SL1 are in series and capacitors C_SC1, C_SC2 and C₀ are in parallel, which means the currents through L and L_SL1 are equal and the voltages of C_SC1, C_SC2 and C₀ are same. Therefore, the state variables V_CSC1, V_CSC2 and i_LSL1 are invalid, while the state variables i_L, i_L0, V_C and V_C0 are considered. Similarly, the voltages in capacitors C_SC1, C_SC2 and C₀ are equal and the currents through L and L_SL1 are equal as shown in Figure 4. The state variables V_CSC1, V_CSC2 and i_LSL1 are invalid, the variables i_L, i_L0, V_C and V_C0 are considered. The PSLSC system is represented in a steady state with state variables i_L, i_L0, V_C and V_C0 and the input-output variables V_g and V₀.

The steady-state representation of a system in general is given by

$$\dot{x\left(t\right)}=Ax\left(t\right)+Bu\left(t\right)$$

(36)

$$y\left(t\right)=Cx\left(t\right)+Du\left(t\right)$$

(37)

During the ON and OFF conditions, the state equation of the system in general form is given as follows:

$$\dot{x\left(t\right)}=A_{1}x\left(t\right)+B_{1}u\left(t\right)$$

(38)

$$y\left(t\right)=C_{1}x\left(t\right)+D_{1}u\left(t\right)$$

(39)

$$\dot{x\left(t\right)}=A_{2}x\left(t\right)+B_{2}u\left(t\right)$$

(40)

$$y\left(t\right)=C_{2}x\left(t\right)+D_{2}u\left(t\right)$$

(41)

The proposed PSLSC converter state equations during the ON and OFF conditions are given as follows:

During ‘ON’ condition of the switch

$$\left[\begin{array}{c}\dot{i_L}\\ \dot{i_{L0}}\\ \dot{v_C}\\ \dot{v_{C0}}\end{array}\right]=\left[\begin{array}{cccc}0& 0& 0& 0\\ 0& 0& \frac{2}{L_0}& \frac{-1}{L_0}\\ 0& \frac{-1}{C}& 0& 0\\ 0& \frac{-1}{C_0}& 0& \frac{-1}{R_L{C}_0}\end{array}\right]\left[\begin{array}{c}{i}_L\\ i_{L0}\\ v_C\\ v_{C0}\end{array}\right]+\left[\begin{array}{c}\frac{1}{L}\\ 0\\ 0\\ 0\end{array}\right]\left[v_g\right]$$

(42)

during ‘OFF ‘condition of the switch

$$\left[\begin{array}{c}\dot{i_L}\\ \dot{i_{L0}}\\ \dot{v_C}\\ \dot{v_{C0}}\end{array}\right]=\left[\begin{array}{cccc}0& 0& \frac{-1}{3L}& 0\\ 0& 0& \frac{1}{L_0}& \frac{-1}{L_0}\\ \frac{-1}{2C}& \frac{-1}{2C}& 0& 0\\ 0& \frac{1}{C_0}& 0& \frac{-1}{R_L{C}_0}\end{array}\right]\left[\begin{array}{c}{i}_L\\ i_{L0}\\ v_C\\ v_{C0}\end{array}\right]+\left[\begin{array}{c}\frac{1}{3L}\\ 0\\ 0\\ 0\end{array}\right]\left[v_g\right]$$

(43)

the output voltage is given as

$$\left[V_0\right]=\left[\begin{array}{cccc}0& 0& 0& 0\end{array}\right]\left[\begin{array}{c}{i}_L\\ i_{L0}\\ v_C\\ v_{C0}\end{array}\right]+\left[0\right]\left[v_g\right]$$

(44)

The generalized input to output transfer function is given as

$$\frac{V_0\left(S\right)}{V_g\left(S\right)}=C{\left[SI-A\right]}^{-1}B$$

(45)

On substituting the values for A, B, C and D matrices, the gain expression under dynamic analysis is as follows:

$$\frac{V_0\left(S\right)}{V_g\left(S\right)}=\left[\begin{array}{cccc}0& 0& 0& 1\end{array}\right]{\left[\left[\begin{array}{cccc}S& 0& 0& 0\\ 0& S& 0& 0\\ 0& 0& S& 0\\ 0& 0& 0& S\end{array}\right]-\left[\begin{array}{cccc}0& 0& \frac{-D^{\prime }}{3L}& 0\\ 0& 0& \frac{1+D}{L_0}& \frac{-1}{L_0}\\ \frac{D^{\prime }}{2C}& \frac{-\left(1+D\right)}{2C}& 0& 0\\ 0& \frac{1}{C_0}& 0& \frac{-1}{R_0{C}_0}\end{array}\right]\right]}^{-1}.\left[\begin{array}{c}\frac{1+2D}{3L}\\ 0\\ 0\\ 0\end{array}\right]$$

(46)

where

$$A=\left[\begin{array}{cccc}0& 0& \frac{-D^{\prime }}{3L}& 0\\ 0& 0& \frac{1+D}{L_0}& \frac{-1}{L_0}\\ \frac{D^{\prime }}{2C}& \frac{-\left(1+D\right)}{2C}& 0& 0\\ 0& \frac{1}{C_0}& 0& \frac{-1}{R_0{C}_0}\end{array}\right]$$

(47)

$$B=\left[\begin{array}{c}\frac{1+2D}{3L}\\ 0\\ 0\\ 0\end{array}\right]$$

(48)

$$C=\left[\begin{array}{cccc}0& 0& 0& 1\end{array}\right]$$

(49)

$$D=\left[0\right]$$

(50)

By simplifying and rearranging, the input to output transfer function is obtained as

$$\frac{V_0\left(s\right)}{V_g\left(s\right)}=\frac{\frac{\left(1-D\right)\left(1+2D\right)D^{\prime }}{6L{L}_{0}C{C}_0}}{\frac{S^{4}6L{L}_{0}C{C}_0{R}_0+S^{3}6L{L}_{0}C+S^2\left[D^{\prime 2}{L}_0{C}_0{R}_0+{\left(1+D\right)}^{2}3L{C}_0{R}_0+6LC{R}_0\right]+S\left[D^{\prime 2}{L}_0+{\left(1+D\right)}^{2}6L\right]+R_0{D}^{\prime 2}}{6L{L}_{0}C{C}_0{R}_0}}$$

(51)

On further simplification, the transfer function of the PSLSC converter is finally obtained as

$$\frac{V_0\left(S\right)}{V_g\left(S\right)}=\frac{\frac{\left(1+2D\right)\left(1+D\right)}{\left(1-D\right)}}{\left[1+S\left[\frac{L_0}{R_0}+\frac{6{\left(1+D\right)}^{2}L}{D^{\prime 2}{R}_0}\right]+S^2\left[L_0{C}_0+\frac{3L{C}_0{\left(1+D\right)}^2}{D^{\prime 2}}+\frac{6LC}{D^{\prime 2}}\right]+S^3\frac{6L{L}_{0}C}{D^{\prime 2}{R}_0}+S^4\frac{6L{L}_{0}C{C}_0}{D^{\prime 2}}\right]}$$

(52)

The transfer function in Equation (52) is used to design the voltage feedback compensation. To determine the stability of the system, the following parameters are used. Vg = 300 V, Vo = 1.8 kV, R_o = 500 Ω, D = 0.5 and f_s = 50 kHz. The reason for this operating voltage for the proposed converter is that the converter is designed for food processing applications. The power rating of this application is around 50–100 W. The bode plot and pole-zero map of the transfer function given in Equation (52) is given in Figure 9. It can be found from the plot and map that the system is not stable and the selection of a suitable converter can make the system stable. Red cross denotes the poles in the map.

8. Efficiency Analysis

This section discusses the proposed converter efficiency. Figure 10 shows the equivalent circuit of the proposed converter. The internal resistances of the diodes DSL1, D_SL2, D_SC1 and D_SC2 are represented as R_fDSL1, R_fDSL2, R_fDSC1 and R_fDSC2, respectively. The ESR of the inductors L, L_SL1 and L₀ are represented as R_L, R_LSL1 and R_L0. Similarly, ESR of capacitors C_SL1, C_SC1, C_SC2 and C₀ are represented as R_CSL, R_CSC1, R_CSC2 and R_C0, respectively. The ‘ON’ state resistance of the switch is denoted as R_SW.

The power loss on the switch is denoted as PSW and it is given as

$$P_{SW}=P_{SW\left(conduction\right)}+P_{SW\left(switching\right)}$$

(53)

$$P_{SW\left(conduction\right)}=\frac{I_0^2{\left(1+2D\right)}^2{\left(1+D\right)}^{2}D{R}_{DS\left(on\right)}}{{\left(1-D\right)}^2}$$

(54)

$$P_{SW\left(switching\right)}=\frac{f_s{C}_0{V}_{max}^2}{2} =\frac{f_s{C}_0{V}_g^2{\left(1+2D\right)}^2}{2{\left(1-D\right)}^2}$$

(55)

The power losses on the diodes are given as PD and PD as follows:

$$P_D=\frac{2I_0\left(1+2D\right)\left(1+D\right)D{V}_{F }}{3\left(1-D\right)}+4I_{0 }D{V}_{F }+\frac{2I_0^2{\left(1+D\right)}^2{\left(1+2D\right)}^2}{9{\left(1-D\right)}^2}D{R}_F+ \frac{4I_0^2{D}^2}{1-D}{R}_F$$

(56)

P_L and P_C denotes the inductor and capacitor loss and is given as

$$P_L=\frac{2{[I_{0 }\left(1+D\right)]}^2{R}_L}{{\left(1-D\right)}^2} +I_0^2{R}_L$$

(57)

$$P_C=\left[\frac{I_0^2{\left(1+2D\right)}^2{\left(1+D\right)}^2\left(3-2D\right)\left(1+D\right)D{V}_{F }}{3{\left(1-D\right)}^2} +\frac{2I_0^{2}D}{\left(1-D\right)}+ I_0^2 D\right]R_C$$

(58)

The total power loss (PLOSS) in the converter is given as

$$P_{LOSS}=P_{SW}+P_D+P_L+P_C$$

(59)

The efficiency ($\eta )$of the proposed high step-up converter is given by

$$Efficiency=\eta =\frac{P_0}{P_{in}}=\frac{1}{1+(\frac{P_{LOSS}}{P_0})}$$

(60)

9. Comparative Study

Table 5 presents the comparison of the proposed converter and other DC–DC converters developed recently in terms of voltage gain, component count, extendibility and switch count. Figure 11 demonstrates the voltage ratio versus the duty cycle for the converters in [51,52,53,54,55,56]. It is clear that the boost ratio of the converter PSLSC is higher when compared with the converters in [52,53,54,55,56]. This characteristic feature makes the converter PSLSC much more suitable for step-up application in a higher range. At the expense of a higher component quantity, the converters [51,52,53,54,55,56] are shown to have a high voltage gain compared with the proposed topology. For instance, the [53] has a single switch topology as that of the proposed one but the extendibility and boost ratio is less when compared with the proposed converter. Though a converter [54] offers extendibility, it has more switch counts and switch stresses than the PSLSC converter.

Table 5. Comparison of PSLSC converter and existing high gain converters.

Converter	Voltage Gain	Component Count				Extendable	Single Switch Topology
		Sw	D	L	C
Proposed converter	$\frac{\left(1+2M_{SL}D\right)\left(1+M_{SC}D\right)}{1-D}$	1	2(MSL + MSc)	MSL + 2	1 + MSL + 2MSc	Yes	✓
APIC converter [54]	$\frac{1+\left(n+1\right)D}{1-D}$	n + 2	2n	n + 2	1	Yes	X
ASLPSC converter [55]	$\frac{1+3D}{1-D}$	2	2	3	3	No	X
Modified sepic [52]	$\frac{1+3D}{1-D}$	2	2	3	3	No	X
SH-SLC converter [56]	$\frac{1+3D}{1-D}$	2	7	4	1	No	X
Switched inductor [51]	$\frac{3-D}{1-D}$	2	3	2	3	No	X
Boost with VM cell [53]	$\frac{2+D}{1-D}$	1	4	2	5	No	✓

Table 5. Comparison of PSLSC converter and existing high gain converters.

Converter	Voltage Gain	Component Count				Extendable	Single Switch Topology
		Sw	D	L	C
Proposed converter	$\frac{\left(1+2M_{SL}D\right)\left(1+M_{SC}D\right)}{1-D}$	1	2(MSL + MSc)	MSL + 2	1 + MSL + 2MSc	Yes	✓
APIC converter [54]	$\frac{1+\left(n+1\right)D}{1-D}$	n + 2	2n	n + 2	1	Yes	X
ASLPSC converter [55]	$\frac{1+3D}{1-D}$	2	2	3	3	No	X
Modified sepic [52]	$\frac{1+3D}{1-D}$	2	2	3	3	No	X
SH-SLC converter [56]	$\frac{1+3D}{1-D}$	2	7	4	1	No	X
Switched inductor [51]	$\frac{3-D}{1-D}$	2	3	2	3	No	X
Boost with VM cell [53]	$\frac{2+D}{1-D}$	1	4	2	5	No	✓

10. Simulation Results

A simulation circuit is designed with the rating of 65 W and 1.8 kV output voltages. From the Expressions (34)–(39), the values of inductors and capacitors are calculated as given in

Table 6. Design parameters of PSLSC converter.

Sno	Parameters	Values
High gain converter-Specifications
1	Input voltage	300 V
2	Output voltage	1.8 kV
3	Duty cycle	0.5
4	Switching frequency	50 kHz
5	Gain	6
6	Inductor	2 mH, 10 mH
7	Capacitor	10 µF
8	Load resistance	500 Ω
HV switch specification
9	Switching frequency	300 V
10	Pulse width	1.8 kV
11	Repetitive pulse rate	0.5
12	Duty cycle	50 kHz

. Table 6 gives the chosen design specifications of the proposed converter. This simulation analysis is performed to validate that the PSLSC converter is suitable for pulsed electric field (PEF) in the food industry. For vegetable tissue drying, the required pulsed electric field is 0.5–5 kV/cm. In this aspect, we have assumed the distance between the electrode as 1 cm and the area of the plate as 1 cm². With these specifications, the equivalent resistance of the sample to be dried is calculated as 500 Ω (1 cm/(2000 µs/cm × 1 cm²)).

The simulation is carried out in an nl5 simulator. The reason for choosing the output voltage of the converter as 1.8 kV is illustrated in Figure 11a. For vegetable and fruit juice expression and tissue drying, the required high voltage pulses ranges from 0.3 to 5 kV. Figure 11b shows the simulation circuit with the design values of each of the components exactly as used in the simulator. The obtained output voltage, switch and diodes’ stress in terms of voltage are given in Figure 11c–f.

Figure 11e presents the regulated voltage obtained from the PSLSC converter with 300 V input voltage and a gain of six. A high voltage switch is used to chop this regulated dc voltage with a 10% duty cycle and a switching frequency of 1 kHz. The repetitive high voltage pulse is presented in Figure 11f.

Table 7. Comparison of simulation and theoretical results.

Sno	Parameters	Theoretical Formulae	Theoretical Results	Simulation Result
1	Output voltage	$\frac{V_g\left(1+2D\right)\left(1+D\right)}{1-D}$	1.8 kV	1.8 kV
2	Switched capacitor voltage	$\frac{V_g\left(1+2D\right)}{1-D}$	1.2 kV	1.19 kV
3	Switch voltage	$\frac{V_g\left(1+2D\right)}{1-D}$	1.2 kV	1.19 kV
4	Capacitor in switched inductor cell	$V_g$	300 V	299.6 V
5	Average diode voltage in switched inductor cell	$\frac{V_g\left(D\right)}{1-D}$	300 V	299.6 V
6	Average diode voltage in switched capacitor cell	$\frac{V_g\left(1+2D\right)D}{1-D}$	600 V	603 V

presents the comparative result which depicts the validation of theoretical study with the simulation results. From this table, it is clear that the voltage rating of the components in the converter is lesser than the output voltage with the single SL and SC cells. In this case, if the SL and SC cells are extended to generate high voltage pulses then the voltage rating of the components will be further reduced due to the division of the voltage in the components. The efficiency of the converter is noted to be 93% for this rating. Figure 12 shows the comparison of the proposed PSLSC converter with the converters in [33,58] to highlight the advantage of the converter.

11. Experimental Results

The proposed PSLSC converter is tested for its design effectiveness for a 10 V input voltage and a 42 V output with 50 W to verify the theoretical analysis in CCM mode of the operation. The list of hardware components taken for the construction of prototype is given in

Table 8. Hardware Specifications of PSLSC converter.

Sl.no	Parameters	Values	Prototype Tested
PSLSC converter-Specifications
1	Input voltage	10 V
2	Output voltage	42 V
3	Duty cycle	0.4
4	Switching frequency	50 kHz
5	Gain	4.2
6	Inductor	15 µH, 50 µH
7	Capacitor	10 µF
8	Power rating	40 W
HV switch specification
9	Switching frequency	50 kHz
10	Pulse width	10 µs
11	Repetitive pulse rate	50,000/s

. The prototype is scaled down and tested to confirm the potential ability of the proposed PSLSC high voltage pulse generator. The photograph of the experimental setup with the results obtained is presented in Figure 13a–h. the pulse generator is fed with the input voltage of 10 V and it operates with the duty cycle of 0.4 to generate the output voltage of 42 V. Pulsed output voltage is obtained with a 10-microsecond pulse width and the obtained data are presented in Figure 13b.

From the results obtained from the prototype, it is more obvious that the scaled down prototype generates the desired voltage required for the mentioned application. It generates the pulse with the width of 10 µs and a repetition rate of 500 per second. The operation of switched inductor cell is validated with the results obtained across the L and LSL1. This is verified with the results illustrated in Figure 13e,f. These two inductors are parallelly charged and discharged serially at the ON and OFF conditions of the switch.

12. Conclusions

In this paper, a high voltage pulse generator is proposed for food processing which can be used for mechanical extraction, solid-liquid extraction, dehydration, freezing, etc. The design steps involved in this topology are presented. Steady-state and dynamic study is performed in a continuous conduction mode and the necessary waveforms are presented. It is noted that the topology has an attractive feature of extendable capability for increasing the voltage gain. This topology is also more suitable to domestic use if it is presented with multiple SL and SC cells and it can be integrated with the available standard voltage source in the domestic location. Furthermore, the converter can employ lower rating components with the integration of multiple cells with the feature of extendibility. This feature allows us to generate high voltages in a kV range with low voltage components. To meet up to the high voltage need of practical food processing applications, the number of multiplier stages need to be increased. This increases the number of components, cost and thereby the weight of the converter. However, the operation of the circuit is simple as it is a single switch topology. High rated switches need to be selected when the numbers of converter stages are increased for higher voltage applications and operations.

Dynamic study is performed using state–space analysis and the inference from the frequency response is discussed. The efficiency of the converter is observed to be 93%. A simulation study is performed with 1.8 kV, 65 W rating to generate a repetitive high voltage pulse at 500 pulses/second with a 100 µsec pulse width. Finally, a scaled down prototype is tested with a 50 W rating and the repetitive pulse is obtained with 42 V. The way to perform the MPPT action for the proposed converter is the future scope.