An Embedded Half-Bridge Γ-Z-Source Inverter with Reduced Voltage Stress on Capacitors

Abstract

In this paper, an embedded half-bridge Z-source inverter based on gamma structure is proposed. In contrast with the classical half-bridge inverter, the proposed inverter can generate zero voltage levels in output. High voltage gain and low voltage stress on capacitors are the main advantages of the proposed converter. The value of the boost factor in the proposed structure is increased by changing both the shoot-through (ST) duty cycle and turns ratio of the transformer. The operating principle of the proposed converter in four operating modes is presented. We also calculate the critical inductance and compare the proposed converter with conventional topologies. In addition, power loss and THD analysis are presented. Finally, PSCAD/EMTDC software is used to verify the correct operation of the proposed inverter and the experimental results.

1. Introduction

The Z-source network is one of the important networks in power electronic converters. This network can be used in dc/dc, dc/ac, ac/dc, and ac/ac power conversion. Among the four mentioned types of power conversion, the utilization of the Z-source network in dc/ac power conversion gives significant benefits; hence, the Z-source inverter (ZSI) has been discussed in [1]. The conventional ZSI has an X-shaped impedance network and its Z-source network has two inductors, two capacitors, and one diode. A quasi-Z-source inverter (QZSI) with better features has been presented in [2]. Among these benefits, one can note the reduction in voltage stress and the reduction in input current ripple. In order to decrease the inrush current of the converter in startup, the improved ZSI (IZSI) has been presented in [3]. In [4], the cascaded arrangement of several Z-source networks with low voltage stress on capacitors led to multiple-series Z-source inverters. To increase the boost factor of the presented topology in [4], several networks are required, leading to high volume and high cost.

In some of the articles, Z-source converters have been categorized based on the type of Z-source network of the converter. In general, the impedance networks of the Z-source converters are categorized as conventional Z-source networks and switched Z-source networks [5]. The main difference between these two types of Z-source networks is the existence of a power switch in the switched Z-source converters. To reduce the number of passive elements, a switched boost inverter (SBI) has been presented in [6]. The impedance network of SBI has one inductor, one capacitor, two diodes, and a power switch, and its boost factor is lower than that of ZSI [1]. In order to improve the boost factor of SBI, a current-fed switched inverter (CFSI) has been proposed in [7]. CFSI has the same boost factor as ZSI [1] and a low input current ripple. A high boost factor has been achieved in [8] by using switched-inductor cells. Another topology for a switched Z-source inverter has been presented in [9], which has several passive and semiconductor elements. The reported topology in [9] has two inductors, two capacitors, four diodes, and one power switch in the impedance network. All proposed topologies in [1,2,3,4,5,6,7,8,9] can be used as a full-bridge inverter; however, the extension of the Z-source concept to a half-bridge inverter is possible. The half-bridge Z-source inverters feature the same operation as full-bridge inverters but with a two-times lower number of power switches than the full-bridge topology. In [10], a Z-source half-bridge converter with the aim of application in the electrochemical industry has been presented. In [11], a half-bridge Z-source inverter with two Z-source networks has been presented. This topology does not have a high boost factor in comparison with a conventional Z-source inverter but it features low voltage stress of the components. In [12], another topology for a half-bridge Z-source inverter has been presented, but it needs more Z-networks to achieve a high boost factor. The half-bridge switched boost inverter (HF-SBI) has been proposed in [13]. Steady-state analysis and small signal analysis of HF-SBI has been presented in [13]. With the same value of the input voltage and duty cycle, the boost factor of HF-SBI is higher than that of SBI [6] but the input current ripple of HF-SBI is still high. Two different switched half-bridge Z-source inverters have been presented in [14,15]. These topologies have a high boost factor in comparison with conventional topologies, but the use of power switches can lead to complexity in switching and modulation techniques.

Extension of half-bridge Z-source and switched Z-source inverters to a half-bridge transformer-based Z-source inverter is possible [16]. The transformer-based Z-source inverters can control the boost factor of the converter by two parameters, the shoot-through duty cycle and the turns ratio of the transformer [17,18]. A trans-Z-source neutral point clamped inverter has been presented in [19], which is composed of two impedance networks. A transformer based on the presented structures in [7,8] has been introduced in [20,21]. In [20], two types of trans-switched boost inverters have been presented with the same value of the boost factor. A variation of the presented structures in [20] has been proposed in [21]. The number of the elements in [20,21] is the same; however, in the presented structure in [21], a lower turns ratio is needed for increasing the voltage. Furthermore, the cascaded topologies for Z-source inverters based on the transformer and tapped inductors have been presented [22]. A half-bridge trans-Z-source inverter has been reported in [23]. The proposed concept features a continuous input current with a high voltage boost factor. However, comparing the counterparts, the number of components is greater and the converter features high voltage stress of the capacitors.

In this paper, a new embedded topology for the half-bridge Γ-Z-source inverter is proposed. Compared with the conventional Γ-Z-source full-bridge inverter, the input power source is connected in series with power switches instead of a series connection with diodes. The proposed concept features a high boost factor compared to the conventional Z-source inverters. Further, low capacitor voltage stresses and low switching voltage spikes are achieved with the proposed configuration. The paper is organized as follows.

In Section 2, the topology and operating principle of the proposed converter are presented. The design considerations of the magnetic components and capacitors are given in Section 3. In addition, the calculation of power losses and total harmonic distortion is provided in Section 4. A detailed comparison with the other related topologies is presented in Section 5. The power losses and efficiency are evaluated in Section 6. Section 7 validates the effectiveness of the proposed concept using simulation. The control scheme and dynamic of the proposed converter are studied in Section 8. Finally, experimental results are used to verify the correctness of the theoretical analysis in different operating modes.

2. Proposed Topology

The power circuit of the proposed topology is shown in Figure 1. The proposed topology has two transformers with a turns ratio of N₁₂ = N₁/N₂, diodes D₁ and D₂, and capacitors C₁ and C₂. Similar to the classic half-bridge inverter, the proposed half-bridge inverter has two voltage sources and two switches. In the proposed topology, the magnetizing inductances of the transformers are equal (L_m1 = L_m2 = L_m) and C₁ = C₂ = C. The values of voltage across primary windings in the upper and lower networks (v_p1 = v_p2 = v_p) are equal. Hence, the following summarization can be considered:

$$v_{p1}=v_{n1}=v_1$$

(1)

$$v_{p2}=v_{n2}=v_2$$

(2)

$$V_{C1}=V_{C2}=V_C$$

(3)

$$v_{D1}=v_{D2}=v_D$$

(4)

2.1. Operating Principle

The operating modes of the proposed inverter are specified by turning on and turning off the diodes and power switches. The number of operating modes in the proposed inverter is four. Figure 2 shows the equivalent circuit of the proposed converter in operation modes. In the first operating mode, both switches S₁ and S₂ are on; so, the proposed inverter is in shoot-through (ST) state. In the second operating mode, switch S₁ is on and switch S₂ is off; hence, the proposed inverter is in non-shoot-through state. In the third operating mode, similar to the first operating mode, both switches S₁ and S₂ are on; so, the proposed inverter is in ST state. In the fourth operating mode, switch S₁ is off and switch S₂ is on. It is important to note that, in the theoretical analysis, all of the elements are assumed to be ideal. More precisely, the following items are considered in the theoretical calculations:

• The series resistance and the voltage drop of the switches and the diodes are ignored;
• The series resistance and the capacitors and the inductors are ignored;
• The internal resistance of the input voltage is ignored;
• The switching method and the turning on and off of semiconductor elements are assumed to be ideal;
• The load of the proposed converter is pure ohmic with resistance R.

In the following, the operating principle and detailed analyses are given.

2.1.1. First Operating Mode

The ST state occurs in the first operating mode and both switches are on but both diodes are off. By applying Kirchhoff’s voltage law (KVL) in both the upper and lower networks, the following equations are obtained:

$$V_C+v_2-v_1+V_i-v_o$$

(5)

$$V_C+v_o+V_i-v_1+v_2=0$$

(6)

By using Equations (5) and (6), the average voltage across the capacitors and the output voltage are obtained as follows:

$$V_C=v_1-v_2-V_i=\left(1-\frac{N_2}{N_1}\right)v_1-V_i$$

(7)

$$v_o=0$$

(8)

In this operating mode, due to the positive value of the voltage across the magnetizing inductor $L_m$, the magnetizing current linearly increases from its minimum value (I_L,min) to its maximum value (I_L,max). By considering Equation (7), the magnetizing current is obtained as follows:

$$i_{Lm}=\frac{v_1}{L_m}t+I_{L,\min }=\frac{N_1\hspace{0.17em}(V_C+V_i)}{(N_1-N_2)L_m}t+I_{L,\min }$$

(9)

By considering $i_{p1}=i_{n1}=i_1$, $i_{p2}=i_{n2}=i_2$ and Kirchhoff’s current law (KCL), the following equation can be written:

$$i_2=i_1+i_{Lm}$$

(10)

Since i₂ = (N₁/N₂)i₁, the current through the capacitor C₁ is calculated as follows:

$$i_{C1}=-i_2=-\frac{N_1}{N_1-N_2}{i}_{Lm}$$

(11)

2.1.2. Second Operating Mode

In the second operating mode, switch S₁ is on, and switch S₂ is off. The diodes are on. By using KVL, the obtained equations are as follows:

$$V_C=-v_2=-\frac{N_2}{N_1}{v}_1$$

(12)

$$v_o=v_{o,\max }=V_i-v_1=V_i-\frac{N_1}{N_2}{v}_2$$

(13)

In this operating mode, due to the negative value of the voltage across the magnetizing inductor, the magnetizing current linearly decreases from its maximum value (I_L,max) to its minimum value (I_L,min). By using Equation (12), the magnetizing current is obtained as:

$$i_{Lm}=\frac{v_1}{L_m}t+I_{L,\max }=-\frac{N_1\hspace{0.17em}{V}_C}{N_2{L}_m}t+I_{L,\max }$$

(14)

By using KCL, the following equation is obtained as follows:

$$i_{p1}+i_{Lm}=\frac{v_{o,\max }}{R}$$

(15)

where R is the load resistance.

The current of capacitor C₁ is obtained by Equation (16):

$$i_{C1}=\frac{N_1}{N_2}\left(i_{Lm}-\frac{v_{o,\max }}{R}\right)$$

(16)

2.1.3. Third Operating Mode

In the third operating mode, both diodes are off, but both switches are on. Due to the similarity of the analysis in this operating mode to the first operating mode and to avoid prolongation, detailed analysis is omitted.

2.1.4. Fourth Operating Mode

In the fourth operating mode, switch S₁ is off, and switch S₂ is on. Both of the diodes are on. By using KVL, the following equation is obtained by Equation (17):

$$v_o=v_{o,\min }=-\hspace{0.17em}{v}_{o,\max }=v_1-V_i$$

(17)

The current through the capacitor C₁ is calculated as follows:

$$i_{C1}=-i_{p2}=-\frac{N_1}{N_2}{i}_{p1}=\frac{N_1}{N_2}{i}_{Lm}$$

(18)

Figure 3a shows a logical diagram and waveforms of the switching pattern. Figure 3b shows waveforms of the current and voltage in the proposed inverter.

2.2. Boost Factor

The average voltage across the magnetizing inductor in steady state is zero; hence, the following equation can be written:

$${\displaystyle \underset{0}{\overset{T_s}{\int }}{v}_1\hspace{0.17em}dt=0}$$

(19)

By using Equations (7), (12), and (19), the following equation is derived:

$$\frac{N_1\hspace{0.17em}(V_C+V_i)}{N_1-N_2}{D}_{ST}{T}_s-\frac{N_1\hspace{0.17em}{V}_C}{N_2}(1-D_{ST})\hspace{0.17em}{T}_s=0$$

(20)

where D_ST and T_S are the ST duty cycle and switching period, respectively.

From Equation (20), the average voltage across the capacitors is calculated as follows:

$$V_C=\frac{D_{ST}}{N_{12}(1-D_{ST})-1}{V}_i$$

(21)

where N₁₂ is equal to the ratio of N₁/N₂ and the range of the ST duty cycle is 0 ≤ D_ST < 1 − (1/N₁₂).

By using Equations (12), (13), and (21), the maximum output voltage is calculated as follows:

$$v_{o,\max }=\frac{N_{12}-1}{N_{12}(1-D_{ST})-1}{V}_i$$

(22)

Due to the definition of the boost factor for the proposed inverter as B = (v_o,max/V_i), the following equation for the boost factor is derived:

$$B=\frac{N_{12}-1}{N_{12}(1-D_{ST})-1}$$

(23)

3. Design Considerations

In steady state, the average value of the capacitor’s current is zero; hence, the following equation can be written:

$${\displaystyle \underset{0}{\overset{T_s}{\int }}{i}_C\hspace{0.17em}dt=0}$$

(24)

From Equations (11), (16), and (24), the following equation can be written:

$$-\frac{N_1}{N_1-N_2}{I}_{Lm}{D}_{ST}+\frac{N_1(1-D_{ST})}{2N_2}\left(2I_{Lm}-\frac{v_{o,\max }}{R}\right)=0$$

(25)

By solving Equation (25), the average current through the magnetizing inductors is obtained as follows:

$$I_{Lm}=\frac{(1-D_{ST})(N_1-N_2)}{2R(N_1-N_2-N_1{D}_{ST})}{v}_{o,\max }$$

(26)

By using Equations (22) and (26), I_Lm is calculated as follows:

$$I_{Lm}=\frac{(1-D_{ST}){(N_{12}-1)}^2}{2R{[N_{12}(1-D_{ST})-1]}^2}{V}_i$$

(27)

For a proper design, the ripple of magnetizing current should be calculated. By using of Equation (7), the following equation is written:

$$L_m\frac{\Delta i_{Lm}}{0.5D_{ST}{T}_s}=\frac{N_1}{N_1-N_2}(V_i+V_C)$$

(28)

where ∆i_Lm is the ripple of the magnetizing current.

By using Equations (21) and (28), ∆i_Lm is obtained as follows:

$$\Delta i_{Lm}=\frac{N_{12}{D}_{ST}(1-D_{ST})}{2L_m\hspace{0.17em}{f}_s[N_{12}(1-D_{ST})-1]}{V}_i$$

(29)

To calculate the voltage ripple across capacitors, ∆v_C, we use:

$$\Delta v_C=\frac{N_1}{N_{2}C}{\displaystyle \underset{0}{\overset{0.5(1-D_{ST})T_s}{\int }}\left(\frac{v_1}{L_m}t+I_{L,\max }\right)dt}$$

(30)

By solving Equation (30), ∆v_C can be written as follows:

$$\Delta v_C=\frac{N_{12}{(N_{12}-1)}^2{(1-D_{ST})}^2}{4RC{f}_s{[N_{12}(1-D_{ST})-1]}^2}{V}_i$$

(31)

By defining the percentage of permissible current ripple of the magnetizing inductance (x_Lm%) and the percentage of permissible voltage ripple for capacitors (x_C%), we have:

$$x_{Lm}\%=\frac{\Delta i_{Lm}}{I_{Lm}}\times 100$$

(32)

$$x_C\%=\frac{\Delta v_C}{V_C}\times 100$$

(33)

By using Equations (27), (29), and (32), x_Lm% is derived as follows:

$$x_{Lm}\%=\frac{N_{12}{D}_{ST}R[N_{12}(1-D_{ST})-1]}{L_m\hspace{0.17em}{f}_s{(N_{12}-1)}^2}\times 100$$

(34)

By using Equation (34), the value of the magnetizing inductors is obtained as follows:

$$L_m=\frac{N_{12}{D}_{ST}R[N_{12}(1-D_{ST})-1]}{x_{Lm}\%\hspace{0.17em}{f}_s{(N_{12}-1)}^2}\times 100$$

(35)

By considering Equations (21), (31), and (33), x_C% is derived as follows:

$$x_C\%=\frac{N_{12}{(N_{12}-1)}^2{(1-D_{ST})}^2}{4RC{f}_s{D}_{ST}[N_{12}(1-D_{ST})-1]}\times 100$$

(36)

Hence, the value of the capacitors can be written as follows:

$$C=\frac{N_{12}{(N_{12}-1)}^2{(1-D_{ST})}^2}{4R{f}_s{x}_C\%D_{ST}[N_{12}(1-D_{ST})-1]}\times 100$$

(37)

It is noticeable that the calculated inductance from Equation (35) should not lead to improper operating states. It should be mentioned that two operating states can occur in the proposed inverter. In the first operating state, the synchronous operation of diodes (SOD) leads to four operating modes, and D₁ and D₂ turn on and off simultaneously. Detailed analyses of these operating modes have been described in the previous sections. By selecting a small magnetizing inductance, SOD is disrupted. Asynchronous operation of diodes (AOD) in the second operating state leads to ann asymmetrical output voltage with more than four operating modes. To avoid AOD, the critical inductance (L_m,crit) should be lower than the magnetizing inductance. In the boundary condition between SOD and AOD, the current through diode D₁ at the second operating mode reaches zero. Hence, by using Equation (16), the following equation is derived:

$$i_{D1}=i_{C1}+i_o=\frac{N_1}{N_2}{i}_{Lm}-\frac{N_1\hspace{0.17em}{v}_{o,\max }}{N_2\hspace{0.17em}R}+\frac{v_{o,\max }}{R}=0$$

(38)

From Equations (14) and (38), the following equation for L_m,crit is calculated:

$$L_{m,crit}=\frac{R{N}_{12}^2[N_{12}(1-D_{ST})-1]D_{ST}(1-D_{ST})}{2\hspace{0.17em}{f}_s[2{(N_{12}-1)}^2-N_{12}{(N_{12}-1)}^2(1-D_{ST})]}$$

(39)

4. Power Loss and THD Calculation

4.1. Power Loss Calculation

In order to calculate the power loss of the proposed converter, the method that has been presented in [9,24] is used. At first, the power loss of the each element is calculated and then the total power loss is obtained from the sum of them.

The power losses in semiconductor elements are divided into conduction power loss and switching power loss. The voltage and current of the switch (S₁) for a period are obtained as follows:

$$v_{S1}=\{\begin{array}{cc}0& 0\le t\le 0.5D_{ST}{T}_s(1st mode)\\ 0& 0\le t\le 0.5(1-D_{ST}{T}_s)(2nd mode)\\ 0& 0\le t\le 0.5D_{ST}{T}_s(3rd mode)\\ 2\left|v_{o,\min }\right|& 0\le t\le 0.5(1-D_{ST}{T}_s)(4th mode)\end{array}$$

(40)

$$i_{S1}=\{\begin{array}{cc}\frac{N_1}{N_1-N_2}{I}_{Lm}& 0\le t\le 0.5D_{ST}{T}_s(1st mode)\\ \frac{N_1}{N_2}\left(\frac{v_{o,\max }}{R}-I_{Lm}\right)& 0\le t\le 0.5(1-D_{ST}{T}_s)(2nd mode)\\ \frac{N_1}{N_1-N_2}{I}_{Lm}& 0\le t\le 0.5D_{ST}{T}_s(3rd mode)\\ 0& 0\le t\le 0.5(1-D_{ST}{T}_s)(4th mode)\end{array}$$

(41)

According to Equation (41), the conduction power loss of the switch S₁ is calculated as follows:

$$\begin{array}{ll}{P}_{Cond,S1}& =\frac{D_{ST}{N}_1}{N_1-N_2}{I}_{Lm}\left(V_{F,S}+\frac{N_1}{N_1-N_2}{r}_S{I}_{Lm}\right)\\ & +\frac{0.5(1-D_{ST})N_1}{N_2}\left(\frac{v_{o,\max }}{R}-I_{Lm}\right)\left[V_{F,S}+r_s\frac{0.5N_1}{N_2}\left(\frac{v_{o,\max }}{R}-I_{Lm}\right)\right]\end{array}$$

(42)

where r_S and V_F,S are the series resistance and the voltage drop of the switch in conduction mode, respectively.

By considering Equations (40) and (41), the switching power loss of S₁ in t_on,S and t_off,S (turn-on and turn-off time) is calculated as follows:

$$P_{Sw}^{on,off}=\frac{N_1}{3(N_1-N_2)}{f}_{s}B{I}_{Lm}{V}_i(t_{on,S}+t_{off,S})$$

(43)

In order to calculate the power loss of the diodes, the voltage and current of the diode D₁ should be calculated for a period as follows:

$$v_{D1}=\{\begin{array}{cc}\frac{N_{12}{V}_C+V_i}{1-N_{12}}& 0\le t\le 0.5D_{ST}{T}_s(1st mode)\\ 0& 0\le t\le 0.5(1-D_{ST}{T}_s)(2nd mode)\\ \frac{N_{12}{V}_C+V_i}{1-N_{12}}& 0\le t\le 0.5D_{ST}{T}_s(3rd mode)\\ 0& 0\le t\le 0.5(1-D_{ST}{T}_s)(4th mode)\end{array}$$

(44)

$$i_{D1}=\{\begin{array}{cc}0& 0\le t\le 0.5D_{ST}{T}_s (1st mode)\\ \frac{N_1}{N_2}\left(I_{Lm}-\frac{v_{o,\max }}{R}\right)+\frac{v_{o,\max }}{R}& 0\le t\le 0.5(1-D_{ST}{T}_s) (2nd mode)\\ 0& 0\le t\le 0.5D_{ST}{T}_s (3rd mode)\\ \frac{N_1}{N_2}{I}_{Lm}& 0\le t\le 0.5(1-D_{ST}{T}_s) (4th mode)\end{array}$$

(45)

The conduction and switching loss of the diode D₁ are calculated from the below equations.

$$\begin{array}{ll}{P}_{Cond,D1}& =0.5(1-D_{ST})\left[\frac{N_1}{N_2}\left(I_{Lm}-\frac{v_{o,\max }}{R}\right)+\frac{v_{o,\max }}{R}\right]\left\{V_{F,D}+r_D\left[\frac{N_1}{N_2}\left(I_{Lm}-\frac{v_{o,\max }}{R}\right)+\frac{v_{o,\max }}{R}\right]\right\}\\ & +0.5(1-D_{ST})\left(\frac{N_1}{N_2}{I}_{Lm}\right)\left(V_{F,D}+r_D\frac{N_1}{N_2}{I}_{Lm}\right)\end{array}$$

(46)

$$P_{Sw,D1}^{off}=\frac{N_{12}{V}_C+V_i}{6(1-N_{12})}{f}_s\left[2N_{12}{I}_{Lm}+\frac{v_{o,\max }}{R}\left(1-N_{12}\right)\right]t_{off,D}$$

(47)

where r_D and V_F,D are the series resistance and the voltage drop of the diodes in conduction mode, respectively.

According to the symmetrical operation of the proposed converter, the power loss of the switch S₂ and the diode D₂ are the same as the power loss of S₁ and D₁, respectively.

The power loss of the capacitors is obtained as:

$$P_{rC}=\frac{1}{T_s}{\displaystyle {\int }_0^{T_s}{r}_C{i}_C{}^{2}dt}$$

(48)

where r_C is the internal series resistance capacitors.

By considering the value of $i_{C1}$ Equations (11), (16), and (18), the power loss of the capacitors is obtained as follows:

$$\begin{array}{ll}{P}_{C1}=P_{C2}& =r_{C1}\left[{\left(\frac{N_1}{N_1-N_2}{I}_{Lm}\right)}^2{D}_{ST}+{\left(0.5(1-D_{ST})\frac{N_1}{N_2}{I}_{Lm}\right)}^2\right]\\ & +0.5r_{C1}(1-D_{ST}){\left(\frac{N_1}{N_2}\left(I_{Lm}-\frac{v_{o,\max }}{R}\right)+\frac{v_{o,\max }}{R}\right)}^2\end{array}$$

(49)

The power loss of inductors is expressed by the core loss and conduction power loss. The core power loss is calculated as follows:

$$P_{CL}=0.33B^{1.98}{f}^{1.64}{V}_{eff}$$

(50)

where B is the flux density, f is the frequency in kHz, and V_eff is the effective core volume.

The conduction power loss of inductors is expressed by the values of resistance of inductors (r_L) and the RMS current of them as follows:

$$P_{rL1}=P_{rL2}=r_L{I}_{Lm}{}^2$$

(51)

4.2. THD Calculation

In order to obtain the relation of the total harmonic distortion (THD) for the proposed converter, the Fourier series of the output voltage should be considered as follows:

$$v_o={\displaystyle \sum _{m=1,\hspace{0.17em}3,\hspace{0.17em}5,\hspace{0.17em}\dots }^{\infty }{X}_m\sin (m\omega \hspace{0.17em}t)}$$

(52)

The value of Xm in Equation (52) is calculated from the below equation. It should be noted that because v_o is an odd function, the a_n Fourier coefficient is equal to zero.

$$\begin{array}{ll}{X}_m& =\frac{2}{T_s}{\displaystyle {\int }_0^{T_s}{v}_o}sin(m\omega t)d\omega t\\ & =\frac{2B{V}_i}{m\pi }\left[-cos(m\omega t)|\begin{array}{c}{}^{\pi -0.5\pi D_{ST}}\\ {}^{0.5\pi D_{ST}}\end{array}\right]\end{array}$$

(53)

By simplifying the above equation, the following equation is obtained:

$$X_m=\frac{4B{V}_i}{m\pi }cos(0.5m\pi D_{ST})$$

(54)

The RMS value of the output voltage is calculated from the following equation:

$$V_{o,rms}=\sqrt{1-D_{ST}}B{V}_i$$

(55)

Considering Equations (54) and (55), the value of THD is calculated as follows:

$$\begin{array}{ll}THD& =\frac{\sqrt{V_{o,rms}{}^2-X_{1,rms}{}^2}}{X_{1,rms}}\\ & =\frac{\sqrt{2V_{o,rms}{}^2-X_1{}^2}}{X_1}\end{array}$$

(56)

By simplifying the above equation, the value of THD is as follows:

$$THD=\frac{\sqrt{2{\pi }^2(1-D_{ST})-{\left[4cos(0.5\pi D_{ST})\right]}^2}}{4cos(0.5\pi D_{ST})}$$

(57)

5. Comparison

In this section, the proposed converter is compared with the literature regarding the different parameters, such as the boost factor and voltage stress on capacitors.

Table 1. Comparison of the parameters of the proposed and conventional structures.

Structures	Boost Factor	Maximum Voltage Stressacross of Capacitors
Proposed	$\frac{N_{12}-1}{N_{12}(1-D_{ST})-1}$	$\frac{D_{ST}B{V}_i}{N_{12}-1}$
ZSI [1]	$\frac{1}{1-2D_{ST}}$	$(1-D_{ST})B{V}_i$
QZSI [2]	$\frac{1}{1-2D_{ST}}$	$(1-D_{ST})B{V}_i$
IZSI [3]	$\frac{1}{1-2D_{ST}}$	$(1-D_{ST})B{V}_i$
Multiple SZSI [4]	$\frac{1}{1-(N+1)D_{ST}}$	$D_{ST}B{V}_i$
SBI [6]	$\frac{1-D_{ST}}{1-2D_{ST}}$	$B{V}_i$
CFSI [7]	$\frac{1}{1-2D_{ST}}$	$B{V}_i$
Switched inductor ESBI [8]	$\frac{1+D_{ST}}{1-3D_{ST}}$	$B{V}_i$
DA-SZSI [9]	$\frac{1}{1-3D_{ST}+D_{ST}}$	$B{V}_i$
Half-bridge ZSI [10]	$\frac{1}{1-2D_{ST}}$	$2B{V}_i$
Half-bridge SZSI [11]	$\frac{1}{1-(N+1)D_{ST}}$	$D_{ST}B{V}_i$
Low-stress half-bridge ZSI [12]	$\frac{1-(N-1)D_{ST}}{1-(N+1)D_{ST}}$	$\frac{2D_{ST}B{V}_i}{1-(N-1)D_{ST}}$
Half-bridge SBI [13]	$\frac{1-D_{ST}}{1-3D_{ST}}$	$B{V}_i$
Half-bridge qSBI [14]	$\frac{1-D_{ST}}{1-3D_{ST}}$	$\frac{2D_{ST}B{V}_i}{1-D_{ST}}$
Diode-assisted half-bridge ZSI [15]	$\frac{1}{1-3D_{ST}}$	$B{V}_i$
Trans ZSI [17]	$\frac{1}{1-(N+1)D_{ST}}$	$N{D}_{ST}B{V}_i$
Trans SBI [19]	$\frac{1+N{D}_{ST}}{1-(N+2)D_{ST}}$	$B{V}_i$

shows the relation among the boost factor and the maximum voltage stress across the capacitors in the proposed and the conventional structures.

5.1. Comparison of Boost Factor

The boost factor of the proposed converter depends on two factors. The first factor is the value of the ST duty cycle, and the second factor is the turns ratio of the used transformer. Figure 4a shows the boost factor of the proposed converter for different values of N₁₂. As can be appreciated from Figure 4a, the boost factor increases by increasing the turns ratio of the transformers. In Figure 4b, the boost factor of the proposed converter with N₁₂ = 5/4 is compared with [4,7]. Figure 4c,d show the variation in the boost factor for N₁₂ = 4/3 and N₁₂ = 3/2 with the presented topologies in [1,2,3,5,6,8,9,10,11,12,13,14]. As can be appreciated from Figure 4c, the proposed converter features a high boost factor. For the proposed converter, a boost factor of 10 could be achieved for an ST duty cycle around 0.2, but for the proposed converter in [13,14], it is achievable at an ST duty cycle around 0.3. It is worth mentioning that, for the same condition, the boost factor of the proposed converter could be increased by increasing the turn ratio of the transformers.

5.2. Comparison of Voltage Stress on Capacitors

The voltage stress of the capacitors is one of the parameters that could be considered for the benchmarking of the converters. This value for the proposed converter is lower than some conventional inverters for low values of the ST duty cycle. According to Equation (21), the voltage stress in D_ST = 0 is close to zero, which results in soft-start capability [25]. Figure 5a shows the normalized value of the voltage stress of the capacitors for different values of N₁₂. The voltage stress of the capacitors for the proposed and conventional inverters is compared in Figure 5b. As can be seen for the turns ratio of N₁₂ = 2, the voltage stress of the capacitors is the lowest for the proposed converter. For the turns ratio of 3/2, it is the lowest for ST duty cycles lower than 0.25, and it increases by increasing the D_ST.

5.3. Comparison of the Number of Used Elements

Comparison of the number of used elements is one of the most important tasks when comparing topologies. In

Table 2. Comparison of the number of the elements for the proposed and conventional structures.

Structures	Number of Elements
	Transformer.	L	C	D	S
Proposed	2	-	2	2	2
ZSI [1]	-	2	2	1	4
QZSI [2]	-	2	2	1	4
IZSI [3]	-	2	2	1	4
Multiple SZSI [4]	-	N + 1	2N	N	4
SBI [6]	-	1	1	2	5
CFSI [7]	-	1	1	2	5
Switched inductor ESBI [8]	-	N	1	3N − 1	5
DA-SZSI [9]	-	2	2	4	5
Half-bridge ZSI [10]	-	2	2	1	2
Half-bridge SZSI [11]	-	2N + 2	4N	2N + 2	2
Low-stress half-bridge ZSI [12]	-	N + 1	2N	N + 2	2
Half-bridge SBI [13]	-	2	2	4	4
Half-bridge qSBI [14]	-	2	2	4	4
Diode-assisted half-bridge ZSI [15]	-	1	2	4	4
Trans ZSI [17]	1	-	1	1	4
Trans SBI [19]	1	-	1	2	5

, the number of elements in the proposed and conventional inverters is shown. According to Table 2, the proposed topology, similar to conventional Z-source inverters [1,2,3], has two capacitors in the power circuit, but the number of used transformers is double in comparison with Trans ZSI [17]. Of course, the proposed inverter has fewer switches due to the half-bridge structure of the output stage.

5.4. THD Comparison

The THD factor is one of the most important parameters for the evaluation of impedance source inverters. For the proposed converter, THD could be defined by Equation (57).

Table 3. Comparison of THD in the proposed and conventional structures.

Proposed Half-Bridge Inverter							[13]		[15]
${\mathit{D}}_{\mathit{S}\mathit{T}}$	${\mathit{N}}_{12}=2$		${\mathit{N}}_{12}=\frac{3}{2}$		${\mathit{N}}_{12}=\frac{4}{3}$
	B	THD%	B	THD%	B	THD%	B	THD%	B	THD%
0	1	40.89	1	41.19	1	41.19	1	40.33	1	41.71
0.05	1.11	38.92	1.18	39.34	1.25	39.34	1.12	40.17	1.18	37.9
0.1	1.25	33.3	1.43	33.78	1.67	33.78	1.29	34	1.43	33.79
0.15	1.43	26.98	1.82	27.05	2.5	27.04	1.55	27.39	1.82	27.22
0.2	1.67	21.92	2.5	21.97	5	21.89	2	22.45	2.5	23.61
0.25	2	21.14	4	21.15	-----	-----	3	23.63	4	-----
0.3	2.5	22.4	10	22.5	-----	-----	7	28.75	10	-----
0.4	5	28.39	-----	-----	-----	-----	-----	-----	-----	-----

compares the estimated THD for the proposed converter and two other structures for different values of the ST duty cycle. The switching control method is the same for all of the structures. For all the converters, THD is the maximum for D_ST = 0 as the converters do not have zero values at the output. By increasing the ST duty cycle, the THD is decreased as the zero state is produced for the output voltage. The trend demonstrates that by increasing the ST duty cycle from 0 to 0.2 for all the converters, THD is decreased. The THD is improved by around 47% by increasing the ST duty cycle from 0 to 0.2. Comparing the THD for the proposed converter and reported converters in [13,15], it is the lowest for the proposed converter and the highest for the converter presented in [13]. According to this table, it can be seen that changing the value of the turns ratio of the transformer does not have a significant effect on the value of THD.

6. Power Losses and Efficiency Evaluation

Based on the given methodology in Section 4, the power losses of the proposed converter are analyzed. Figure 6 shows the power loss distribution of the proposed converter. The estimation was carried out at the input power of 400 W for the given values in

Table 4. Selected values of parameters.

Parameter	Symbol	Value
Input voltage	Vi	48 V
Switching frequency	fS	10 kHZ
Load resistance	R	100 Ω
Turns ratio	N12	4/3
Magnetizing inductance	Lm	2.5 mH
Capacitors	C	100 µF
Shoot-through duty cycle	DST	0.2
Switches	S1, S2	Cree C3M0120100K
Diodes	D1, D2	Vishay VS-10ETS12THM3
Equivalent resistance	rL	395 mΩ
ESR of capacitors	rC	6 mΩ
Drain-source on-state resistance	RDS	141 mΩ
Rise time	ton	15 ns
Fall time	toff	8 ns
Forward voltage drop	VF,D	1.1 V
Forward resistance	rD	20 mΩ

. As can be appreciated from Figure 6, the power losses of the semiconductors dominate over the power losses of the inductors and capacitors. Around 32% of the power losses are switching losses, and 37% of the dissipated power is for conduction losses in the switches. As can be seen, the switching losses are lower than the conduction losses of the switches. As the proposed converter operates at a low switching frequency, the switching losses are low compared with the conduction losses. The diodes feature a power loss that is lower than the total power losses of the switches. Most of the power losses for diodes are conduction losses, as the used diodes are Schottky barrier diodes; the conduction losses dominate over the turn-off losses of the diodes. Based on the estimated power losses, the efficiency of the proposed converter is 90.35%.

Figure 7 shows the comparison of the estimated efficiency for the proposed converter and the reported converters in [11,16,26]. As can be appreciated from Figure 7, the proposed converter features the highest efficiency. The number of components is same for the proposed converter and [16]. However, the proposed configuration features a low voltage stress in the capacitors and switches that results in high efficiency. The proposed converters in [11,26] feature a higher number of components than the proposed converter and [16]; due to this and the high RMS current of the switches, the efficiency is low for [11,26], with a difference of around 2.5% at the full-load condition. The difference for the part- and full-load conditions is higher than that for the light-load condition, as, for the full-load condition, the conduction losses dominate the switching losses. The efficiency for the proposed converter in [26] is the lowest as the number of components, especially semiconductors, is the highest.

7. Simulation Results

In this section, the given theoretical analysis and operation of the proposed converter are verified using PSCAD/EMTDC software. Selected values of parameters are reported in Table 4. It is noticeable that the selected value for magnetizing inductance is higher than the critical inductance, with a value of 914 µH, which is calculated from equation (39). On the other hand, x_Lm% and x_C% are lower than 70% and 2%, respectively.

Figure 8a shows waveforms of the current through diodes D₁ and D₂. According to this figure, the current through diodes in the ST state is zero, which is in line with Figure 3b. Figure 8b shows the primary side current, which verifies theoretical concepts. Figure 8c shows the voltage and current of the primary magnetizing inductor. As can be observed from Figure 8c, the voltages in ST and non-ST states are 762.01 V and −190.98 V, which are close to values of 768 V and −192 V calculated from (12) and (17), respectively. The simulated average value and ripple of the magnetizing current are 4.76 A and 3.18 A, which differ slightly from the values of 4.80 A and 3.07 A calculated from (27) and (29). Figure 8d shows the waveform of the capacitors’ current. These waveforms have a 180° phase degree with each other, which is in agreement with theory. Figure 9 shows the voltage across capacitors and the output voltage. According to Figure 9a, voltage ripple and average voltage values across capacitors are 2.57 V and 142.12 V, respectively. The estimated value from Equations (31) and (21) equals 2.56 V and 144 V, indicating minor differences between simulated and estimated values. According to Figure 9b, the output voltage has negative, positive, and zero levels. The maximum value of the output voltage is 237.82 V, which is in line with the value of 240 V calculated from (22). In general, the simulation results are in good agreement with the theoretical results.

Figure 10 shows the simulation results of the proposed converter during the transient state. Figure 9a shows the voltage across capacitor C₁. As can be seen, the voltage across the capacitor reaches a steady state after 0.04 s. Figure 9b shows the output voltage waveform at the startup moment. According to this figure, the proposed inverter has stable operation, and the dynamic response is appropriate.

8. Control Scheme and Dynamic Performance

Figure 10 shows the schematic of the control strategy for the proposed converter. The Pulse Width Modulation (PWM) method is used to control the switches. In order to control the maximum value of the output voltage, a PI controller is used. The maximum value of the output voltage of the proposed converter is compared with the desired value of the output voltage (V_{o,max_ref}), and if there is a difference, it is applied to the controller to produce a desirable duty ratio. The desirable duty ratio is compared with a carrier wave, and then suitable interpolated pulses are produced to the switches. The PI controller has a gain and time constant this parameters are defined by a trade-off. In order to show the stable performance of the proposed converter, the simulated dynamic response of the output voltage for a step change in the input voltage is shown in Figure 11. As can be appreciated from Figure 11, by applying a step change in the input voltage, the converter shows stable performance. By increasing the input voltage when the converter operates in steady state, the feedback control system changes the ST duty cycle to fix the operating point at the constant output voltage, with a maximum value of 240 V when the ST duty cycle is decreased. After a short operation at an input voltage of 58 V, the voltage is step changed to 48 V and the closed-loop control system operates as the maximum value of the output voltage is fixed at 240 V by increasing the duty cycle. The stable operation of the proposed converter could be confirmed by carrying out the step change process.

9. Experimental Verification

In this section, experimental results are provided to verify the validity of the theoretical analysis and simulation results. A 400 W prototype (Figure 12) was assembled based on the main schematics of the proposed converter shown in Figure 1. The main specifications and types of semiconductor components used in the prototype are listed in Table 4. The converter was tested at the input voltage of 48 V, which was provided by the power supply EA PSI9080-60. The maximum value of output voltage was regulated to 240 V. The converter was controlled by the microcontroller STM32F334R8T6, utilizing a Cortex-M4 core. The driver circuit consisted of an ACPL-K342 BROADCOM optocoupler and dc-dc converter PEM1-S12-D15-S. The power conversion efficiency was measured with the help of a precision power analyzer, Yokogawa WT1800. Figure 13a shows waveforms of the current through diodes D₁ and D₂. According to this figure, the current through diodes in the ST state is zero, in agreement with Figure 3b. Figure 13b shows the primary side current of the transformers, which verifies theoretical concepts. Figure 13c shows the waveform of the current through capacitors C₁ and C₂, respectively. These waveforms have a 180° phase degree with each other, which is in agreement with theory. Figure 14a shows the voltage of the primary magnetizing inductor. According to this figure, voltages in ST and non-ST states are 750 V and −190 V, close to the values of 768 V and −192 V estimated by (17) and (12), respectively. The measured waveform of the voltage across the capacitor and the output voltage is shown in Figure 14b,c. As can be appreciated from Figure 14b, the average value of the voltage across the capacitor is close to 137 V. The difference between 144 V calculated from (21) with the measured values is insignificant. According to Figure 14c, the output voltage has negative, positive, and zero levels. The maximum value of the output voltage is close to 231 V, which agrees with the value of 240 V calculated from (22). In general, the experimental results are in good agreement with the theoretical results.

Figure 15 shows the heat distribution of the prototype under the input power of 400 W. The photo was recorded with a Fluke thermal camera. As can be appreciated from Figure 15, the hottest points are the semiconductors. The average temperature for the switches is 47 °C, and it is 40 °C for the diodes. This shows that the majority of the dissipated power belongs to the semiconductors. This could be predicted from the power loss analysis described in Section 6, as the power losses of the semiconductors dominate over the power losses of the magnetics and capacitors.

Figure 16 shows the comparison of the measured and estimated efficiency for the proposed converter and the reported structures in [11,16]. As can be seen, the proposed converter has the highest efficiency at the input power of 100 W and the lowest at the full-load condition. For a constant value of output voltage, the RMS current increases by increasing the input power, which results in high conduction losses and a reduction in the efficiency by around 3.5%. Comparing the measured efficiency to the estimated results, the measured efficiency follows the same trend as the estimated efficiency. The deviations between the estimated and experimental results are caused by thermal effects, which are not considered in the model: the diodes increase their resistance with temperature (0.38% per Kelvin); the on-state drain-source resistance changes with temperature (0.44% per Kelvin); the tolerance margin of datasheet parameters also has an effect (for example, 33% difference between typical and maximum on-state drain-source resistance). Figure 16b shows the comparison of the measured efficiency between the proposed concept and reported structures in [11,16]. As can be appreciated from Figure 16b, the efficiency is the highest for the proposed converter and the lowest for [11] when comparing the number of components; moreover, for the same boost factor, the RMS current of the proposed converter in [11] is higher than that of for the proposed converter, which results in a 1.38% drop in efficiency. The difference in the measured efficiency of the proposed converter and the converter presented in [16] is less as the two structures have the same number of components and the same boost factor. However, the voltage stress of the capacitors and switches is the lowest for the proposed converter. Regarding the measured waveforms, at the full-load condition, the voltage stress of the capacitors is 150 V for the proposed converter and 198 V for the proposed structure in [16]. This demonstrates an improvement of around 25%, with almost better efficiency for the proposed converter.

10. Conclusions

In this paper, an embedded topology for a half-bridge gamma-based Z-source inverter was proposed. The steady-state analysis of the proposed inverter at different operating modes was performed and design considerations have been given. The proposed converter features low voltage stress across the capacitors. In comparison with a conventional gamma-source half-bridge converter, the proposed converter improves the voltage stress of the capacitors by around 25%. The proposed half-bridge inverter could generate high voltage gain in comparison with half-bridge and full-bridge conventional Z-source inverters. Moreover, for the same boost factor, the proposed converter features a lower number of power switches than a conventional full bridge ZSI, which results in low switching losses. The estimated THD for an ST duty cycle of 0.2 equals 21.89%, which could be considered acceptable as the proposed converter features a higher boost factor than the conventional ZSI. The power loss analysis shows that the power switches dissipate the power more successfully than the other components, as around 70% of the power losses belong to the switches. Simulation results and experimental results were used to verify the given theoretical analysis. Based on the mentioned features, the proposed approach could be adopted for a full-bridge inverter. The proposed converter could be used as a grid-tied inverter to interface the dc sources to the grid; for this, it is necessary to design an output filter to filter the 50 or 60 Hz waveforms. Another application could be a front-end inverter for isolated dc-dc converters. The proposed concept can provide a boosted voltage to an isolated transformer operated at a high frequency. Depending on the boost factor of the converter, the transformer could be a step-up transformer or simply an isolated transformer.