Design and Implementation of Improved High Step-Down DC-DC Converter for Electric Vehicles

Abstract

An improved high step-down DC-DC converter for charging the batteries in an electric vehicle application is proposed in this paper. It adopts the topology of the conventional full-bridge converter, which has a coupled inductor current-doubler rectifier as the secondary side of the transformer. In addition, four power switches are driven using a phase-shifting technique. The proposed converter can achieve a high step-down voltage with low-voltage stress on the rectifier diodes. In addition, the coupled inductor current-doubler rectifier of the secondary side can reduce the ripple current and losses of the secondary side to achieve high efficiency. Furthermore, the proposed converter can overcome the drawbacks of the conventional full-bridge converter, such as switching loss caused by high switching frequency, duty-cycle loss, voltage stress, and numerous components, and can increase the efficiency with the soft-switching technique. A 600 W laboratory prototype of the proposed converter was manufactured. The results of the experiments performed with the prototype proved the effectiveness and validated the use of the proposed converter for better charging of electric vehicles.

1. Introduction

While the first and second industrial revolutions resulted in the improvement of mechanical and electrical technologies, the third industrial revolution has brought about the use of various electronic devices in people’s everyday lives.

Various types of electronic devices have been developed over the years, based on improvements such as miniaturization and high efficiency, and the operating voltage of devices has been gradually decreasing; notably, the operating voltage of microprocessors has decreased from 5 V to 3.3 V. In some cases, operating voltage has dropped below 1 V, but current has gradually increased, and is expected to exceed 100 A in the future. Therefore, a point-of-load DC-DC converter with independent voltage distribution uses 5 V or 12 V as the main input voltage to reduce distribution loss. Based on these tendencies, an isolated DC-DC converter with high output current, high step-down voltage ratio, and high efficiency is usually required, as shown in the shaded area of Figure 1 [1].

In addition, global warming and the depletion of natural resources have become global issues in recent decades, resulting in the need to regulate carbon dioxide emissions; accordingly, various eco-friendly vehicles such as hybrid electric vehicles (HEV), plug-in HEVs (PHEV), mild HEVs (MHEV), and battery electric vehicles (BEV) have been developed. These vehicles, except for MHEV, necessarily require a rechargeable battery system as a power source for the electric traction system [2,3].

With the continued development of these systems, the importance of batteries in various electrical vehicles (xEVs) is increasing steadily. Among them, HEVs and PHEVs typically require a high-voltage battery to be charged from a public line via the AC–DC converter to drive the vehicle’s electric motor; in addition, most of the vehicle’s electronic equipment requires a low-voltage battery to be charged. In order to meet the requirements of low ripple current and high efficiency, a high-voltage battery, named as the battery charger, requires an AC-DC converter with a power factor corrector (PFC) circuit and an isolated DC-DC converter; this system is called an on-board charger (OBC) [4,5,6,7,8,9].

In addition, the low-voltage battery is charged from the high-voltage battery through a low-voltage DC-DC converter (LDC) to drive most of the vehicle‘s electronic equipment, such as lights, wipers, and audio [10,11]. The overall electric traction system of HEV and PHEV is shown in Figure 2.

Research into improving the efficiency and durability of the OBC and LDC has been actively conducted, and improvements in system weight, volume, and cost have been emphasized [12]. Moreover, the capacity of the OBC and LDC in HEVs and PHEVs is increasing in proportion to the capacities of high-voltage and low-voltage batteries. High power density and high efficiency are most essential to this system. In particular, a high switching frequency is required to achieve the high power density of the LDC, and the elements and circuit design should be selected appropriately to achieve high efficiency and reduce loss [13,14,15].

The LDC has two important roles in charging the low-voltage battery (auxiliary battery). First, the low-voltage battery, charged from the high-voltage battery and LDC, supplies a low voltage of 12 V to the electric field system of the EVs. Second, the LDC supplies high voltage during the initial operating phase of the EVs [10,16]. Therefore, the LDC is the most essential component in the power train of the EVs to charge the low-voltage battery, and various topologies have been developed based on it. A phase-shift full-bridge (PSFB) converter is a commonly used topology for low output voltage, high output current, and high efficiency, and it has been widely researched for medium- or high-power applications requiring isolation [17,18,19]. The PSFB has a very simple structure and can perform a zero-voltage-switching (ZVS) operation with constant frequency pulse-width modulation (PWM), and without auxiliary components or complex control circuit. Nevertheless, it has limitations such as a high step-down voltage conversion, which necessitates a low duty ratio of the power switch or high turns ratio of the transformer. High turns ratio will increase the voltage stress of components such as the power switch [20]. In addition, the large external resonant inductor induces a very large circulating current, which flows through the primary winding of the transformer and the power switch during the reflux period. Therefore, the conduction loss of the power switch and copper loss of the transformer are of serious concern; in addition, reverse recovery losses occur. Several researchers have attempted to overcome these problems of the conventional PSFB converter [19,21,22,23,24,25,26,27]. In addition to the numerous studies on improvement of the primary side circuit, various secondary-side circuits for rectification have been considered in recent years; the secondary-side rectification circuits were introduced in [28,29,30,31]. Many researchers have adopted various techniques such as the conventional bridge rectifier, the center-tapped rectifier, and the current-doubler rectifier (CDR) as secondary rectification methods for the PSFB. The CDR method has proven suitable as a secondary side rectification method for a high-output-current application in many studies [32,33].

In this paper, a PSFB with a coupled inductor current-doubler rectifier (CICDR) is proposed as an LDC for EVs. The circuit design is illustrated in Figure 3. The proposed rectification method is the same as in the conventional CDR method, but the turns ratio of the coupled inductor can be adjusted to expand the range of the duty ratio, thereby reducing the current stress of the transformer and power switch and the output current ripple. Further, the voltage stress of the rectification diode can be reduced even in high-frequency operations and, consequently, the reverse recovery loss can be reduced.

Section 2 describes and proves the operating principle of the proposed converter. Section 3 describes the steady-state operation analysis and characteristics of the proposed converter.

The design considerations of the proposed converter are presented in Section 4, and Section 5 describes the experimental results obtained with a 600 W laboratory prototype of the proposed converter to verify its feasibility. Finally, the conclusion is presented in Section 6.

2. Derivation and Operating Principles of the Proposed Converter

2.1. Circuit Derivation

The derivation of the CDR method is based on the conventional voltage-doubler rectifier circuit shown in Figure 4a. Based on the concept of duality, nodes are used in place of the meshes of the voltage-doubler and inductors replace conductors; a current-doubler rectifier is formed with no change in diodes, as depicted in Figure 4b. Based on the secondary rectification method presented above, this paper proposes the CICDR method for the secondary side; the electrical schematic diagram is shown in Figure 4c. Figure 5 presents the winding arrangement of the CICDR. The two freewheeling diodes and the output capacitor C_o are the same as in the conventional CDR, but the output filter inductor combines two filter inductors and the winding is located on the outer leg of the E-Type single core. Finally, the coupled inductor functions as a transformer, and the currents i_Lo1 and i_Lo2 generate magnetic flux in the winding direction, which is added to the center leg. The turns ratio of the two windings is assumed as one. The electrical characteristics are presented in Figure 6.

2.2. Analysis of Operating States of Modes

To analyze the operation of the proposed converter, the following assumptions are made:

• The switching devices are ideal MOSFETs except for the internal body diodes and parasitic capacitors.
• The transformer ideally operates according to the turns on the primary and secondary sides, i.e., N_p and N_s, respectively.
• The output filter inductors have the same magnitude, i.e., L₁ = L₂, and the output current ripples are the same, i.e., $\Delta i_{L1}=\Delta i_{L2}$.
• The output filter capacitor C_o is large enough to be treated as a voltage source with output voltage V_o.

Figure 7 shows the key waveforms of the proposed converter. $v_p, v_s$ denotes the voltage across the resonant inductor and the primary winding of the transformer and the voltage of the secondary side of the transformer, respectively, and $i_p$ denotes the primary side current of the transformer. $i_{L1}$ and $i_{L2}$ denote the currents of the coupled inductor, $D_{eff}$ and $D_{loss}$ denote the effective duty cycle and duty cycle loss, respectively, and $i_o$ denotes the output current. From Figure 7, the proposed converter has six modes during a half cycle, and the other half cycle has symmetrical operation. Figure 8 shows the equivalent circuits for twelve operation modes. Additionally, the other symbols stated in all equations are as follows:

• $v_i$—Input voltage
• v_o—Output voltage
• $v_{C1}, v_{C2}, v_{C3}, v_{C4}$—voltage of the switch capacitor
• $i_i$—Input current
• $i_o$—Output current
• $n$—Turns ratio of the transformer
• $L_k$—Leakage inductance of the transformer
• $C_{oss}$—Output capacitance of the switch
• $f_s$—Switching frequency

Mode 1 [$t_0\le t<t_1$]: Figure 8a shows the equivalent circuit of this mode. In this mode, switches S₁ and S₄ are turned on, and transformer primary side voltage $v_p$ equals input voltage $v_i$. The input energy is transferred to the secondary side through switches S₁, S₄, and the transformer. The energy from the primary side is transferred to the output through filter inductor L₁, filter capacitor C_o, and diode D₂. Thus, inductor current $i_{L1}$ increases. In this mode, inductor current $i_{L2}$ has to flow through filter inductor L₂ and filter capacitor C_o; therefore, diode D₁ is turned off. This mode ends when switch S₄ is turned off. The primary voltage, output current, and filter inductor currents are expressed as follows.

$$v_p=v_i,$$

(1)

$$i_o\left(t\right)=i_{L1}\left(t\right)+i_{L2}\left(t\right),$$

(2)

$$i_{L1}\left(t\right)=\frac{n{v}_i-v_o}{L_1}\left(t-t_0\right)+i_{L1}\left(t_0\right),$$

(3)

$$i_{L2}\left(t\right)=\frac{-v_o}{L_2}\left(\mathrm{t}-t_o\right)+i_{L2}\left(t_o\right).$$

(4)

Mode 2 [$t_1\le t<t_2$]: Figure 8b shows the equivalent circuit of this mode, where $C_{eq}=C_3+C_4=2C_{oss}, \left(C_{oss}=C_1=C_2=C_3=C_4\right)$. At time $t=t_1$, switch S₄ is turned off, capacitor C₄ for switch S₄ is charged from 0 V to $v_i$, and capacitor C₃ for switch S₃ is discharged from $v_i$ to 0 V. Capacitor voltage $v_{C4}$ for capacitor C₄ increases linearly because the capacitances for switches S₃ and S₄ are very small. Capacitor voltages $v_{C3}, v_{C4}$ are given as follows.

$$v_{C3}\left(t\right)=\frac{-n{i}_{L1}\left(t_1\right)}{2C_{oss}}\left(t-t_1\right)+v_i,$$

(5)

$$v_{C4}\left(t\right)=\frac{n{i}_{L1}\left(t_1\right)}{2C_{oss}}\left(t-t_1\right).$$

(6)

At time $t=t_2$, the capacitor voltage $v_{C4}$ is equal to input voltage $v_i$. The transformer primary side voltage and current, secondary side voltage and current, and output current are expressed as follows.

$$v_p\left(t\right)=v_i-v_{c4}\left(t\right),$$

(7)

$$i_p\left(t\right)=n{i}_{L1}\left(t\right),$$

(8)

$$i_o\left(t\right)=i_{L1}\left(t\right)+i_{L2}\left(t\right),$$

(9)

$$i_{L1}\left(t\right)=\frac{n{v}_i-v_o}{L_1}\left(t-t_1\right)+i_{L1}\left(t_1\right),$$

(10)

$$i_{L2}\left(t\right)=\frac{-v_o}{L_2}\left(t-t_1\right)+i_{L2}\left(t_1\right).$$

(11)

The time interval from $t_1$ to $t_2$ is given as

$$\Delta t_{12}=\frac{v_i}{n{i}_{L1}\left(t_1\right)}\times 2C_{oss}.$$

(12)

The time interval $\Delta t_{12}$ is very small, and the primary side current of the transformer is nearly constant because the voltage associated with the leakage inductance converges to zero.

$$v_{L_k}=L_k\times \frac{d\left(n{i}_{L1}\right)}{dt}\approx 0.$$

(13)

Mode 3 [$t_2\le t<t_3$]: Figure 8c shows the equivalent circuit of this mode. At time $t=t_2$, capacitor C₃ is discharged to zero voltage when switch S₃ is turned on. Therefore, switch S₃ is turned on under the ZVS condition. In this mode, a delay time $t_d$ is necessary between the turning off of switch S₄ and the turning on of switch S₃, and it has to be longer than time interval $\Delta t_{12}$. The required delay time is given as

$$t_d=\frac{v_i\times 4C_{oss}}{n{i}_{L1}\left(t_1\right)}.$$

(14)

In this mode, the transformer’s primary and secondary side voltages of the transformer equal 0 V, i.e., $v_p=v_{s,drop}=0\mathrm{V}, v_s=0\mathrm{V}$, where ($v_{s,drop}$= forward voltage drop of the power switch).

Both diodes D₁ and D₂ are turned on. The primary side current and secondary side current of the transformer are expressed as follows.

$$i_p\left(t\right)=\left[\frac{v_{s,drop}}{r}+i_p\left(t_2\right)\right]e^{-\frac{r}{L_k}\left(t-t_2\right)}-\frac{v_{s,drop}}{r},$$

(15)

$$i_{L1}\left(t\right)=-\frac{v_o}{L_1}\left(t-t_2\right)+i_{L1}\left(t_2\right),$$

(16)

$$i_{L2}\left(t\right)=-\frac{v_o}{L_2}\left(t-t_2\right)+i_{L2}\left(t_2\right),$$

(17)

where $r$ is the equivalent series resistor for the leakage inductor $L_k$. This mode is ended when switch S₁ is turned off.

Mode 4 [$t_3\le t<t_4$]: Figure 8d shows the equivalent circuit of this mode. At time $t=t_3$, switch S₁ is turned off because the energy stored in the leakage inductor is discharged through capacitor C₁ of switch S₁. Thus, capacitor C₁ is charged from 0 V to $v_i$ and capacitor C₂ is discharged from $v_i$ to 0 V. The capacitor voltages $v_{C1}, v_{C2}$ are expressed as follows.

$$v_{C1}\left(t\right)=\frac{i_p\left(t_3\right)}{2C_{oss}}\left(t-t_3\right),$$

(18)

$$v_{C2}\left(t\right)=\frac{-i_p\left(t_3\right)}{2C_{oss}}\left(t-t_3\right)+v_i.$$

(19)

The transformer primary side voltage and current, and the secondary side voltage and current, are expressed as follows.

$$v_p\left(t\right)=-v_{C1}\left(t\right),$$

(20)

$$i_p\left(t\right)=\left[\frac{v_{C1}\left(t\right)}{r}+i_p\left(t_3\right)\right]e^{-\frac{r}{L_k}\left(t-t_3\right)},$$

(21)

$$i_{L1}\left(t\right)=\frac{-v_o}{L_1}\left(t-t_3\right)+i_{L1}\left(t_3\right),$$

(22)

$$i_{L2}\left(t\right)=\frac{-v_o}{L_2}\left(t-t_3\right)+i_{L2}\left(t_3\right),$$

(23)

This mode is ended when capacitor voltage $v_{C1}$ equals input voltage $v_i$. The time interval from $t_3$ to $t_4$ is given as

$$\Delta t_{34}=2C_{oss}·\frac{v_i}{i_p\left(t_3\right)}.$$

(24)

Mode 5 [$t_4\le t<t_5$]: Figure 8e shows the equivalent circuit of mode 5. The operation of this mode is very similar to that of mode 3, except for switch S₂ being turned on under the ZVS condition. At time $t=t_4$, capacitor C₂ is discharged to zero voltage for switch S₂ to be turned on. Therefore, switch S₂ is turned on under the ZVS condition. The transformer primary side voltage $v_p$ equals $-v_i$ to decrease primary side current $i_p.$ For ensuring the ZVS operation, a delay time $t_d$ is needed between the turning off of switch S₁ and the turning on of switch S₂. The required delay time is given as

$$t_d=2\Delta t_{34}=\frac{4C_{oss}}{n{i}_{L1}\left(t_3\right)}.$$

(25)

The voltages and currents of the transformer primary side and secondary side are expressed as follows.

$$v_p=-v_i,$$

(26)

$$i_p\left(t\right)=\frac{-v_i}{L_k}\left(t-t_4\right)+i_p\left(t_4\right),$$

(27)

$$i_{L1}\left(t\right)=-\frac{v_o}{L_1}\left(t-t_4\right)+i_{L1}\left(t_4\right),$$

(28)

$$i_{L2}\left(t\right)=-\frac{v_o}{L_2}\left(t-t_4\right)+i_{L2}\left(t_4\right).$$

(29)

This mode ends when the transformer primary side current $i_p$ equals zero.

Mode 6 [$t_5\le t<t_6$]: Figure 8f shows the equivalent circuit of this mode. The operation of this mode is very similar to that of mode 5, except that the transformer primary side current $i_p$ is negative and flows through switches S₂ and S₃. The voltages and currents of the transformer primary and secondary sides are expressed as follows.

$$v_p=-v_i,$$

(30)

$$i_p\left(t\right)=\frac{-v_i}{L_k}\left(t-t_5\right),$$

(31)

$$i_{L1}\left(t\right)=-\frac{v_o}{L_1}\left(t-t_5\right)+i_{L1}\left(t_5\right),$$

(32)

$$i_{L2}\left(t\right)=-\frac{v_o}{L_2}\left(t-t_5\right)+i_{L2}\left(t_5\right).$$

(33)

This mode ends when the transformer primary side current $i_p$ equals $\mathrm{n}{i}_{L2}$.

Mode 7 [$t_6\le t<t_7$]: Figure 8g shows the equivalent circuit of this mode. In this mode, switches S₂, S₃ are turned on and the transformer primary side voltage $v_p$ equals $-v_i$. The input energy is transferred to the secondary side through switches S₂, S₃, and the transformer. The energy from the primary side is transferred to the output through filter inductor L₂, filter capacitor C_o, and diode D₁. In this mode, inductor current $i_{L1}$ has to flow through filter inductor L₂ and filter capacitor C_o; therefore, diode D₂ is turned off. This mode ends when switch S₃ is turned off. The output current and filter inductor currents are expressed as follows.

$$i_o\left(t\right)=i_{L1}\left(t\right)+i_{L2}\left(t\right),$$

(34)

$$i_{L2}\left(t\right)=\frac{-v_o}{L_2}\left(\mathrm{t}-t_6\right)+i_{L2}\left(t_6\right).$$

(35)

$$i_{L2}\left(t\right)=\frac{-v_o}{L_2}\left(\mathrm{t}-t_6\right)+i_{L2}\left(t_6\right).$$

(36)

Mode 8 [$t_7\le t<t_8$]: Figure 8h shows the equivalent circuit of this mode. At $t=t_7$, switch S₃ is turned off. Capacitor C₃ for switch S₃ is charged from 0 V to $v_i$, and capacitor C₄ for switch S₄ is discharged from $v_i$ to 0 V. Capacitor voltage $v_{C3}$ for capacitor C₃ increases linearly because the capacitance of the switches S₃ and S₄ is very small. Capacitor voltages $v_{C3}, v_{C4}$ are given as follows.

$$v_{C3}\left(t\right)=\frac{n{i}_{L1}\left(t_7\right)}{2C_{oss}}\left(t-t_7\right),$$

(37)

$$v_{C4}\left(t\right)=\frac{-n{i}_{L1}\left(t_7\right)}{2C_{oss}}\left(t-t_7\right)+v_i.$$

(38)

At time $t=t_8$, capacitor voltage $v_{C3}$ equals input voltage $v_i$. The transformer primary side voltage and current, secondary side voltage and current, and output current are expressed as follows.

$$v_p=v_i-v_{C3}\left(t\right),$$

(39)

$$i_p\left(t\right)=n{i}_{L2}\left(t\right),$$

(40)

$$i_o\left(t\right)=i_{L1}\left(t\right)+i_{L2}\left(t\right),$$

(41)

$$i_{L1}\left(t\right)=\frac{n{v}_i-v_o}{L_1}\left(t-t_7\right)+i_{L1}\left(t_7\right),$$

(42)

$$i_{L2}\left(t\right)=\frac{-v_o}{L_2}\left(t-t_7\right)+i_{L2}\left(t_7\right).$$

(43)

The time interval from $t_7$ to $t_8$ is given as

$$\Delta t_{78}=2C_{oss}·\frac{v_i}{n{i}_{L2}\left(t_7\right)}.$$

(44)

Mode 9 [$t_8\le t<t_9$]: Figure 8i shows the equivalent circuit of this mode. At time $t=t_9$, capacitor C₄ for switch S₄ is discharged to zero voltage for turning on switch S₄. Therefore, switch S₄ is turned on under the ZVS condition. To ensure the ZVS operation, a delay time $t_d$ is needed between the turning off of switch S₃ and the turning on of switch S₄, and it has to be longer than time interval $\Delta t_{78}$. The required delay time is given as

$$t_d=2\Delta t_{78}=\frac{4C_{oss}·v_i}{n{i}_{L2}\left(t_7\right)}.$$

(45)

In this mode, the transformer primary and secondary side voltages equal 0 V, i.e., $v_p=v_{s,drop}=0 \mathrm{V}, v_s=0 \mathrm{V}$.

Both diodes D₁ and D₂ are turned on. The primary and secondary side currents of the transformer are expressed as follows:

$$i_p\left(t\right)=\left[i_p\left(t_8\right)+\frac{v_{s,drop}}{r}\right]e^{-\frac{r}{L_k}\left(t-t_8\right)}-\frac{v_{s,drop}}{r},$$

(46)

$$i_{L1}\left(t\right)=\frac{-v_o}{L_1}\left(t-t_8\right)+i_{L1}\left(t_8\right),$$

(47)

$$i_{L2}\left(t\right)=\frac{-v_o}{L_2}\left(t-t_8\right)+i_{L2}\left(t_8\right),$$

(48)

where $r$ is the equivalent series resistor for the leakage inductor $L_k$. This mode ends when switch S₂ is turned off.

Mode 10 [$t_9\le t<t_{10}$]: Figure 8j shows the equivalent circuit of this mode. At time $t=t_9$, switch S₂ is turned off because the energy stored in the leakage inductor is discharged through capacitor C₂ of switch S₂. Thus, capacitor C₂ is charged from 0 V to $v_i$ and capacitor C₁ is discharged from $v_i$ to 0 V. Capacitor voltages $v_{C1}, v_{C2}$ are expressed as

$$v_{C1}\left(t\right)=v_i-\frac{i_p\left(t_9\right)}{2C_{oss}}\left(t-t_9\right),$$

(49)

$$v_{C2}\left(t\right)=\frac{i_p\left(t_9\right)}{2C_{oss}}\left(t-t_9\right).$$

(50)

The transformer primary side voltage and current, and the secondary side voltage current, are expressed as follows.

$$v_p\left(t\right)=-v_{C2}\left(t\right),$$

(51)

$$i_p\left(t\right)=\left[i_p\left(t_9\right)+\frac{v_{C2}\left(t\right)}{r}\right]e^{-\frac{r}{L_k}\left(t-t_9\right)},$$

(52)

$$i_{L1}\left(\mathrm{t}\right)=\frac{-v_o}{L_1}\left(t-t_9\right)+i_{L1}\left(t_9\right),$$

(53)

$$i_{L2}\left(t\right)=\frac{-v_o}{L_2}\left(t-t_9\right)+i_{L2}\left(t_9\right).$$

(54)

This mode ends when capacitor voltage $v_{C2}$ equals input voltage $v_i$. The time interval from $t_9$ to $t_{10}$ is given as

$$\Delta t_{9 10}=2C_{oss}·\frac{v_i}{i_p\left(t_9\right)}.$$

(55)

Mode 11 [$t_{10}\le t<t_{11}$]: Figure 8k shows the equivalent circuit of this mode. At time $t=t_{10}$, capacitor C₁ is discharged to zero voltage for switch S₁ to be turned on. Thus, switch S₁ is turned on under the ZVS condition. Transformer primary side voltage $v_p$ equals $v_{in}$ to increase primary side current $i_p.$ To ensure the ZVS operation, a delay time $t_d$ is needed between the turning off of switch S₂ and the turning on of switch S₁. The required delay time is expressed as follows.

$$t_d=2\Delta t_{9 10}=\frac{v_i·4C_{oss}}{n{i}_{L2}\left(t_9\right)}.$$

(56)

The transformer primary side voltage and current, and the secondary side voltage and current, are expressed as follows.

$$v_p=v_i,$$

(57)

$$i_p\left(t\right)=\frac{v_i}{L_k}\left(t-t_{10}\right)+i_p\left(t_{10}\right),$$

(58)

$$i_{L1}\left(t\right)=-\frac{v_o}{L_1}\left(t-t_{10}\right)+i_{L1}\left(t_{10}\right),$$

(59)

$$i_{L2}\left(t\right)=-\frac{v_o}{L_2}\left(t-t_{10}\right)+i_{L2}\left(t_{10}\right).$$

(60)

This mode is ended when the primary side current $i_p$ equals 0 A.

Mode 12 [$t_{11}\le t<t_0$]: Figure 8l shows the equivalent circuit of this mode. The operation of this mode is very similar to that of mode 11, except that the transformer primary side current $i_p$ is positive and flows through switches S₁ and S₄. This mode ends when primary side current $i_p$ equals $-n{i}_{L1}$. The voltage and current of the transformer are expressed as follows.

$$v_p=v_i,$$

(61)

$$i_p\left(t\right)=\frac{v_i}{L_k}\left(t-t_{11}\right),$$

(62)

$$i_{L1}\left(t\right)=-\frac{v_o}{L_1}\left(t-t_{11}\right)+i_{L1}\left(t_{11}\right),$$

(63)

$$i_{L2}\left(t\right)=-\frac{v_o}{L_2}\left(t-t_{11}\right)+i_{L2}\left(t_{11}\right).$$

(64)

The operation of the proposed converter is analyzed through mode 1–12. It is confirmed that the waveforms of the primary side voltage and current in modes 1–6 are symmetrical to those in modes 7–12. In addition, by analyzing the operation, it is confirmed that one period is shaped by twelve modes and four switches are turned on and turned off under the ZVS condition.

3. Characteristics of the Proposed Converter

3.1. Voltage Gain and Effective Duty Cycle

In Figure 7 and Figure 8, a time shift occurs between S₁ and S₃ for achieving zero voltage at time $t_2-t_3$, $t_8-t_9$. Moreover, based on the operation analysis in Section 2, rectification and freewheeling are performed when the two diodes are conducted during the time intervals $t_3-t_6$ and $t_9-t_0$.

The input energy is never transferred to the output. Therefore, the effective duty cycle is smaller than the designed duty cycle, as shown in Figure 9. The effective duty cycle is expressed as

$$D_{eff}=\frac{v_o}{n{v}_i}=\frac{n^{\prime 2}{v}_o}{v_s}$$

(65)

where $n^{\prime }$ is the turns ratio of the coupled inductor as the transformer.

The designed duty cycle $D$ is expressed as

$$D=D_{eff}+D_{loss},$$

(66)

where $D$ is the duty cycle of the switch ($D<0.5$) and $D_{loss}$ is the duty cycle loss during the time intervals $t_3-t_6$ and $t_9-t_0$. The duty cycle loss has to be much smaller than the effective duty cycle and is expressed as $D_{loss}=2f_s\left(t_6-t_3\right)=2f_s\left(t_0-t_9\right)$, where $f_s$ is the switching frequency of the switches.

The relationship curve between duty ratio $D$ and voltage gain $v_o/v_s$ is illustrated in Figure 10a, and the comparison curve of voltage gain between the conventional CDR and CICDR is illustrated in Figure 10b and voltage gain $v_o/v_s$ for different values of turns ratio $n$; (b) Comparison curve between the conventional CDR and the proposed CICDR.

3.2. Voltage Stress

In modes 1 and 2, diode D₁ is in the off state, whereas diode D₂ is conducting. On the contrary, in modes 7 and 8, diode D₂ is in the off state, whereas diode D₁ is conducting. Thus, the voltage stress of the rectifier diode at the transformer secondary side can be expressed as

$$V_{D1}=V_{D2}=\frac{V_s}{n}.$$

(67)

For illustrating the voltage stress of the proposed converter, Figure 11 shows the relationship curve between the voltage stress and the turns ratio $n$.

3.3. Resonant Capacitance

The resonant capacitance depends upon the output capacitance $C_{oss}$ of the two MOSFETs and the parasitic capacitance of the primary side, $C_{tmr,p}$, for high switching frequency $f_s$. Thus, the resonant capacitance is expressed as

$$C_r=2C_{oss}+C_{tmr,p}.$$

(68)

In addition, the energy stored at the resonant capacitance can be expressed as

$$E_{C_r}=\frac{1}{2}\left(2C_{oss}+C_{tmr,p}\right)v_i^2.$$

(69)

3.4. Resonant Inductance

The leakage inductance on the primary side of the transformer functions as the resonant inductance. Resonant inductance can be determined by resonant frequency ${\omega }_r$ (or delay time $t_d),$ and the resonant capacitance.

The resonant frequency, the delay time for ensuring the ZVS operation, and resonant inductance are expressed as follows.

$${\omega }_r=\frac{1}{\sqrt{L_r{C}_r}},$$

(70)

$$t_d=\frac{\pi \sqrt{L_r{C}_r}}{2},$$

(71)

$$L_r=\frac{1}{{\omega }_r^2{C}_r}=\frac{1}{{\left(\frac{\pi }{2t_d}\right)}^2\left(2C_{oss}+C_{tmr,p}\right)}.$$

(72)

The energy stored in the resonant inductance is expressed as

$$E_{L_r}=\frac{1}{2}{L}_r{i}_p^2.$$

(73)

To ensure ZVS operation, the energy stored in the resonant inductance should be much larger than that stored in the resonant capacitance.

4. Design Considerations

To verify the proposed converter, a 600 W prototype converter with the proposed rectification method was designed and built. The hardware system parameters are as follows:

(1)

Input voltage range $V_i$: 360–400 V;

(2)

Output voltage $V_o$: 12 V;

(3)

Rated output power $P_o$: 600 W;

(4)

Switching frequency $f_s$: 100 kHz;

(5)

Maximum output current $I_o$: 50 A;

(6)

Output filter ripple voltage $\mathsf{\Delta }{v}_o$: 0.12 V;

(7)

Output filter ripple current $\mathsf{\Delta }{i}_L$: 9 A.

4.1. Design of the Isolation Transformer

The TDK ETD 39/20/13 core with $B_{max}=200 \mathrm{mT}$, $A_e=1.25{ \mathrm{cm}}^2$ is used in the isolation transformer for minimizing the core loss. In addition, the maximum duty cycle is 0.4 for maximum efficiency. By Faraday’s law, the transformer primary winding is determined as

$$N_p=\frac{v_{i\left(\min \right)}{D}_{max}}{B_{max}{A}_e{f}_s}=46.08.$$

(74)

Thus, 46 turns are chosen for this design. Therefore, the secondary side voltage and number of winding turns are determined as follows.

$$V_s=\frac{V_o}{n}=\frac{n{\prime }^2{V}_o}{D}=40 \mathrm{V},$$

(75)

$$N_s=N_p\frac{V_s}{V_{p\left(\min \right)}}=4.$$

(76)

From Equations (74)–(76), the magnetizing inductance is calculated as

$$L_m=v_{i\left(min\right)}\frac{\mathsf{\Delta }t}{\mathsf{\Delta }{i}_L\frac{N_s}{N_P}}=192 \mathsf{\mu }\mathrm{H}.$$

(77)

4.2. Selection of the Filter Coupled Inductors and Capacitor

For lower leakage inductance, lower power loss, and high step-down voltage gain, the turns ratio $n^{\prime }$ is determined as 1.15. Thus, filter-coupled inductance $L=L_1=L_2$ is calculated as

$$L=L_1=L_2=\frac{D\left(v_s-v_o\right)}{\mathsf{\Delta }{i}_L{f}_s}=8 \mathsf{\mu }\mathrm{H}.$$

(78)

The filter capacitance is usually related to output ripple voltage $\mathsf{\Delta }{v}_o$, which has to be less than 1% of rated output voltage $V_o$.

Thus, filter capacitance is calculated as

$$C_o=\frac{I_o{D}_{max}}{0.01V_o{f}_s}=1680 \mathsf{\mu }\mathrm{F}.$$

(79)

4.3. Selection of the Rectifier Diodes and Power Switches

When rectifier diodes D₁ or D₂ are conducting, the maximum current flowing through the diode is $I_{o\left(max\right)}=i_D{}_{\left(max\right)}=50 \mathrm{A}$. Therefore, Vishay V60100C Dual High-Voltage Trench is used in this design.

In addition, Vishay IRFP460A MOSFETs with output parasitic capacitance $C_{oss}=870\mathrm{pF}$ are used as the active power switches for this design. Therefore, the resonant capacitance is approximated as 3.5 nF. Based on Equations (70) and (72), the resonant inductor $L_r$ is approximately 5.5 $\mathsf{\mu }\mathrm{H}$.

5. Experimental Verification

Based on the design considerations, a 600 W laboratory prototype of the proposed converter, shown in Figure 12, was manufactured for verifying the theoretical analysis and effectiveness of the converter. Additionally, Figure 13 shows the designed block diagram of the proposed converter. A digital signal processing (DSP) controller was used to generate the PWM for a MOSFET gate. The DSP control was realized using the TMS320F28335 chip, which has a C28X Core 32-bit FPU and is capable of high-speed processing of decimal data with a processing capability of 150 MHz. Additionally, the ADC circuit was capable of sampling at 12.5 MSPS with 16 channels, and the analog input signal range was 0 to 3 V.

Figure 14 shows gate-source voltage $v_{GS}$ waveforms of switches S₁, S₂, S₃, and S₄. Based on the design considerations, four switches were shifted to control the power transferred from the primary side of the transformer to the secondary side. Figure 15a shows the voltage and current waveforms of switch S₁ under the half-load condition. The measured voltage and current waveforms of switch S₂ under the full-load condition are shown in Figure 15b. Operation of the switches under the ZVS condition is verified through Figure 15c. In addition, Figure 16a,b shows the primary side voltage and current of the transformer under the half- and full-load conditions, respectively. The current waveforms of the filter inductor with CICDR for the half- and full-load conditions are shown in Figure 17a,b. The fact that CDR is suitable for high output current has already been verified through various experiments conducted in recent years. Figure 18 shows the calculated efficiency of the proposed converter, along with the input power and output power under various load conditions.

The efficiencies of various conventional converters are shown in Figure 15. A comparison with conventional converters such as hard switching, center-tapped, and CDR shows that the proposed converter with CICDR is much better than those with low-voltage and high current, and it has a lower loss.

6. Conclusions

In this paper, an improved high step-down DC-DC converter with CICDR for EVs has been proposed. Its topology is based on the conventional phase-shift full-bridge converter. In addition, the proposed converter achieves high efficiency based on the soft-switching technique with the phase-shifting technique. Furthermore, a current-doubler rectifier with a coupled inductor is adopted to reduce various losses, extend the duty range, and ensure ZVS operation and high efficiency. The effectiveness and validity of the proposed converter for low-voltage battery charging in EVs was experimentally verified. The experimental results showed that the proposed converter with CICDR can achieve high efficiency under various load conditions when compared with the conventional converter. The characteristics of the proposed converter are summarized as follows:

• The CICDR rectification method can achieve high output current and high step-down voltage gain for EVs;
• The voltage stress of the rectifier diode is low. Consequently, the losses of the rectifier diode can be reduced and high efficiency can be obtained;
• The leakage energy can turn on the switch under the ZVS condition. This reduces conduction loss and improves efficiency.