Voltage Balance Switching Scheme for Series-Connected SiC MOSFET LLC Resonant Converter

Abstract

To achieve high efficiency and power density, silicon carbide (SiC)-based Inductor-Inductor-Capacitor (LLC) resonant converters are applied to the DC/DC converter stage of a solid-state transformer (SST). However, because the input voltage of an SST is higher than the rated voltage of a commercial SiC device, it is essential to connect SiC devices in series. This structure is advantageous in terms of voltage rating, but a parasitic capacitance tolerance between series-connected SiC devices causes voltage imbalance. Such imbalance greatly reduces system stability as it causes overvoltage breakdown of SiC device. Therefore, this paper proposes a switching scheme to solve the voltage imbalance between SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). The proposed scheme sequentially turns off series-connected SiC MOSFETs to compensate for the turn-off delays caused by parasitic capacitor tolerances. In addition, dead-time selection methods to achieve voltage balance and zero voltage switching simultaneously are provided in detail. To verify the effectiveness of the proposed scheme, experiments were conducted on a 2 kW series-connected SiC MOSFET LLC resonant converter prototype.

1. Introduction

Due to the recent interest in smart grid, distributed power system, and renewable energy, researches have been actively conducted to replace large and heavy line-frequency transformers. A solid-state transformer (SST) proposed as a solution is a power converter that converts the magnitude or type of voltage using a power semiconductor and a high-frequency transformer [1,2,3,4]. As shown in Figure 1, an SST consists of an AC/DC rectifier stage, a DC/DC converter stage, and a DC/AC inverter stage. In particular, the DC/DC converter stage enables DC voltage conversion, high power density, and galvanic isolation by using a high-frequency transformer. The most commonly used topology for the DC/DC converter stage is a dual active bridge (DAB) [5,6,7,8], which exhibits characteristics of galvanic isolation and high power density, and can achieve zero-voltage switching (ZVS) without additional circuit. However, due to a high turn-off current, the turn-off loss is large and it is difficult to guarantee ZVS under light load conditions. In addition, it is difficult to achieve high efficiency over a wide load range because of the large conduction losses caused by circulating current. At the same time, an Inductor-Inductor-Capacitor (LLC) resonant converter has very low switching losses because it guarantees ZVS of the switches and zero-current switching (ZCS) of the rectifier diodes from no load to full load. As a result, operating at high switching frequencies, the size of passive elements and transformers can be reduced, which allows for high power density. Therefore, research has been conducted to replace DAB converters with LLC resonant converters to improve the efficiency and power density of DC/DC converter stage [3,9,10,11,12]. However, silicon (Si)-based LLC resonant converters still exhibit high conduction and turn-off losses, making it difficult to design for high frequencies and power [3,9,10].

To overcome the physical limitations of Si materials, researches are being conducted actively on wide-bandgap (WBG) materials such as silicon-carbide (SiC) and gallium-nitride (GaN). WBG materials have a very thin drift layer because they have a higher dielectric breakdown field than Si materials. As a result, WBG devices have a low on-resistance and reverse recovery loss [13,14,15,16]. Therefore, much effort is being put in to apply WBG devices to LLC resonant converters to achieve high efficiency and power density [17,18,19,20,21].

Among WBG devices, GaN devices typically have low voltage ratings of less than 600 V and hence SiC devices, which have relatively higher voltage ratings, are suitable for high-voltage applications. Although technological advances in SiC devices have greatly improved their voltage rating, they are still not a perfect replacement for Si devices. Thus, in the case of an SST where very high voltage ratings are required, it is essential to connect SiC devices in series [22,23,24,25]. However, connecting SiC devices in series may cause voltage imbalance due to a parasitic capacitor tolerance between them, which causes overvoltage breakdown of the device. In particular, SiC devices have a very small parasitic capacitor as their drift layers are thinner than those of Si devices [26], which causes a large voltage imbalance even with small parameter tolerances.

To solve voltage imbalance problems caused by the series connection, a number of methods have been proposed. Snubber circuits are the simplest way to resolve voltage imbalance [22,23,24,25,27]. These circuits can reduce voltage and current stress and switching losses, as well as voltage imbalances [23,24,27]. However, snubber circuits not only decrease the switching speed and power density but also reduce power conversion efficiency due to additional losses. In [22,25], a parameter optimization design was proposed to minimize snubber losses, but the optimal design of parameters is complicated.

In the active voltage control (AVC) method, the drain-source voltage of the switch is directly controlled [28,29,30,31,32,33,34,35,36]. In [28,29,30], a temporary clamp technique is proposed to eliminate the voltage imbalance. In [31,32,33,34,35,36], voltage imbalance was eliminated by adjusting the gate signal timing of series-connected switches. However, the gate driver circuit is enlarged by the AVC circuit, and these methods do not solve voltage imbalance during the transient [28,29,30]. In addition, it takes several milliseconds to solve voltage imbalance. Therefore, it is difficult to apply the methods to WBG devices operating at high frequency [31,32,33,34,35,36].

Quasi-active gate control (QAGC) [37,38] is a combination of snubber circuits and the AVC method. This method has the advantage that the number of additional devices is small and the circuit is simple. However, as the number of series-connected switches increase, the voltage balancing performance is greatly reduced and the parameter design is complicated.

Gate current control [39,40,41,42,43] eliminates voltage imbalance by controlling the gate charge or discharge current. This method, however, complicates the gate driver circuit due to additional components [39,40] and reduces the switching speed by limiting the gate current. In addition, very high current control bandwidth is required for fast response speed [41,42,43].

To overcome these problems, a gate signal delay control has been proposed in [44]. The advantage of this method is that no voltage balancing circuit is required, which implies no additional losses or power density reduction. In addition, this method enables voltage balancing through simple gate signal adjustment even when the operating point changes. However, analysis of several series-connected switches is insufficient, and the analysis of problems that occur during turn-on when applying this method is not provided.

This paper proposes a switching scheme to solve the voltage imbalance in series-connected SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) LLC resonant converter without any additional circuitry. The proposed scheme sequentially turns off series-connected SiC MOSFETs to compensate for the turn-off delay caused by parasitic capacitor tolerances. A detailed analysis of the effect of input and output parasitic capacitance differences on voltage imbalance is presented. In addition, a dead-time analysis considering the junction capacitors of the rectifier diode is provided to achieve both voltage balance and ZVS. The effectiveness of the proposed scheme is verified experimentally using a 2 kW series-connected SiC MOSFETs LLC resonant converter prototype.

2. Series-Connected SiC-MOSFET LLC Resonant Converter

2.1. System Description

Figure 2 shows a series-connected SiC-MOSFET LLC resonant converter circuit. The circuit consists of a half-bridge converter with a split-capacitor, resonant tank, and center tap rectifier. V_in represents the input voltage of the bridge, C_ds1 and C_ds2 are split capacitors, respectively, Q₁–Q₈ are SiC-MOSFETs, and their output capacitances are expressed as C_oss1~C_oss8. Switches Q₁–Q₄ are connected in series with each other and they are turned on and off at the same time. The same is true for switches Q₅–Q₈. In addition, Q₁–Q₄ and Q₅–Q₈ operate complementary to each other. The resonant tank consists of the resonant capacitor C_r, leakage inductor of the transformer L_r, and magnetizing inductor of the transformer L_m. The center tap rectifier consists of rectifier diodes D₁ and D₂, an output capacitor C_o, and a load resistor R_L where C_j1 and C_j2 denote junction capacitances of the rectifier diodes.

2.2. Operating Principle

Figure 3 and Figure 4 show the main waveforms of the series-connected SiC MOSFET LLC resonant converter and the equivalent circuit for each mode, respectively. To simplify analysis, it is assumed that the parasitic capacitances of the switches are the same and circuit operation is steady-state. The operation is divided into ten modes during the switching period.

Mode 1 [t₀ < t < t₁]: At t₀, Q₁–Q₄ are turned on at the same time and Mode 1 is initiated. In this mode, L_r and C_r participate in resonance. L_m does not participate in resonance because it is clamped by the output voltage. A resonance current i_r flows through Q₁–Q₄. i_r is larger than the magnetizing inductance current i_Lm and energy is transferred to the load through the rectifier diode D₁. This mode ends when i_r equals i_Lm. During this mode, i_r, i_Lm, and the voltage of the resonant capacitor v_Cr can be expressed as follows

$$i_r\left(t\right)=i_r\left(t_0\right)\cdot \cos {\omega }_{r1}\left(t-t_0\right)+\frac{V_a}{Z_1}\sin {\omega }_{r1}\left(t-t_0\right)$$

(1)

$$i_{Lm}\left(t\right)=\frac{V_{op}}{L_m}t+i_{Lm}\left(t_0\right)$$

(2)

$$v_{Cr}\left(t\right)=Z_1{i}_r\left(t_0\right)\cdot \sin {\omega }_{r1}\left(t-t_0\right)-V_a\cos {\omega }_{r1}\left(t-t_0\right)+\frac{V_{in}}{2}-V_{op}$$

(3)

where ω_r1 = 1/√(L_rC_r) is the resonant angular frequency, Z₁ = √(L_r/C_r) is the characteristic impedance, n is the turn ratio of transformer, V_op = nV_o is the output voltage converted to the transformer primary side, and V_a = V_in/2 − V_op − V_cr(t₀).

Mode 2 [t₁ < t < t₂]: This mode starts when the linearly increasing i_Lm becomes equal to i_r. At this time, the rectifier diodes D₁ and D₂ do not conduct, and junction capacitances C_j1 and C_j2 participate in resonance. L_m also participates in resonance as it is no longer clamped by the output voltage. Therefore, the resonant capacitor C_r, resonant inductor L_r, magnetizing inductor L_m, and junction capacitances of the rectifier diodes C_j1 and C_j2 form a resonant tank. Assuming that L_m is larger than L_r and that the interval of this mode is sufficiently short relative to the switching period, the magnitude of i_Lm is constant [45]. This mode ends when Q₁–Q₄ are turned off. During this mode, i_r, i_Lm, and v_Cr can be expressed as follows

$$i_r\left(t\right)=\left[i_r\left(t_1\right)-\frac{I_{Lm,pk}{C}_{eq1}}{C_{jp}}\right]\cos {\omega }_{r2}\left(t-t_1\right)+\frac{V_b}{Z_2}\sin {\omega }_{r2}\left(t-t_1\right)+\frac{I_{Lm,pk}{C}_{eq1}}{C_{jp}}$$

(4)

$$i_{Lm}\left(t\right)=I_{Lm,pk}=\frac{n{V}_o}{L_m}\frac{T_s}{4}$$

(5)

$$\begin{array}{ll}{v}_{Cr}\left(t\right)& =\frac{1}{C_r{\omega }_{r2}}\left[i_r\left(t_1\right)-\frac{I_{Lm,pk}{C}_{eq1}}{C_{jp}}\right]\sin {\omega }_{r2}\left(t-t_1\right)-\frac{V_b}{Z_2{C}_r{\omega }_{r2}}\cos {\omega }_{r2}\left(t-t_1\right)+\frac{I_{Lm,pk}{C}_{eq1}}{C_{jp}{C}_r}t\\ & +\frac{V_a}{Z_1{C}_r{\omega }_{r2}}+v_{Cr}\left(t_2\right)\end{array}$$

(6)

where T_s is the switching period, n is transformer turn ratio, ω_r2 = 1/√(L_rC_eq1) is the resonant angular frequency, Z₂ = √(L_r/C_eq1) is the characteristic impedance, C_jp = 2C_j1/n² is the total junction capacitance of the rectifier diode converted to the transformer primary side, C_eq1 = C_r‖C_jp, and V_b = V_in/2 − V_op − V_cr(t₁).

Mode 3 [t₂ < t < t₃]: This mode starts when Q₁–Q₄ are turned off. In this mode, output capacitances C_oss1–C_oss8 and junction capacitances, C_j1 and C_j2, are charged or discharged by i_Lm. This mode ends when C_j1 and C_j2 are fully charged and discharged, respectively. During this mode, i_r, i_Lm, and v_Cr can be expressed as follows

$$i_r\left(t\right)=\left[i_r\left(t_2\right)-\frac{I_{Lm,pk}{C}_{eq2}}{C_{jp}}\right]\cos {\omega }_{r3}\left(t-t_2\right)+\frac{V_c}{Z_3}\sin {\omega }_{r3}\left(t-t_2\right)+\frac{I_{Lm,pk}{C}_{eq2}}{C_{jp}}$$

(7)

$$i_{Lm}\left(t\right)=I_{Lm,pk}=\frac{n{V}_o}{L_m}\frac{T_s}{4}$$

(8)

$$\begin{array}{ll}{v}_{Cr}\left(t\right)& =\frac{1}{C_r{\omega }_{r3}}\left[i_r\left(t_2\right)-\frac{I_{Lm,pk}{C}_{eq2}}{C_{jp}}\right]\sin {\omega }_{r3}\left(t-t_2\right)-\frac{V_c}{Z_3{C}_r{\omega }_{r3}}\cos {\omega }_{r3}\left(t-t_2\right)+\frac{I_{Lm,pk}{C}_{eq2}}{C_{jp}{C}_r}t\\ & +\frac{V_c}{Z_3{C}_r{\omega }_{r3}}+v_{Cr}\left(t_2\right)\end{array}$$

(9)

where ω_r3 = 1/√(L_rC_eq2) is the resonant angular frequency, Z₃ = √(L_r/C_eq2) is the characteristic impedance, C_oss,eq = C_oss1/2 is the total output capacitance of the switches, C_eq2 = C_oss,eq‖C_r‖C_jp, and V_c = V_in/2 − V_op − V_cr(t₂).

Mode 4 [t₃ < t < t₄]: At t₃, the rectifier diode D₁ is turned off and D₂ is turned on. Thus, the energy stored in the magnetizing inductor is not fully used to charge and discharge output capacitances; instead, a part of it is transferred to the load through D₂. This mode ends when C_oss1–C_oss4 are fully charged and C_oss5–C_oss8 are fully discharged. During this mode, i_r, i_Lm, and v_Cr can be expressed as follows

$$i_r\left(t\right)=i_r\left(t_3\right)\cos {\omega }_{r4}\left(t-t_3\right)+\frac{V_d}{Z_4}\sin {\omega }_{r4}\left(t-t_3\right)$$

(10)

$$i_{Lm}\left(t\right)=-\frac{V_{op}}{L_m}t+i_{Lm}\left(t_3\right)$$

(11)

$$v_{Cr}\left(t\right)=\frac{i\left(t_3\right)}{C_r{\omega }_{r4}}\sin {\omega }_{r4}\left(t-t_3\right)-\frac{V_d}{Z_4{C}_r{\omega }_{r4}}\cos {\omega }_{r3}\left(t-t_3\right)+\frac{V_d}{Z_4{C}_r{\omega }_{r4}}+v_{Cr}\left(t_3\right)$$

(12)

where ω_r4 = 1/√(L_rC_eq3) is the resonant angular frequency, Z₄ = √(L_r/C_eq3) is the characteristic impedance, C_eq3 = C_oss,eq‖C_r, and V_d = V_in/4 + V_op – V_cr(t₃).

Mode 5 [t₄ < t < t₅]: At t₄, the output capacitance is fully charged or discharged and this mode starts. In this mode, all the switches are off but the body diodes of Q₅–Q₈ start to conduct due to the continuity of the resonant current i_r. Therefore, the drain-source voltage of Q₅–Q₈ is equal to the forward voltage of its body diode; this ensures that ZVS conditions are achieved. This mode ends when Q₅–Q₈ are turned on. At this time, if resonant current i_r flows in the positive direction, Q₅–Q₈ are ZVS turned on. During this mode, i_r, i_Lm, and v_Cr can be expressed as follows

$$i_r\left(t\right)=i_r\left(t_4\right)\cos {\omega }_{r1}\left(t-t_4\right)+\frac{V_e}{Z_1}\sin {\omega }_{r1}\left(t-t_4\right)$$

(13)

$$i_{Lm}\left(t\right)=-\frac{V_{op}}{L_m}t+i_{Lm}\left(t_4\right)$$

(14)

$$v_{Cr}\left(t\right)=Z_{1}i\left(t_3\right)\sin {\omega }_{r1}\left(t-t_4\right)-V_e\cos {\omega }_{r1}\left(t-t_4\right)+V_{op}-V_{in}/2$$

(15)

where V_e = V_op − V_cr(t₄) − V_in/2.

Because the operation principle of Mode 6 to Mode 10 is similar to that of Mode 1 to Mode 5, a detailed description of these modes is omitted here.

3. Analysis of Voltage Imbalance in the Series-Connected SiC MOSFET LLC Resonant Converter

In this section, the effect of parasitic capacitance differences of series-connected switches on their turn-on and turn-off switching characteristics is discussed.

3.1. Turn-On Switching Characteristics

As shown in Figure 3, during Mode 3 and Mode 4, Q₅–Q₈ are off, and C_oss5–C_oss8 are discharged by i_r. Because it is assumed that all parasitic capacitances of the switches are equal, the drain-source voltages V_ds of Q₅~Q₈ simultaneously decreases to zero. If C_oss5~C_oss8 are different, their V_ds values decrease at different rates. These rates are inversely proportional to the output capacitance and can be calculated as follows

$$\Delta Q=C_{oss}\cdot \Delta V_{ds}$$

(16)

where ΔQ is the incremental change in the charge supplied by the resonant current, C_oss is the output capacitance of the switch, and ΔV_ds is the incremental change in the drain-source voltage of the switch.

Figure 5 shows the turn-on switching transient waveforms when C_oss5–C_oss8 satisfy the following inequality:

$$C_{oss5}<C_{oss6}=C_{oss7}=C_{oss8}.$$

(17)

According to Equations (16) and (17), the drain-source voltage of switch Q₅, which has the smallest output capacitance, decreases most rapidly. Figure 6a shows the switch discharge situations during Interval 1. Because v_ds5 is not fully discharged, the body diode of Q₅ does not conduct. Figure 6b shows the switch discharge situations during Interval 2. Once v_ds5 is completely discharged, the body diode of Q₅ conducts due to continuity of the current. Those switches that are not yet fully discharged are discharged by the resonant current. v_ds5 is clamped to the body diode forward voltage V_f until all the switches are fully discharged. Therefore, during turn-on transient, differences in the output capacitance do not cause voltage spikes.

As shown in Figure 6c, the body diodes of all switches are conducting when Q₅–Q₈ are fully discharged. Because v_ds of the switches is clamped to V_f, all the switches achieve ZVS conditions and differences in the input capacitance of the switches do not substantially affect v_ds. Thus, when ZVS turn-on is achieved, input and output capacitance differences between the series-connected switches do not cause problems during turn-on switching transients.

3.2. Turn-Off Switching Characteristics

The drain-source voltage imbalance caused by the parasitic capacitance difference in the series-connected switches during the turn-off switching transients is discussed in this section. Figure 7 shows the turn-off switching waveforms of the gate signal v_sig, gate-source voltage v_gs, and drain-source voltage v_ds of the switches with different input capacitance C_iss or output capacitance C_oss value. Figure 7a shows the turn-off switching waveforms when the input capacitance C_iss1 of switch Q₁ is larger than the input capacitances C_iss2–C_iss4 of switches Q₂–Q₄. Although turn-off signals are simultaneously applied at t_a1, v_gs decreases at different rates because the input capacitances are different. In other words, v_gs1 of switch Q₁ decreases slowly and it takes longer to decrease from the gate-source turn-on voltage V_gs,on to the threshold voltage V_th. In this case, the turn-off delay caused by the difference in input capacitance can be expressed as [44,46]

$$\Delta t_{d1}=R_g\left(C_{iss1}-C_{iss2}\right)\ln \left(\frac{V_{gs,on}}{V_{th}}\right)$$

(18)

where R_g denotes a gate resistor.

As can be seen in Figure 7a, even though the output capacitance C_oss of series-connected switches is equal, their v_ds rises at different time due to the time delay shown in Equation (18). Thus, a difference in input capacitance causes voltage imbalance. In this case, the steady-state voltage ratios of Q₁–Q₄ follow the relationship

$$v_{ds1}:v_{ds2}:v_{ds3}:v_{ds4}=\frac{\Delta t_{d2}}{C_{oss1}}:\frac{\Delta t_{d1}+\Delta t_{d2}}{C_{oss2}}:\frac{\Delta t_{d1}+\Delta t_{d2}}{C_{oss3}}:\frac{\Delta t_{d1}+\Delta t_{d2}}{C_{oss4}}$$

(19)

where ∆t_d2 is the time taken for v_ds1 to reach steady-state from zero voltage under different input capacitance condition.

By assumption, the output capacitances are equal. Using Equation (19), the magnitude of voltage imbalance due to input capacitance tolerance is calculated as

$$\left|v_{ds2}-v_{ds1}\right|=\left|\frac{V_{in}\Delta t_{d1}}{3\Delta t_{d1}+4\Delta t_{d2}}\right|.$$

(20)

Figure 7b shows the turn-off switching waveforms when the output capacitance C_oss1 of switch Q₁ is larger than the output capacitances C_oss2–C_oss4 of switches Q₂–Q₄. At t_a1, the turn-off signal is applied, and v_gs decreases at the same rate.

At t_a2, v_gs reaches V_th and v_ds increases. Because C_oss1 is larger than C_oss2–C_oss4, v_ds1 increases slowly, which causes a voltage imbalance. In this case, the steady-state voltage ratios of Q₁–Q₄ and the magnitude of voltage imbalance due to output capacitance tolerance are calculated as

$$v_{ds1}:v_{ds2}:v_{ds3}:v_{ds4}=\frac{\Delta t_{d3}}{C_{oss1}}:\frac{\Delta t_{d3}}{C_{oss2}}:\frac{\Delta t_{d3}}{C_{oss3}}:\frac{\Delta t_{d3}}{C_{oss4}}$$

(21)

$$\left|v_{ds2}-v_{ds1}\right|=\left|\frac{C_{oss1}-C_{oss2}}{3C_{oss1}+C_{oss2}}{V}_{in}\right|$$

(22)

where ∆t_d3 is the time taken for v_ds1 to reach steady-state from zero voltage under different output capacitance condition.

4. Proposed Switching Scheme

In this section, a gate signal compensation method is proposed to overcome the voltage imbalance caused by discrepancies between the parasitic capacitances of series-connected switches. To simplify analysis, it is assumed that the parasitic capacitances of all switches, except Q₁, are equal and the parasitic capacitances of Q₁ are larger than those of Q₂–Q₈.

Figure 8 shows the operation principle of the proposed switching scheme. As discussed in Section 3, when the proposed switching scheme is not applied, switch Q₁, which has a large parasitic capacitance, causes voltage imbalance. In this case, the steady-state voltage ratios of Q₁–Q₄ and the magnitude of voltage imbalance due to input and output capacitance tolerance are calculated as

$$v_{ds1}:v_{ds2}:v_{ds3}:v_{ds4}=\frac{\Delta t_{d4}}{C_{oss1}}:\frac{\Delta t_{d1}+\Delta t_{d4}}{C_{oss2}}:\frac{\Delta t_{d1}+\Delta t_{d4}}{C_{oss3}}:\frac{\Delta t_{d1}+\Delta t_{d4}}{C_{oss4}}$$

(23)

$$\left|v_{ds2}-v_{ds1}\right|=\left|\frac{\left(C_{oss1}-C_{oss2}\right)\Delta t_{d4}+C_{oss1}\Delta t_{d1}}{\left(3C_{oss1}+C_{oss2}\right)\Delta t_{d1}+3C_{oss1}\Delta t_{d1}}{V}_{in}\right|$$

(24)

where ∆t_d4 is the time taken for v_ds1 to reach from zero voltage to steady-state value under different input and output capacitance condition.

Figure 8b shows the turn-off switching waveforms when the proposed scheme is applied. This scheme solves voltage imbalance by sequentially turning off switches with a large parasitic capacitance. This scheme ensures time for v_ds of the switch with a large parasitic capacitance to increase to V_in/4. As shown in Figure 8b, t_comp is required to compensate for the turn-off delay and it can be calculated as follows

$$t_{comp}=\Delta t_{d1}+\Delta t_{d5}$$

(25)

where ∆t_d1 and ∆t_d5 represent the time taken for v_gs to reach from V_gs,on to V_th without and with the proposed switching scheme, respectively. ∆t_d1 is the time delay caused by input capacitance tolerance and it is constant in Equation (18), regardless of whether the proposed scheme is applied or not. Therefore, ∆t_d5 must be calculated to derive the gate signal compensation time. The magnetizing current is constant during turn-off switching transient by assumption. The best case is when the voltages of the series-connected switches are V_in/4 and this relationship is expressed as

$$\frac{V_{in}}{4}=\frac{\Delta t_{d6}}{C_{oss2}}{I}_{Lm,pk,H}=\frac{\Delta t_{d5}+\Delta t_{d6}}{C_{oss1}}{I}_{Lm,pk,H}$$

(26)

$$I_{Lm,pk,H}=\frac{C_{oss,H}}{C_{oss,H}+C_{oss,L}}{I}_{Lm,pk}$$

(27)

where I_Lm,pk,H is the magnitude of current that charges the upper switches of the half-bridge during the dead-time and C_oss,H and C_oss,L are the total output capacitance of the upper and lower switches, respectively.

Using Equation (25), ∆t_d5 can be calculated as follows:

$$\Delta t_{d5}=\frac{C_{oss1}-C_{oss2}}{4I_{Lm,pk}}{V}_{in}.$$

(28)

5. Design Considerations for Achieving ZVS

In this section, the dead-time design process for achieving ZVS is analyzed. As discussed earlier, the LLC resonant converter achieves ZVS from no load to full load. However, some constraints must be met to achieve ZVS, one of which can be expressed as

$$I_{Lm,pk}\cdot t_{dead}\ge {\displaystyle \sum _{i=1}^8\left(C_{oss1}\Delta V_{ds,i}\right)}$$

(29)

where t_dead denotes dead-time [45,47].

Equation (29) indicates that charge supplied by the magnetizing current I_Lm,pk should be larger than the charge necessary for fully charging and discharging the output capacitance of all switches in the dead-time. However, Equation (29) assumes that I_Lm,pk is used only to charge or discharge the output capacitance to achieve ZVS during the dead-time, so it is not valid when considering the junction capacitance of the rectifier diode.

Figure 9 shows the equivalent circuit during dead-time. The magnetizing inductor is represented as a current source by assumption. During the dead-time, I_Lm,pk charges or discharges the output capacitances of switches and junction capacitances of rectifier diodes. Therefore, if the dead-time is selected using Equation (29), ZVS cannot be achieved because v_ds is fully discharged. In this paper, a resonant current i_r is used instead of a magnetizing current for accurate dead-time design.

Referring to Figure 3, the resonant current during dead-time can be approximated as

$$i_r\left(t\right)\approx f\left(t\right)={i^{\prime }}_r\left(t_2\right)\left(t-t_2\right)+i_r\left(t_2\right)$$

(30)

where

$${i^{\prime }}_r\left(t_2\right)=\frac{V_c{\omega }_{r3}}{Z_3}=\frac{V_c}{L_r}<0$$

(31)

$$i_r\left(t_2\right)=I_{Lm,pk}.$$

(32)

Because charge Q_ir supplied by the resonant current is equal to the area below i_r(t) during the dead-time, it is obtained as

$$Q_{ir}=\frac{t_{dead}}{2}\left[I_{Lm,pk}+\left\{\frac{V_c}{L_r}{t}_{dead}+I_{Lm,pk}\right\}\right]=t_{dead}\left(I_{Lm,pk}+\frac{V_c}{2L_r}{t}_{dead}\right)$$

(33)

Assuming that C_oss1–C_oss8 are equal, using Equations (29) and (33), the dead-time constraint for achieving ZVS is derived as follows:

$$\frac{V_c}{2L_r}{\left(t_{dead}\right)}^2+I_{Lm,pk}{t}_{dead}\ge \frac{C_{oss1}{V}_{in}}{2}.$$

(34)

Using Equation (31), the lower limit of t_dead is obtained as

$$t_{dead}\ge -\frac{L_r{I}_{Lm,pk}{}_c}{V_c}\left\{1+\sqrt{1+\frac{V_c{V}_{in}{C}_{oss1}}{L_r{\left(I_{Lm,pk}\right)}^2}}\right\}.$$

(35)

Using Equation (35), it is possible to calculate the ZVS condition taking into account C_j. However, Equation (32) does not consider the parasitic capacitance tolerance at all. When the parasitic capacitances of individual switches are different, the lowest dead-time limit to achieve both ZVS and voltage balance is obtained as follows

$$t_{dead,i}\ge -\frac{L_r{I}_{Lm,pk}{}_c}{V_c}\left\{1+\sqrt{1+\frac{2V_c{V}_{in}{C}_{oss,tot}}{L_r{\left(I_{Lm,pk}\right)}^2}}\right\}+t_{comp,i}$$

(36)

where t_dead,i is the dead-time of switch Q_i, C_oss,tot is the sum of C_oss1–C_oss8, and t_comp,i is the gate signal compensation time of switch Q_i calculated using Equation (25).

The other constraint for achieving ZVS is related to turn-on switching. If the dead-time selected is too long and the direction of i_r is changed before the gate signal is applied, ZVS cannot be achieved. When i_r changes direction, the output capacitor being charged begins to discharge and vice versa. The ZVS constraint reflecting the above phenomenon is expressed as follows:

$$i_r\left(t_5\right)=i_r\left(t_4\right)\cos {\omega }_{r1}\left(t_{dead}+t_2-t_4\right)+\frac{V_e}{Z_1}\sin {\omega }_{r1}\left(t_{dead}+t_2-t_4\right)\ge 0.$$

(37)

Using Equation (37), the dead-time constraint is derived as follows

$$t_{dead}\le \frac{\arctan \varphi }{{\omega }_{r1}}+t_{low,lim}$$

(38)

where

$$\varphi =-\frac{Z_1{i}_r\left(t_4\right)}{V_e}$$

(39)

$$t_{low,lim}=-\frac{L_r{I}_{Lm,pk}}{V_c}\left\{1+\sqrt{1+\frac{2V_c{V}_{in}{C}_{oss,tot}}{L_r{\left(I_{Lm,pk}\right)}^2}}\right\}.$$

(40)

Using Equations (36) and (38), the dead-time range to achieve both ZVS and voltage balance is derived as follows:

$$t_{low,lim}+t_{comp,i}\le t_{dead}\le \frac{\arctan \varphi }{{\omega }_{r1}}+t_{low,lim}.$$

(41)

6. Experimental Results

To verify the effectiveness of the proposed switching scheme, a series-connected SiC-MOSFET LLC resonant converter was implemented as shown in Figure 10. The equivalent circuit is shown in Figure 2 and the design parameters are listed in

Table 1. Component parameters of the test setup.

Symbol	Quantity	Value (Unit)
Vin	Input voltage	600–800 (V)
fr1	Resonant frequency	100 (kHz)
fs	Switching frequency	86.6 (kHz)
Lm	Magnetizing inductor	873 (μH)
Lr	Resonant inductor	135 (μH)
Cr	Resonant capacitor	11 (nF)
np:ns1:ns2	Transformer turns ratio	44:8:8

. A Rohm 1.2 kV SiC MOSFET (SCH2080KE) was used for the series-connected switches and gate signals were generated by a Texas Instruments TMS320F28377D DSP board.

Figure 11 shows the drain-source voltage waveforms of the upper switches Q₁–Q₄ under different input voltage conditions. As discussed in Section 3, input and output capacitance tolerance causes a voltage imbalance between series-connected switches. Switch Q₄, which has the smallest parasitic capacitance, blocks higher voltage when compared to the other switches. V_ds4 blocks 34.5%, 35%, and 37% of V_in at input voltages of 600 V, 700 V, and 800 V, respectively.

Figure 12 shows the drain-source voltage waveforms of the upper switches when the proposed switching scheme is applied. Voltage imbalance is solved by turning off switches with a large parasitic capacitance in sequence. The gate signal compensation time is calculated using Equations (25) and (41).

Figure 13 compares the drain-source voltage of series-connected switches at different input voltages. Approximately 35% of the input voltage is applied to switch Q₄. Therefore, this switch has a risk of overvoltage breakdown. However, after using the proposed scheme, approximately 25 % of the input voltage is applied to switch Q₄. In addition, voltage imbalance between the series-connected switches is also significantly reduced.

Figure 14 shows the maximum voltage imbalance between the series-connected switches. Parasitic capacitance tolerances cause a voltage imbalance of 101–158 V. However, after applying the proposed method, the maximum voltage imbalance reduced by 90% to 12–15 V.

7. Conclusions

This paper proposes a switching scheme to overcome voltage imbalance in series-connected SiC MOSFET LLC resonant converter. The proposed method eliminates voltage imbalance by sequentially turning off switches with a large parasitic capacitance. Furthermore, we analyzed the effect of parasitic capacitance on voltage imbalance in detail. The procedure for calculating the gate signal compensation time was provided. In addition, to achieve both voltage balance and ZVS turn-on, dead-time design constraints were derived. In order to verify the effectiveness of the proposed method, experimental results were presented at various input voltages. Compared to series-connected switches in which the proposed method was not applied, voltage imbalance reduced by 91% at 800 V after applying the proposed method.