Advances in Ultra-High-Speed Transceiver IC

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 May 2024 | Viewed by 226

Special Issue Editors


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Guest Editor
School of Integrated Circuits, Peking University, Beijing 100871, China
Interests: high-speed wireline transceiver; clock & data recovery

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Guest Editor
School of Microelectronics, Xi'an Jiaotong University, Xi'an 710049, China
Interests: CMOS high-speed broad-band communication IC design

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Guest Editor
School of Microelectronics, Southern University of Science and Technology, Shenzhen 518055, China
Interests: high-speed IC designs

Special Issue Information

Dear Colleagues,

The explosive growth of internet traffic and computing power drives the increasing demand for wireline transceiver data rates. In recent years, various transceiver architectures have been proposed to optimize the link performance in emerging applications. DSP-based transceivers demonstrate robust PAM-4 data transmission on high-loss channels, while the analog counterparts achieve better energy efficiency and lower latency. Although differential signaling provides better signal integrity, single-ended signaling achieves higher bandwidth density in memory interfaces and in-package communications. Simultaneously bi-directional signaling is another attractive technique that doubles the data rate by transmitting and receiving data on the same wire in a full-duplex fashion. Because the loss of electrical channels is proportional to the baud rate and transmission distance, optical links have replaced electrical links in long-reach scenarios. Waveguide links eliminate the frequency-dependent loss and are more energy-efficient than optical links. With the continuous increase in the data rate, broadening analog bandwidth, compensating for heavy channel loss and reducing sampling clock jitter while maintaining reasonable power consumption are challenging.

This Special Issue of Electronics aims to report recent advances in ultra-high-speed transceiver IC, including wireline transceivers achieving outstanding performance, circuit innovations, and new design methodology. The topics of interest include, but are not limited to, the following:

  • Backplane transceivers
  • High-speed memory interfaces
  • In-package communications
  • Die-to-die chiplet transceivers
  • Optical links
  • Plastic waveguide links
  • Advanced clock and data recovery
  • Building blocks for transceivers
  • Equalization techniques

Prof. Dr. Weixin Gai
Prof. Dr. Xiaoyan Gui
Prof. Quan Pan
Guest Editors

Manuscript Submission Information

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Keywords

  • Wireline transceiver
  • SerDes
  • Simultaneously bi-directional signaling
  • Single-ended signaling
  • Double data rate (DDR)
  • Four-level pulse amplitude modulation (PAM-4)
  • Clock and data recovery (CDR)
  • Equalizer

Published Papers

This special issue is now open for submission.
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