Analog Circuits and Analog Computing

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 December 2024 | Viewed by 978

Special Issue Editor


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Guest Editor
1.Institute for Artificial Intelligence, Peking University, Beijing 100871, China
2. School of Integrated Circuits, Peking University, Beijing 100871, China
Interests: analogue matrix computing; neural networks; resistive memory

Special Issue Information

Dear Colleagues,

Recently, we have witnessed a resurgence of analog computing, which is motivated by the strong demand for developing high-throughput and energy-efficient computers for accelerating data-intensive applications in the post-Moore era. It is also the result of the continuous interest in exploring unconventional computing paradigms, which is fueled by today’s advanced CMOS technology and emerging resistive memory concepts. Analog circuits inherently demonstrate immense computing parallelism, which endows analog computing with fast speed and low computational complexity. There have been widespread investments into analog computing, by using conventional or novel hardware technologies that concern computational acceleration or fusing memory and computing, in order to seek for computer performance breakthroughs in applications such as scientific computing and artificial intelligence. It is highly promising that analog computing in modern times will be substantially different from its past versions, and its development should make a key contribution to the sustainable development of the computer industry.

In this framework, the aim of this Special Issue is to attract reviews and original research outcomes related to the design of analog circuits and their applications to analog computing.

The topics of interest for this Special Issue include but are not limited to:

  • CMOS analog circuits for solving differential equations or linear algebraic problems;
  • CMOS analog circuits for neuromorphic computing and engineering;
  • Analog computing with emerging resistive memory for implementing logic gates, performing matrix operations, or emulating synapse/neuron functions;
  • In-memory computing using analog physical laws, with SRAM, DRAM, or nonvolatile resistive memory devices;
  • Addressing noise and accuracy issues of analog computing;
  • Analog–digital hybrid architectures for high-precision analog computing.

Prof. Dr. Zhong Sun
Guest Editor

Manuscript Submission Information

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Keywords

  • analog computing
  • analog CMOS
  • resistive memory
  • neuromorphic
  • in-memory computing

Published Papers (1 paper)

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Research

16 pages, 5014 KiB  
Article
A First-Order Noise-Shaping SAR ADC with PVT-Insensitive Closed-Loop Dynamic Amplifier and Two CDACs
by Jaehyeon Nam, Youngha Hwang, Junhyung Kim, Jiwoo Kim and Sang-Gyu Park
Electronics 2024, 13(9), 1758; https://doi.org/10.3390/electronics13091758 - 2 May 2024
Viewed by 488
Abstract
This paper presents a first-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, (supply) voltage, and temperature (PVT)-insensitive closed-loop integrator and data-weighted averaging (DWA). The use of a cascode floating inverter amplifier (FIA)-type dynamic amplifier with high gain enables [...] Read more.
This paper presents a first-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, (supply) voltage, and temperature (PVT)-insensitive closed-loop integrator and data-weighted averaging (DWA). The use of a cascode floating inverter amplifier (FIA)-type dynamic amplifier with high gain enables an aggressive noise transfer function while minimizing the power consumption associated with the use of an active filter. In the proposed ADC, the residue is generated by a capacitive digital-to-analog converter (CDAC) employing DWA, which is made possible by employing a second CDAC, which operates after the SAR operation is completed. The proposed ADC is designed with a 28 nm CMOS process with 1 V power supply. The simulation results show that the ADC achieves the SNDR of 71.2 dB and power consumption of 228 μW when operated with a sampling rate of 80 MS/s and oversampling ratio (OSR) of 10. The Schreier figure-of-merit (FoM) is 173.6 dB, and Walden FoM is 9.6 fJ/conversion-step. Full article
(This article belongs to the Special Issue Analog Circuits and Analog Computing)
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