Reduction of DC Capacitor Size in Three-Phase Input/Single-Phase Output Power Cells of Multi-Cell Converters through Resonant and Predictive Control: A Characterization of Its Impact on the Operating Region

Abstract

Cascaded H-bridge drives require using a significant-size capacitor on each cell to deal with the oscillatory power generated by the H-bridge inverter in the DC-link. This results in a bulky cell with reduced reliability due to the circulating second harmonic current through the DC-link capacitors. In this article, a control strategy based on a finite control set model predictive control and a proportional-resonant controller is proposed to compensate for the oscillatory power required by the H-bridge inverter through the cell’s input rectifier. With the proposed strategy, a DC-link second harmonic free operation is achieved, allowing for the possibility of reducing the capacitor size and, in consequence, the cell dimensions. The feasibility of the proposed control scheme is verified by experimental results in one cell of a cascade H-bridge inverter achieving an operation with a capacitance 141 times smaller than required by conventional control approaches for the same voltage ripple.

1. Introduction

Industrialization has required increasingly higher power levels for applications that use power converters [1,2]. Multilevel topologies have emerged as a solution for medium-voltage applications where available power semiconductors have limited voltage and current ratings [3]. This has enabled the assembly of medium to high-power topologies using low-voltage/current semiconductors [4]. Among them, the cascade H-bridge multilevel inverter (CHB) stands out by its simplicity, reliability, and scalability [5,6]. The topology allows increasing the voltage/power level by stacking cells in series that are based on H-bridge inverters such as [7]. Despite its advantages, the main drawback of the topology is its size, due to (i) the DC-link capacitor present in every cell and (ii) the bulky multi-pulse transformer required to feed the cells [8].

The first factor directly depends on the criteria used to design the DC-link capacitor bank to achieve correct operation of the inverter. Two typical criteria for sizing the DC-link capacitor are the admissible ripple and the required ride-through capability [9,10,11,12,13,14,15,16]. Generally, the DC-link capacitor is selected to satisfy both conditions. Nevertheless, simultaneously considering them often results in an oversized capacitor that increases the cost and size of the topology. If either one of these requirements (or both) could be lowered, a smaller capacitor bank size could be used for the desired application. A useful strategy to lower the capacitor ripple requirement, thus enabling the reduction of the capacitor size and extending its service life, is to decrease the harmonic current circulating through it [17,18,19]. Certainly, there are cases where reducing the capacitor size to achieve a less bulky cell is not an option, e.g., when ride-through capability is required. However, even in this case, reducing the harmonic current can ease the design constraints and be used to extend the capacitor’s service life, rather than reducing the cell size.

Along these lines, several methods have been proposed in the literature to reduce the size of the capacitor when ride-through is not critical. In Perez et al. [19], this reduction is achieved by forcing the instantaneous input power to the cell to be equal to the load’s instantaneous power. To implement this strategy, the typical diode rectifier of the cascade H-bridge inverter (CHB) cell is replaced with an active front-end rectifier using a cascade voltage-current loop based on proportional-integral (PI) controllers. However, the results show that the ripple reduction achieved is around 50%, limited by the poor bandwidth of the PI controllers, which do not allow for appropriate tracking of the harmonic reference currents. To avoid the aforementioned bandwidth issues and simplify controller design, Ramirez et al. [20] proposed using a finite control set model predictive controller (FCS-MPC) to track the required current reference. Simulation results demonstrate a significant reduction of the second harmonic ripple on the DC capacitor, regardless of the load operating conditions. However, no experimental results are provided that validate the proposal. In addition, no comprehensive analysis is provided on how the operating region of the converter is modified.

Both [19,20] assume the availability of instantaneous output power to calculate the reference current of the feedforward term. However, in a typical induction motor control system, such as scalar control [21], the current and power angle of the motor, which are required for power estimation, are not commonly available. Yang et al. [22] proposed another approach for achieving high ripple reduction without requiring extra sensors to measure the load variables. This approach uses a double-loop control scheme to regulate the fundamental and harmonic components separately. The harmonic loop includes a resonant controller tuned to twice the output frequency, which reduces the second harmonic in the DC capacitor. This control scheme reduces the DC voltage ripple by 41% without requiring measuring of the load variables. A similar approach was presented by Zithou et al. [23], in which a control loop is used to generate the current reference to meet the average power requirements, while another loop is used to generate the harmonic current reference for ripple compensation based on an adaptive filter. The results show a 95% reduction in ripple with respect to the average DC voltage and a 25% reduction in capacitance. Although the proposed control shows good performance, the design and computational burden of the controller must be considered.

Previous work has shown that mitigating ripple in the capacitor voltage requires sub- and inter-harmonics in the input currents to the cells, depending on the load frequency. To achieve this operating condition, the diode rectifier must be replaced by an active front-end rectifier (AFE) to provide the oscillating power required by the H-bridge inverter through an appropriate control scheme. The rectifier must have a high-bandwidth controller to ensure the tracking of the harmonic current references. However, a high bandwidth controller for the rectifier’s input current does not guarantee the mitigation of the second harmonic. It is also necessary for the DC-voltage controller to generate the appropriate current references that enable the achievement of a DC-link voltage without a second harmonic.

To meet the requirements, this paper proposes using a cascade control scheme where a proportional-resonant controller is employed for the voltage outer control loop, and a finite control set model predictive control (FCS-MPC) controller is used for the inner current loop. The proposed controller has a high bandwidth that enables fast tracking of the non-sinusoidal reference currents, with better performance than the PI regulators previously proposed in the literature [19], without requiring a complex tuning process or a modulation stage [24,25]. Indeed, among high bandwidth controllers for power converters, predictive control strategies have been in high development during at least the past ten years due to the increase in hardware capability that allows the implementation of elaborate algorithms with a high computational burden [26,27,28,29,30]. In particular, the FCS-MPC strategy stands out by its simple and intuitive implementation [31] and the continuous research for new solutions that allow improving characteristics related to parameter mismatch [32,33,34], switching frequency [35,36], harmonic spectra [31,37,38,39,40], and steady-state error [41,42,43], among others. Thus, FCS-MPC results in an attractive strategy to be considered for power converters applications and has been selected in this paper to be used in the mitigation of the second harmonic in the CHB converter’s capacitor bank. Furthermore, a comprehensive analysis of the effects of the compensation on the operating region of the converter is included, which has not been previously reported in the literature.

The major contributions of this work are (i) the presentation of the mathematical model of a cell from CHB converter operating with a reduced second harmonic and (ii) the proposal and experimental validation of a simple control strategy based on a cascade control scheme using linear controllers for the voltage control and FCS-MPC for the required current control. To test this strategy experimentally under different load conditions, a CHB converter cell is implemented and fed from a programmable power supply. Results show that, using the proposed control scheme, the same ripple achieved with a capacitor of 4 mF can be achieved using a capacitor 141 times smaller.

This paper is organized as follows: Section 2 presents the mathematical model of a CHB cell and the necessary conditions to operate without a second harmonic in the DC capacitor. Section 3 describes the operating region of the cell with reduced ripple in the capacitor. Section 4 outlines the proposed control scheme for oscillating power compensation, and Section 5 presents experimental results that validate the proposed analysis and control scheme. Finally, Section 6 presents the main conclusions of this work.

2. Cell Mathematical Model under Ripple Compensation

To study the second harmonic of the DC voltage and propose a control scheme to mitigate it, the mathematical model of the cells used to build the converter needs to be characterized. Using these equations, the origin of the voltage second-order harmonic and its mitigation through instantaneous power theory can be explained. The subsequent sections will use this model to analyze the operating region of the cells and introduce the control scheme necessary to achieve ripple reduction.

2.1. Cell Mathematical Model

Cascade H-bridge inverters are constructed by connecting single-phase voltage cells in series, as shown in Figure 1a. Each cell comprises a bidirectional rectifier, a DC link capacitor, and a H-bridge inverter, as illustrated in Figure 1b. The rectifier is powered by one of the secondary windings of a multi-pulse transformer through an inductive filter that minimizes the large $\frac{dv}{dt}$ generated by the rectifier’s switched operation. Based on the preceding description, an arbitrary cell of the CHB converter can be characterized by the following equations:

$${\mathbf{v}}_s^{abc}=L_s\frac{d}{dt}{\mathbf{i}}_s^{abc}+R_s{\mathbf{i}}_s^{abc}+{\mathbf{v}}_r^{abc}$$

(1)

$${\left[{\mathbf{s}}_r^{abc}\right]}^T{\mathbf{i}}_s^{abc}=C_{dc}\frac{d}{dt}{v}_{dc}+s_i{i}_o$$

(2)

where ${\mathbf{i}}_s^{abc}={\left[\begin{array}{ccc}{i}_s^a& i_s^b& i_s^c\end{array}\right]}^T$ is the input current to the cell, ${\mathbf{v}}_s^{abc}={\left[\begin{array}{ccc}{v}_s^a& v_s^b& v_s^c\end{array}\right]}^T$ is the input voltage to the cell, ${\mathbf{s}}_r^{abc}={\left[\begin{array}{ccc}{s}_{r,1}& s_{r,3}& s_{r,5}\end{array}\right]}^T$ corresponds to the rectifier gating signal vector, $s_i$ is the inverter switching function, $v_{dc}$ is the DC link voltage, $i_o$ the output load current, $v_o$ the inverter output voltage, and $v_r$ the rectifier AC voltage. Both $v_o$ and $v_r$ can be written as function of the gating signals of their respective converters (see Figure 1b) as:

$$v_o=v_{dc}(s_{i,1}-s_{i,2}),$$

(3)

and

$${\mathbf{v}}_r^{abc}=\frac{v_{dc}}{3}\left[\begin{array}{ccc}2& -1& -1\\ -1& 2& -1\\ -1& -1& 2\end{array}\right]{\mathbf{s}}_r^{abc}.$$

(4)

To obtain an average model of the cell that allows for characterization of its operating region, Equations (1) and (2) can be defined by considering only their fundamental frequencies as:

$$v_o\approx v_{dc}{m}_i,$$

(5)

and

$${\mathbf{v}}_r^{abc}\approx v_{dc}{\mathbf{m}}_r^{abc},$$

(6)

where $m_i$ and ${\mathbf{m}}_r^{abc}$ are the modulation signals of the inverter and rectifier, respectively. Both can be defined as:

$${\mathbf{m}}_r^{abc}=M_r\left[\begin{array}{c}sin({\omega }_{r}t+{\alpha }_r)\\ sin({\omega }_{r}t+{\alpha }_r+\frac{2\pi }{3})\\ sin({\omega }_{r}t+{\alpha }_r+\frac{4\pi }{3})\end{array}\right],$$

(7)

and

$$m_i=M_{i}sin({\omega }_{i}t+{\alpha }_i),$$

(8)

with ${\{M_x,{\omega }_x,{\alpha }_x\}}_{x\in \{r,i\}}$ representing the modulation index, frequency, and phase of the rectifier and inverter, as appropriate.

To simplify the steady state analysis, the resulting average model can be rewritten in a rotating $dq$ coordinate frame that allows achieving continuous signals on steady-state. Considering the coordinate transform:

$$T_{abc-dq}=\sqrt{\frac{2}{3}}\left[\begin{array}{ccc}sin\left({\theta }_s\right)& sin({\theta }_s-\frac{2\pi }{3})& sin({\theta }_s-\frac{4\pi }{3})\\ cos\left({\theta }_s\right)& cos({\theta }_s-\frac{2\pi }{3})& cos({\theta }_s-\frac{4\pi }{3})\\ \frac{1}{\sqrt{2}}& \frac{1}{\sqrt{2}}& \frac{1}{\sqrt{2}}\end{array}\right],$$

(9)

where ${\theta }_s$ represents the cell supply voltage angular position, the equations of the cell are:

$${\mathbf{v}}_s^{dq}=L_s\frac{d}{dt}{\mathbf{i}}_s^{dq}+L_s\mathbf{W}{\mathbf{i}}_s^{dq}+R_s{\mathbf{i}}_s^{dq}+{\mathbf{v}}_r^{dq}$$

(10)

$${\left[{\mathbf{m}}_r^{dq}\right]}^T{\mathbf{i}}_s^{dq}=C_{dc}\frac{d}{dt}{v}_{dc}+m_i{i}_o$$

(11)

with

$$\mathbf{W}=\left[\begin{array}{cc}0& {\omega }_s\\ -{\omega }_s& 0\end{array}\right],$$

(12)

and where ${\mathbf{i}}_s^{dq}={\left[\begin{array}{cc}{i}_s^d& i_s^q\end{array}\right]}^T$, ${\mathbf{v}}_s^{dq}={\left[\begin{array}{cc}{v}_s^d& v_s^q\end{array}\right]}^T$, ${\mathbf{v}}_r^{dq}={\left[\begin{array}{cc}{v}_r^d& v_r^q\end{array}\right]}^T$, ${\mathbf{m}}_r^{dq}={\left[\begin{array}{cc}{m}_r^d& m_r^q\end{array}\right]}^T$ are the cell input current, cell supply voltage, rectifier AC voltage, and rectifier modulating signals in the dq reference frame, respectively.

2.2. DC Voltage Second Harmonic

The second harmonic on the DC capacitor can be derived from the inverter instantaneous output power $p_o$ given by:

$$p_o=v_o{i}_o=\frac{{\left(v_{dc}{M}_i\right)}^2}{Z_m}sin({\omega }_{i}t+{\alpha }_i)sin({\omega }_{i}t+{\alpha }_i+{\alpha }_z)=S_o[cos\left({\alpha }_z\right)-cos(2{\omega }_{i}t+2{\alpha }_i+{\alpha }_z)]$$

(13)

where $Z_m$ and ${\alpha }_z$ are module and the angle of the load impedance, respectively, and $S_o$ the apparent power supplied by the cell:

$$S_o=\frac{v_{dc}^2{M}_i^2}{2Z_m}.$$

(14)

The value of the capacitor can be calculated as a function of the desired ripple $r_{dc}$ at twice the inverter frequency using the capacitor energy expression and the definition of apparent power [23]. This calculation is shown in the following equation, which corresponds to the second harmonic admissible ripple design criterion [20]:

$$C_{dc}=\frac{S_o}{2{\omega }_i{r}_{dc}{v}_{dc}^2}.$$

(15)

The instantaneous output power is composed of (i) a DC component whose value depends on the load active power and (ii) an AC component generated by the output H-bridge converter operation. During normal operation, the input rectifier provides the average power to the load, and the capacitor supplies the second harmonic required by the inverter. However, if the rectifier is used to provide the inverter’s second harmonic, the capacitor is just required to absorb the switching harmonics of each converter, allowing the use of a smaller capacitor resulting in a less bulky cell. Then, the volume of the regenerative CHB system can be greatly reduced, at the same time improving the lifetime and reliability of the converter [23]. However, the final capacitor value could depend on other criteria, such as ride-through capability. Under this criterion, the resulting capacitance could be higher than the second harmonic criterion, depending on the interruption time and load power. In this case, reducing the harmonic current in the capacitor allows extending its service time [44,45].

2.3. Primary and Secondary Current under Second Harmonic Mitigation

From pq power theory [46], the active and reactive instantaneous power can be written as functions of the rectifier’s input currents in the dq reference frame as:

$$\left[\begin{array}{c}{p}_s\\ q_s\end{array}\right]=\left[\begin{array}{cc}{v}_s^d& v_s^q\\ -v_s^q& v_s^d\end{array}\right]\left[\begin{array}{c}{i}_s^d\\ i_s^q\end{array}\right]$$

(16)

where $p_s$ and $q_s$ are the instantaneous active and reactive power provided by the power supply, respectively. From (16), the input current to the cell corresponds to:

$$\left[\begin{array}{c}{i}_s^d\\ i_s^q\end{array}\right]=\frac{1}{{\left(v_s^d\right)}^2+{\left(v_s^q\right)}^2}\left[\begin{array}{cc}{v}_s^d& -v_s^q\\ v_s^q& v_s^d\end{array}\right]\left[\begin{array}{c}{p}_s\\ q_s\end{array}\right].$$

(17)

The instantaneous input power to the cell can be approximated as $p_s$ if losses in the input RL filter are neglected. Thus, by equating the input instantaneous active power to the cell with the load instantaneous active power ($p_s=p_o$), it is possible to determine the required input currents to achieve operation without oscillating power in the DC capacitor as:

$${\mathbf{i}}_s^{abc}=\frac{2}{3V_s^2}{\mathbf{v}}_{\mathbf{s}}^{\mathbf{abc}}\left(p_o\right)=\frac{2}{3V_s^2}{\mathbf{v}}_{\mathbf{s}}^{\mathbf{abc}}\left(v_o{i}_o\right),$$

(18)

where $V_s$ is the cell supply voltage amplitude. From (18), the phase a current is given by:

$$i_s^a=\frac{v_{dc}}{3}\frac{M_i{I}_o}{V_s}\left(cos\left({\alpha }_z\right)sin\left({\theta }_s\right)-\frac{1}{2}(sin({\theta }_s+2{\theta }_i+2{\alpha }_i+{\alpha }_z)+sin({\theta }_s-2{\theta }_i-2{\alpha }_i-{\alpha }_z))\right),$$

(19)

with $I_o$ being the load current amplitude. The rectifier currents have inter- and sub-harmonics that are centered around the fundamental frequency and depend on the load output frequency. However, in a regenerative multi-cell topology, natural harmonic cancellation occurs among the cells that feed different load phases. This is in contrast to a non-regenerative CHB, where the harmonic cancellations occur between the cells connected to the same load phase [19]. This can be confirmed using the converter shown in Figure 2, where each phase uvw of the load is fed by a single cell. The current in the secondary of each cell’s transformer can be expressed as follows:

$$i_{s,u}^a=\frac{v_{dc}}{3}\frac{M_i{I}_o}{V_s}\left(cos\left({\alpha }_z\right)sin\left({\theta }_s\right)-\frac{1}{2}\left(sin({\theta }_s+2{\theta }_i+2{\alpha }_i+{\alpha }_z)+sin({\theta }_s-2{\theta }_i-2{\alpha }_i-{\alpha }_z)\right)\right)$$

(20)

$$i_{s,v}^a=\frac{v_{dc}}{3}\frac{M_i{I}_o}{V_s}\left(cos\left({\alpha }_z\right)sin\left({\theta }_s+\frac{2\pi }{3}\right)-\frac{1}{2}\left(sin({\theta }_s+\frac{2\pi }{3}+2{\theta }_i+2{\alpha }_i+{\alpha }_z)+sin({\theta }_s+\frac{2\pi }{3}-2{\theta }_i-2{\alpha }_i-{\alpha }_z)\right)\right)$$

(21)

$$i_{s,w}^a=\frac{v_{dc}}{3}\frac{M_i{I}_o}{V_s}\left(cos\left({\alpha }_z\right)sin\left({\theta }_s+\frac{4\pi }{3}\right)-\frac{1}{2}\left(sin({\theta }_s+\frac{4\pi }{3}+2{\theta }_i+2{\alpha }_i+{\alpha }_z)+sin({\theta }_s+\frac{4\pi }{3}-2{\theta }_i-2{\alpha }_i-{\alpha }_z)\right)\right).$$

(22)

Then, the current in the primary for phase a ($i_p^a$) can be calculated as the sum of (20)–(22), resulting in the following expression:

$$i_p^a=v_{dc}\frac{M_i{I}_o}{V_s}cos\left({\alpha }_z\right)sin\left({\theta }_s\right).$$

(23)

It is evident from (23) that the multi-pulse transformer naturally eliminates the harmonic components necessary for oscillating power compensation.

3. Operating Region of a CHB Cell with Reduced Ripple in the DC Capacitor

As demonstrated in the previous section, operating without a second harmonic in the capacitor voltage implies distorted rectifier input currents that depend on the inverter output frequency. The system model at the fundamental frequency can be used to calculate the modulation signals of the rectifier that enable this operating condition. This information is useful to determine if the system is able to achieve the desired operating point, independently of the control scheme used. Using (1), the modulation signal of the rectifier can be expressed as:

$${\mathbf{m}}_r^{abc}=\frac{1}{V_{dc}}({\mathbf{v}}_s^{abc}-L_s\frac{d}{dt}{\mathbf{i}}_s^{abc}).$$

(24)

By replacing (18) in (24), it is possible to obtain the modulation signal of phase a required to mitigate the ripple in the DC capacitor as follows:

$$m_{r,wc}^a=m_{r,1}^a+m_{r,1+2{\omega }_i}^a+m_{r,1-2{\omega }_i}^a$$

(25)

with

$$m_{r,1}^a=M_{r,1}sin({\theta }_s+\sigma ),$$

(26)

$$m_{r,1+2{\omega }_i}^a=M_{r,1+2{\omega }_i}cos(({\theta }_s+2{\theta }_i)+2{\alpha }_i+{\alpha }_z)$$

(27)

$$m_{r,1-2{\omega }_i}^a=M_{r,1-2{\omega }_i}cos(({\theta }_s-2{\theta }_i)-2{\alpha }_i-{\alpha }_z)$$

(28)

where

$$M_{r,1}=\sqrt{{\left(\frac{V_s}{V_{dc}}\right)}^2+{\left(\frac{L_s{\omega }_s{I}_r}{V_{dc}}cos\left({\alpha }_z\right)\right)}^2},\sigma =atan\left(\frac{L_s{\omega }_s{I}_{r}cos\left({\alpha }_z\right)}{V_s}\right)M_{r,1\pm 2{\omega }_i}=-\frac{L_s{V}_{dc}{M}_i^2}{6Z_m}({\omega }_s\pm 2{\omega }_i),$$

(29)

and $V_{dc}$ is the average value of the DC voltage. The modulation signals for phases b and c are readily obtained by adding the corresponding $\pm \frac{2\pi }{3}$ phase delay to the supply voltage angular position. Equation (25) shows that the fundamental component of the modulation signal, $m_{r,1}$, defines the nominal operating point of the cell, imposing the power factor and DC link voltage, whereas $m_{r,1\pm 2{\omega }_i}$ imposes the required harmonic currents for ripple compensation.

To ensure that the rectifier operates in the linear region, it is necessary that the peak value of the modulator signal be less than or equal to one [20]. From (25), it is possible to calculate the peak value of the modulation signal for the worst-case scenario, where the peak values of the fundamental and harmonic components are in phase. This expression can be written as:

$$|M_{r,1}|+|M_{r,1+2{\omega }_i}|+|M_{r,1-2{\omega }_i}|=1\ge M_{r,p}.$$

(30)

According to (30), the fundamental value of the cell’s operating condition imposes the values of power factor and DC voltage. Thus, the maximum amplitude of harmonic components is defined. For example, if $M_{r,1}$ is equal to 0.8, the sum of inter-sub harmonics cannot be higher than 0.2. This may not be sufficient to compensate for 100% of the capacitor’s second harmonic.

To evaluate the effect of ripple compensation on the load current (output power), the modulators in the $dq$ reference frame must be calculated. These modulation signals are used to estimate the peak load current that the cell can handle while operating with ripple mitigation, without violating the constraints imposed by Equation (30).

3.1. Modulators without Ripple Reduction in dq Reference Frame

The rectifier modulation signals for normal operating conditions without second harmonic reduction on the DC capacitor are represented in the $dq$ reference frame by ${\mathbf{m}}_{r,nc}^{dq}={\left[\begin{array}{cc}m{r,nc}^d& m_{r,nc}^q\end{array}\right]}^T$, where

$$m_{r,nc}^d=\frac{v_s^d}{G_r{V}_{dc}}+\frac{L_s{\omega }_s}{G_r{V}_{dc}}{i}_s^q,$$

(31)

and

$$m_{r,nc}^q=-\frac{L_s{\omega }_s{I}_o{M}_i}{2G_r{v}_s^d}cos\left({\alpha }_z\right).$$

(32)

From (31) and (32), the corresponding amplitude can be determined using

$$M_{r,nc}=\sqrt{\frac{2}{3}}\sqrt{{\left(m_{r,nc}^d\right)}^2+{\left(m_{r,nc}^q\right)}^2}$$

(33)

3.2. Modulators under Ripple Reduction in dq Reference Frame

Similarly to Section 3.1, the modulation signals needed to achieve second harmonic ripple compensation on the $dq$ reference frame are represented by ${\mathbf{m}}_{r,wc}^{dq}={\left[\begin{array}{cc}{m}_{r,wc}^d& m_{r,wc}^q\end{array}\right]}^T$, where:

$$m_{r,wc}^d=m_{r,nc}^d-r_{2nd}\frac{L_s{M}_i{\omega }_i{I}_o}{G_r{v}_s^d}sin(2{\omega }_{i}t+2{\alpha }_i+{\alpha }_z),$$

(34)

and

$$m_{r,wc}^q=m_{r,nc}^q+r_{2nd}\frac{L_s{M}_i{\omega }_s{I}_o}{2G_r{v}_s^d}cos(2{\omega }_{i}t+2{\alpha }_i+{\alpha }_z).$$

(35)

In the previous expressions, $r_{2nd}$ represents the desired percentage of second harmonic ripple in per unit (p.u.). For example, if $r_{2nd}=1$, the cell operates with 100% ripple mitigation, whereas if $r_{2nd}=0$, the cell operates without ripple compensation. Considering the previous equations, the amplitude of the modulation signal for the compensated case, $M_{r,wc}$, can be expressed as:

$$M_{r,wc}=\sqrt{\frac{2}{3}}\sqrt{\frac{3}{2}{M}_{r,nc}^2+\Phi }$$

(36)

with

$$\Phi =\frac{1}{2}(A+B)+2\sqrt{(A{\left(m_{r,nc}^d\right)}^2+B{\left(m_{r,nc}^q\right)}^2)}+\frac{1}{2}|B-A|$$

(37)

and

$$\psi =\frac{r_{2nd}{L}_s{M}_i}{v_s^d},A={\left(\psi {\omega }_i{I}_o\right)}^2,B={\left(\frac{1}{2}\psi {\omega }_s{I}_o\right)}^2.$$

(38)

Equations (36)–(38) explicitly show that the peak value of the modulation signal with compensation for the second harmonic depends on the inverter output current $I_o$. Thus, there are operating points of the inverter that do not allow for reduced ripple on the DC capacitor because this would imply that the rectifier is operating in the non-linear region [46].

3.3. Output Current under Reduced Ripple Compensation

As demonstrated in Equation (36), the peak value of the rectifier modulation signal under ripple compensation depends on the inverter output current, $I_o$. Therefore, it is possible to calculate the maximum output current that can be sustained while keeping the rectifier operating within its linear operation region. This load current can be expressed as a percentage of the maximum load current achieved during normal cell operation by solving the fourth-order standard equation:

$$a{\left(G_{I_o}\right)}^4+b{\left(G_{I_o}\right)}^2+1=0.$$

(39)

In the above equation, $G_{I_o}$ is defined as the maximum load current that the cell can handle while operating without second harmonic in the DC capacitor, expressed as a percentage of the maximum load current achieved during normal cell operation. The values of a and b are defined as:

$$a={\left(1-{\left(\frac{r_{2nd}}{cos\left({\alpha }_z\right)}\right)}^2\right)}^2,b=-2\left(1+{\left(\frac{r_{2nd}}{cos\left({\alpha }_z\right)}\right)}^2\right)+c,$$

(40)

for ${\omega }_i\le {\omega }_s$ and

$$a={\left(1+4{\left(\frac{{\omega }_i{r}_{2nd}}{{\omega }_{s}cos\left({\alpha }_z\right)}\right)}^2\right)}^2-4{\left(\frac{r_{2nd}}{cos\left({\alpha }_z\right)}\right)}^2,b=-2\left(1+{\left(\frac{2{\omega }_i{r}_{2nd}}{{\omega }_{s}cos\left({\alpha }_z\right)}\right)}^2\right)+c,$$

(41)

for ${\omega }_i>{\omega }_s$. In both cases, the value of c is given by:

$$c=-64\frac{r_{2nd}{\left(m_{r,nc}^d{\omega }_i\right)}^2}{{\psi }^2{\left({\omega }_{s}cos\left({\alpha }_z\right)\right)}^4\left(I_{o,nc}^{max}\right)},$$

(42)

with $I_{o,nc}^{max}$ representing the maximum output current without ripple compensation. This output current for the non-compensated case is calculated replacing (31) and (32) in (33), obtaining:

$$I_{o,nc}^{max}=\frac{2v_s^d}{M_i{\omega }_s{L}_{s}cos\left({\alpha }_z\right)}\sqrt{\frac{3}{2}-\left(\frac{v_s^d}{V_{dc}}+\frac{L_s{\omega }_s{i}_s^q}{\sqrt{3}{v}_s^d}\right)}.$$

(43)

The solution of (39) for a given operating point defines the maximum load current that the cell can handle with reduced ripple. Furthermore, it enables the identification of the variables for which the ratio $G_{I_o}$ is most sensitive. Figure 3 illustrates the variation of $G_{I_o}$ with respect to ${\omega }_i$, $V_{dc}$, $M_i$, and the output power factor, taking into account the following parameters: $L_s=10$ mH, $R_s=0.2 \Omega$, and $v_s^d=22\sqrt{3}$ V and a unity input power factor. Figure 3 shows that the value of $G_{I_o}$ is always less than one, regardless of the values of the variables under study. This means that when the cell operates without second harmonic in the DC capacitor it can handle a lower output current than during normal operation.

Figure 3a presents the variation of $G_{I_o}$ as function of the inverter modulation index and average DC voltage $V_{dc}$. The results show that the value of $G_{I_o}$ is unaffected by changes in the inverter modulation index, in contrast to when the average DC voltage is changed, where a higher value of the capacitor voltage results in a higher value of $G_{I_o}$. According to (31) and (33), the increase in $V_{dc}$ decreases the amplitude of the fundamental component of the rectifier modulation signal, thereby increasing the available range to achieve the required amplitude of the harmonic components as indicated by (30).

Figure 3b shows how the value of $G_{I_o}$ varies in response to changes in the input quadrature current, $i_s^q$. A negative value of the quadrature current, which corresponds to operating with an inductive power factor, allows for an increase in the value of $G_{I_o}$ and, consequently, an increase in the output current capacity of the cell with reduced ripple operation. Just as in the capacitor voltage variation case, a negative $i_s^q$ directly impacts the average value of the modulator component $m_{r,nc}^d$, resulting in a reduction of the modulation signal fundamental component peak value.

Finally, Figure 3c shows how the maximum load current for ripple-free operation on the capacitor voltage, $I_{wc}^{max}$, changes as a function of the output power factor, inverter frequency, and inverter modulation index. As expected, the load current that the cell can handle increases when the modulation index ($M_i$) and the load power factor decrease. This occurs because the power drawn by the load is reduced, decreasing the amplitude of the rectifier’s fundamental component, as shown in (32) and (33).

The results show that harmonic compensation effectively reduces the operating region of the cell. However, they also show that this reduction can be mitigated by increasing the values of the DC voltage and input voltage to the cell. Nevertheless, implementing these solutions would require increasing the rating of the components that make up the cell. Therefore, it is necessary to compare the cost associated with implementing the proposal to the cost savings achieved by using it.

4. Control Scheme for Ripple Mitigation in DC Capacitor

As demonstrated in Section 2.3, to achieve an operation without a second harmonic in the DC-link voltage, the rectifier must provide the oscillating power to the H-bridge. This operating condition requires that input rectifiers’ currents have harmonics depending on the output frequency according to Equation (19). Thus, the current loop for the input rectifier must have a bandwidth high enough to follow the required input harmonic current references. These references could be calculated directly by Equation (18); however, under parameter mismatch, the compensation will not be accurate, and the DC-link ripple will be higher than expected. To avoid this issue, an outer voltage controller can be used to generate the required current references. This controller must ensure that DC voltage does not have a second harmonic. To achieve this condition, the voltage controller must have a high gain at twice the output frequency. In view of the above, the proposed control scheme aims to achieve three objectives: (i) keeping the average DC voltage constant, (ii) ensuring decoupled control of the input quadrature current, and (iii) enabling the input rectifier to provide oscillatory power to the output inverter for capacitor ripple mitigation. To achieve these objectives, a cascade controller is utilized, which includes a proportional-resonant controller for DC voltage regulation and an FCS-MPC current controller for input current tracking.

4.1. Current Loop

The rectifier must have a high-bandwidth controller to ensure the tracking of the harmonic current references required for the compensation of the second harmonic at the DC side. Among them, predictive control has been in development during at least the past ten years. In particular, the FCS-MPC strategy stands out for its desirable characteristics allowing one (i) to reduce the computational burden compared with other model predictive control strategies that require the use of online optimization solvers, (ii) to generate the gating signals to the converter without using a modulation stage [24], and (iii) to provide a fast and intuitive implementation that does not require parameter tuning for the current loop [35].

FCS-MPC uses a discrete system model to calculate the optimal input that achieves the control objectives within a specific prediction horizon [24]. Power converters are systems with finite and discrete numbers of inputs, making it possible to predict the system’s future behavior for each possible input [35].

The discrete model of the system can be derived from (10) using the forward Euler approximation:

$$\frac{d}{dt}x\approx \frac{x(k+1)-x\left(k\right)}{T_s}.$$

(44)

Thus, the discrete model that allows for the prediction of the rectifier’s current behavior is:

$${\mathbf{i}}_s^{dq}(k+1)={\mathbf{A}}_{\mathbf{d}}{\mathbf{i}}_s^{dq}\left(k\right)+{\mathbf{B}}_{\mathbf{d}}({\mathbf{v}}_r^{dq}\left(k\right)-{\mathbf{v}}_s^{dq}\left(k\right)),$$

(45)

where ${\mathbf{A}}_{\mathbf{d}}$ and ${\mathbf{B}}_{\mathbf{d}}$ are defined as:

$${\mathbf{A}}_{\mathbf{d}}=\left[\begin{array}{cc}1-T_s\frac{R_s}{L_s}& T_s{\omega }_s\\ -T_s{\omega }_s& 1-T_s\frac{R_s}{L_s}\end{array}\right],{\mathbf{B}}_{\mathbf{d}}=\left[\begin{array}{cc}\frac{T_s}{L_s}& 0\\ 0& \frac{T_s}{L_s}\end{array}\right].$$

(46)

To find the optimal input, the following quadratic cost function is used:

$$J={({\mathbf{i}}_{s,ref}^{dq}(k+1)-{\mathbf{i}}_s^{dq}(k+1))}^T({\mathbf{i}}_{s,ref}^{dq}(k+1)-{\mathbf{i}}_s^{dq}(k+1)).$$

(47)

In each sampling time, the predictive algorithm evaluates the discrete model (45) for each possible rectifier AC voltage ${\mathbf{v}}_r^{dq}$. There are eight possible values of ${\mathbf{v}}_r^{dq}$, which depend directly on the eight rectifier possible gating signals combinations given by:

$${\mathbf{s}}_r^{abc}=\left\{\begin{array}{c}\left[\begin{array}{c}0\\ 0\\ 0\end{array}\right],\left[\begin{array}{c}0\\ 0\\ 1\end{array}\right],\left[\begin{array}{c}0\\ 1\\ 0\end{array}\right],\left[\begin{array}{c}0\\ 1\\ 1\end{array}\right],\left[\begin{array}{c}1\\ 0\\ 0\end{array}\right],\left[\begin{array}{c}1\\ 0\\ 1\end{array}\right],\left[\begin{array}{c}1\\ 1\\ 0\end{array}\right],\left[\begin{array}{c}1\\ 1\\ 1\end{array}\right]\end{array}\right\}.$$

(48)

The results of each prediction are evaluated using the cost function (47) to calculate the optimal input that will be applied at the next sampling time. Figure 4a shows a flowchart of the implemented predictive controller, which additionally includes delay compensation as described in [35].

4.2. Voltage Loop

The output loop defines the direct current reference for the inner predictive controller. This reference must allow regulating the DC voltage to the desired average value and mitigating the second harmonic ripple generated by the H-bridge inverter operation. To achieve these goals, the following proportional-resonant controller is implemented:

$$h_{eu}\left(z\right)=\frac{1+a_i{z}^{-1}+b_i{z}^{-2}}{1-2cos\left(2{\omega }_i\right)z^{-1}+z^{-2}}+\frac{q_0+q_1{z}^{-1}}{1-z^{-1}},$$

(49)

where $\{a_i,b_i\}$ and $\{q_0,q_1\}$ are the parameters of the resonant and PI controllers, respectively. These values are adjusted through a gain scheduler system according to the inverter output frequency using the design criterion presented in [41].

The tuning of the voltage controller is done considering the discrete-equivalent transfer function:

$$\frac{v_{dc}}{u}=\frac{1}{C_{dc}s}.$$

(50)

This relation between the DC voltage and the output of the PR controller is achieved using the control law,

$$i_{s,ref}^d=\frac{1}{v_s^d}(u{v}_{dc}+p_o-v_s^q{i}_{s,ref}^q).$$

(51)

Figure 4b summarizes the implemented voltage control scheme.

5. Experimental Results

To evaluate the proposed strategy, a prototype cell of a CHB inverter is implemented. A diagram of the experimental set-up is shown in Figure 5. The rectifier and inverter were built using G4BC20UD IGBTs with the parameters shown in

Table 1. Experimental setup parameters.

Parameter	Description	Value
$T_s$	Sampling time	50 $\mathsf{\mu }$s
$f_i$	Inverter modulation frequency	1 kHz
$M_i$	Inverter modulation index	0.35
$V_s$	Cell’s supply voltage	22 ${\mathrm{V}}_{rms}$
$L_s$	Input filter inductance	10 mH
$R_s$	Input filter resistance	0.2 $\Omega$
$L_o$	Load inductance	12 mH
$R_o$	Load resistance	10 $\Omega$
$C_{dc}$	DC capacitor	33 $\mathsf{\mu }$F

. The grid voltage is provided by a California Instruments 4500iL three-phase power supply. The control algorithm is implemented in a TMS320C6713 DSP with a sampling time of 50 $\mathsf{\mu }$s. The voltage controller is tuned to achieve a settling time of 65 ms with zero overshoot. The DC-link capacitor has been designed for a 24% DC-link voltage second harmonic considering an output frequency of 50 Hz. The proposal is evaluated under steady state and dynamic conditions to demonstrate its versatility and validate the mathematical analysis provided by this work.

5.1. Steady-State Performance

The open-loop response of the system without second harmonic compensation is shown in Figure 6a. The rectifier’s gating signals are calculated previously using sine wave pulse width modulation (SPWM) and stored in a look-up table to achieve a DC voltage of 72 V and a unitary displacement factor. The results indicate that the capacitor voltage has an average value of 70 V, with an error of 2 V relative to the desired reference voltage. The capacitor presents a second harmonic voltage ripple with a magnitude of 24.3% of the average DC voltage (Figure 7a), which generates a third harmonic in the rectifier input current, as shown in Figure 7b.

Figure 6b shows the system’s transition from open-loop operation to the proposed compensation strategy. When the compensation is activated, the voltage controller reduces the voltage ripple in 25 ms, however, the rectifier current presents high distortion due to the oscillating power compensation according to (18). The input current before proposal activation has an RMS value of 0.79 A, increasing to 1.23 A when the cell operates with reduced ripple in the capacitor. This result suggests that the cell components rating must be re-evaluated when the cell works with reduced ripple. In this case, it is necessary to evaluate if saving for reducing the capacitor size compensates for the cost of using components with higher ratings.

The steady-state performance of the proposed controller is shown in Figure 6c. The average DC voltage has an error of 0.42% with respect to the voltage reference of 72 V. In addition, the rectifier input current exhibits a third harmonic 2.7 times the one of the non-compensated case, as shown in Figure 7d. The increment in the magnitude of the third harmonic is explained by the operating frequency of the inverter. Indeed, according to (19), when operating at 50 Hz, the rectifier’s currents require harmonics at 150 Hz (3 p.u.) to mitigate the capacitor’s voltage ripple. If the desired output frequency is different, so are the harmonic components required to achieve the compensation. In general, the main harmonic components required are placed at $f_s\pm 2f_o$, where $f_s$ and $f_o$ are the input and output frequencies, respectively. Specifically for the third-order current harmonics, they can flow in the system because they are not in phase; they are phase shifted by 120° from each other. In this case, the third harmonic does not correspond to a zero sequence harmonic.

On the other hand, Figure 6c allows one to confirm the effectiveness of the strategy as the resulting capacitor’s second harmonic magnitude is only 0.3% of the average DC voltage value, as shown in Figure 7c. To achieve this second harmonic magnitude without using the proposed scheme, an oversized capacitor of 4 mF would be required. This value is 121 times higher than the actual capacitor used in the implementation, highlighting the effectiveness of the proposal. Despite the good performance concerning ripple mitigation, the total harmonic distortion (THD) increases by 2.5 times, from 13.5% to 34.4%, due to the sub- and inter-harmonics required for compensation. The high THD observed before activation is attributed to the third harmonic generated by the high voltage second harmonic in the DC voltage. It can be concluded that the distortion in the input currents is the price to pay to achieve the compensation of the voltage ripple. Despite this, it is expected that the achieved THD will be lower than the THD achieved at lower operating output frequencies. In those cases, no harmonic coincides with the fundamental frequency (50 Hz) according to (19), resulting in a more distorted input current to the rectifier.

Figure 8 shows the dq transform of the rectifier’s input currents and their respective references. These waveforms were read from DSP memory using the TMS320C6713 DSK HPI Daughter board along with MATLAB software. The input current has a direct component with a zero frequency and an oscillating component at twice the output frequency. Unlike Equation (18), the current reference does not exhibit a third harmonic when the inverter operates at a frequency of 50 Hz. This discrepancy arises because applying the dq transform results in a shift of 50 Hz in terms of the original waveform frequency. The current reference generated by the voltage controller ensures average power transfer from the supply voltage to the load through the zero frequency component, while its oscillating component enables ripple mitigation in the DC-link capacitor. Regarding the steady-state error of the current loop, the average error is 0.001 A and 0.012 A for the direct and quadrature currents, respectively. These low values enable effective ripple mitigation, consequently reducing the required capacitor size.

Regarding the computational burden of the algorithm, the proposal requires 20 $\mathsf{\mu }$s to run the phase-locked loop algorithm, the frame transforms, lineal control (PR) with non-linear control law, and the FCS-MPC algorithm. The signal acquisition is made using ADS8332 EVM ADC, taking 10 $\mathsf{\mu }$s to acquire five signals, 2 $\mathsf{\mu }$s per signal, corresponding to two input rectifier’s currents, input voltage (one phase), DC-link voltage, and output current. From these results, to extend the strategy, i.e., to a three-phase seven-level CHB [47], three control boards would be necessary (one per phase of the converter) as well as an increase in the sampling time to 100 $\mathsf{\mu }$s. These figures are subject to the use of TMS320C6713 DSP, which is nowadays a legacy control DSP (launched in year 2001); however, if up-to-date control boards based on FPGA, SoC, or ARM processors are used instead, a smaller execution time could be achieved [26,27,48,49]. Moreover, as the proposal is feasible even when implemented in a legacy DSP platform, it should be even more so when an up-to-date control platform is selected.

5.2. Dynamic Performance

The dynamic performance of the proposed solution is evaluated for a series of changes in the cell’s operating conditions. The first change corresponds to a variation of the input displacement factor from 0.72(i) to unity, as shown in Figure 9a. The results show a decoupled response where the capacitor voltage remains nearly constant without an increase in its ripple, despite the changes in current. The voltage controller regulates the voltage change in 18 ms without disturbing the load operation.

The second test performed is shown in Figure 9b and consists of a 35% change in the DC voltage reference from 52 V to 72 V. The quadrature current reference is fixed to achieve a unitary power factor. The results show that the controller can reach the new reference value in 40 ms without overshoot and with a decoupled response concerning the quadrature current. The DC voltage change results in an increase in the capacitor’s ripple, which is compensated in 60 ms. Because the modulation signal of the inverter is constant, the increase in DC voltage leads to an increase in the output current (higher power), resulting in a higher amplitude of the input current.

Finally, Figure 9c shows the response of the system to a 40% step change in the output modulation signal. The voltage controller regulates the DC voltage to maintain its value at 72 V, despite the change in output power. To keep the DC voltage constant, the input current increase its peak value after the change, according to (18), to maintain the input-output cell power equality constant. At the time of the change, there is an increase in the DC voltage ripple, which is reduced in approximately 120 ms. Despite the increase in voltage ripple, its transient value is still lower than that of the uncompensated case.

6. Conclusions

This work has presented a cascade control strategy for reducing the second harmonic present in CHB cells based on three-phase, single-phase active cells. The proposal uses a PR voltage controller in cascade with an FCS-MPC current controller to achieve a high bandwidth that enables tracking of the non-sinusoidal currents required for ripple mitigation. Furthermore, a detailed analysis of the operating region and its dependence on the percentage of ripple reduction is presented. The experimental results obtained from a CHB converter cell show a DC voltage second harmonic of 0.3% with respect to the average DC voltage. To achieve the same percentage of second harmonic on the capacitor voltage without the proposed strategy, the cell would need to be built with a capacitance 121 times higher, resulting in a more costly and bulky cell. Future work will consider: (i) including the percentage of ripple compensation, $R_{2nd}$, in the control scheme to reduce the impact of ripple mitigation on the cell’s operating region and (ii) studying the effect that ripple compensation has in the stress of converter components such as the capacitor and multi-pulse transformer, among others.