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Article

Unlimited Power Division Ratio of Microstrip Balanced-to-Unbalanced Gysel-Type Arbitrary Power Divider

1
School of Information Science and Technology, Dalian Maritime University, Dalian 116026, China
2
Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117583, Singapore
*
Author to whom correspondence should be addressed.
Electronics 2020, 9(7), 1124; https://doi.org/10.3390/electronics9071124
Submission received: 10 June 2020 / Revised: 4 July 2020 / Accepted: 6 July 2020 / Published: 10 July 2020
(This article belongs to the Section Microwave and Wireless Communications)

Abstract

:
A microstrip balanced-to-unbalanced (BTU) Gysel-type arbitrary power divider without the high-impedance transmission-line (TL) section is proposed to eliminate the power division ratio (PDR) limit of the conventional microstrip BTU power dividers. The proposed circuit includes five moderate-impedance TLs having the same characteristic impedance in addition to a grounded resistor. The arbitrary PDR is easily obtained by varying the electrical length of the TLs without changing the characteristic impedances, especially the large PDR, which is difficult to achieve by means of conventional BTU power dividers. When the PDR is ∞, the proposed circuit becomes a balun. The closed-form design equations are derived and discussed. To verify the proposed circuit, three prototypes I, II, and III are designed and fabricated for PDRs of 10 dB, 20 dB, and ∞ dB, respectively. The measured PDRs are in good agreement with the simulations. The measured isolation between the output ports is higher than 31 dB for prototypes I and II. The measured insertion loss of the balun prototype is 0.194 dB. Furthermore, the common-mode suppression of greater than 32 dB and the return loss of higher than 22 dB are obtained for various PDRs.

1. Introduction

Power dividing is widely adopted for various microwave applications such as antenna feeding networks, balanced amplifiers, and mixers [1]. Compared to the Wilkinson power divider, the Gysel-type power divider has the advantage of high power-handling capability because of its grounded resistor to sink the created heat effectively. Besides, the out-of-phase type of power dividers can be used in various circuits such as current bleeding mixers for low noise applications and performance improvement of the balanced circuits [2].
Due to the advantages of good common-mode suppression and high immunity to environmental and device electronic noise, the balanced circuits have been studied, such as balanced filter [3,4,5], balanced power divider [6,7,8], and balanced coupler [9,10,11]. However, for a system with both balanced and unbalanced devices, external baluns are required for the connection between the conventional power divider and balanced circuits, which increase the circuit size. In order to solve this problem, the balanced-to-unbalanced (BTU) power divider is proposed to connect both balanced and unbalanced components. Moreover, the BTU power divider can divide one pair of differential-mode signals into the isolated single-ended ports, and common-mode rejection can also be realized [12,13,14,15,16,17]. The BTU power divider with an arbitrary power division ratio (PDR) is more useful and has the flexibility to divide the power arbitrarily. Thus far, the PDR of the existing microstrip BTU power divider is only controlled by means of the characteristic impedances of the different transmission-line (TL) sections [18,19,20,21,22]. For a large PDR, a high-impedance TL is required. Due to the realizable impedance range of 20–120 Ω for microstrip lines, the maximum PDR of the existing microstrip BTU power divider is 6.8 dB [18].
In this paper, a BTU Gysel-type arbitrary power divider without the high-impedance TL is proposed to eliminate the PDR limit of the conventional microstrip BTU power dividers, along with out-of-phase characteristics at two unbalanced output ports and high power-handling capacity. The proposed circuit includes five moderate-impedance TLs having the same characteristic impedance in addition to a grounded resistor. The arbitrary PDR can be easily obtained by varying the electrical length of the TLs without changing the characteristic impedances. Design formulas are derived, and both the theoretical and experimental results are given and discussed.

2. Circuit Structure and Design Theory

The schematic of the proposed BTU arbitrary power divider is depicted in Figure 1. It is composed of one half-wavelength transmission line (i.e., electrical length of θ1 = 180°), two-section transmission lines with the electrical length θ2, two-section transmission lines with the electrical length θ3, and an isolation resistor R. The isolation resistor is grounded, which makes the created heat sinking of the resistors possible. Besides, all the transmission lines have the same characteristic impedance Z1. The PDR is controlled by means of the electrical lengths of θ2 and θ3. The balanced input port A comprises ports 1 and 4 terminated with Z01, and the output ports 2 and 3 are two unbalanced ports terminated with Z02.

2.1. Analysis of Impedance Matching and Isolation Conditions

To obtain the perfect impedance matching and isolation conditions, the proposed power divider between ports 2 and 3 can be separated into two paths, as shown in Figure 1, and the ABCD matrix of two paths can be obtained as
[ A B C D ] 23 _ Path 1 = [ cos θ 3 j Z 1 sin θ 3 j sin θ 3 / Z 1 cos θ 3 ] [ 1 0 1 / R 1 ] [ cos θ 2 j Z 1 sin θ 2 j sin θ 2 / Z 1 cos θ 2 ] ,
[ A B C D ] 23 _ Path 2 = [ cos θ 2 j Z 1 sin θ 2 j sin θ 2 Z 1 cos θ 2 ] [ 1 0 1 Z 01 1 ] [ cos θ 1 j Z 1 sin θ 1 j sin θ 1 Z 1 cos θ 1 ] [ 1 0 1 Z 01 1 ] [ cos θ 3 j Z 1 sin θ 3 j sin θ 3 Z 1 cos θ 3 ] .
The ABCD parameters of two paths are derived as
A 23 _ Path 1 = cos θ 2 cos θ 3 sin θ 2 sin θ 3 + j Z 1 cos θ 2 sin θ 3 / R ,
B 23 _ Path 1 = Z 1 2 sin θ 2 sin θ 3 / R + j Z 1 cos θ 2 sin θ 3 + j Z 1 cos θ 3 sin θ 2 ,
C 23 _ Path 1 = cos θ 2 cos θ 3 / R + j cos θ 3 sin θ 2 / Z 1 + j cos θ 2 sin θ 3 / Z 1 ,
D 23 _ Path 1 = cos θ 2 cos θ 3 sin θ 2 sin θ 3 + j Z 1 cos θ 3 sin θ 2 / R ,
A 23 _ Path 2 = sin θ 2 sin θ 3 cos θ 2 cos θ 3 j 2 Z 1 cos θ 3 sin θ 2 / Z 01 ,
B 23 _ Path 2 = 2 Z 1 2 sin θ 2 sin θ 3 / Z 01 j Z 1 cos θ 2 sin θ 3 j Z 1 cos θ 3 sin θ 2 ,
C 23 _ Path 2 = 2 cos θ 2 cos θ 3 / Z 01 j cos θ 2 sin θ 3 / Z 1 j cos θ 3 sin θ 2 / Z 1 ,
D 23 _ Path 2 = sin θ 2 sin θ 3 cos θ 2 cos θ 3 j 2 Z 1 cos θ 2 sin θ 3 / Z 01 .
To meet the requirement of perfect isolation (S23 = 0) and perfect matching at output ports (S22 = 0 and S33 = 0), the following relations need to satisfy [22]
B 23 _ Path 1 + B 23 _ Path 2 = 0 ,
Z 02 = B 23 _ Path 1 D 23 _ Path 1 D 23 _ Path 2 = B 23 _ Path 2 D 23 _ Path 2 D 23 _ Path 1 .
By substituting (3b) and (4b) into (5), the following equation is obtained.
2 Z 1 2 sin θ 2 sin θ 3 / Z 01 Z 1 2 sin θ 2 sin θ 3 / R = 0 .
Equation (7) can be simplified as
R = Z 01 / 2 .
By substituting (3b), (3d), (4d) and (8) into (6), the following equation is obtained:
Z 1 2 sin θ 2 sin θ 3 / R + j Z 1 cos θ 2 sin θ 3 + j Z 1 cos θ 3 sin θ 2 = Z 02 ( 2 cos θ 2 cos θ 3 2 sin θ 2 sin θ 3 + j Z 1 cos θ 3 sin θ 2 / R + j Z 1 cos θ 2 sin θ 3 / R )
For simplicity, Z1 and Z02 are set to be equal to R.
Z 1 = Z 02 = R .
Then, the relation between θ2 and θ3 is derived with Equation (9) as
2 cos θ 2 cos θ 3 = sin θ 2 sin θ 3 .
It is obtained from Equation (11) that
tan θ 2 tan θ 3 = 2 .
Thus, the perfect impedance matching and isolation conditions for the proposed power divider are obtained as (8), (10), and (12).

2.2. Analysis of Power Transmission from Input Port to Output Ports

Due to the fact that when the differential port A (combined by ports 1 and 4) is excited, all the input power is transmitted solely to the terminations at ports 2 and 3 [23]. There is no power dissipation in the isolation resistor at the center frequency. The voltage VR (as shown in Figure 1) for the resistor R is zero at the center frequency; therefore, the schematic in Figure 1 is simplified as shown in Figure 2 for the analysis of the power transmission characteristics of the proposed power divider at the center frequency. If the PDR between ports 2 and 3 is k2:1, V2 = −kV3. The voltage relations of the two output branch lines for the differential excitation case (i.e., V4 = −V1) can be obtained by using the ABCD transmission matrix concept as (13).
V 1 = V 2 cos θ 2 + V 2 sin θ 2 cot θ 3 + j V 2 Z 1 sin θ 2 / Z 02 ,
V 4 = V 1 = V 3 cos θ 3 + V 3 sin θ 3 cot θ 2 + j V 3 Z 1 sin θ 3 / Z 02 .
By using the relations of V4 = −V1 and Z1 = Z02, it is obtained as
V 2 cos θ 2 + V 2 sin θ 2 cot θ 3 + j V 2 sin θ 2 = ( V 3 cos θ 3 + V 3 sin θ 3 cot θ 2 + j V 3 sin θ 3 ) .
By equating the real part and imaginary part of (14), the PDR can be derived as
k = V 2 V 3 = sin θ 3 sin θ 2 .
It can be seen from Equation (15) that the PDR of the proposed BTU power divider is only determined by the electrical lengths of the TLs (i.e., θ2 and θ3) when Z1 = Z02 = R = Z01/2.
By substituting (15) into (11), the following equation is obtained:
2 1 sin 2 θ 2 1 k 2 sin 2 θ 2 = k sin 2 θ 2 .
Equation (16) is solved as
sin θ 2 = 4 k 2 + 4 ( 4 k 2 + 4 ) 2 48 k 2 6 k 2 .
Thus, the design equations of the proposed power divider are obtained as (8), (10), (12), and (17).

2.3. S-Parameter Analysis

To derive the standard S-parameter of the proposed circuit, by using the topology shown in Figure 2, the ABCD matrix between ports 1 and 4 can be obtained as
[ A B C D ] 14 = [ 1 0 Y L 1 1 ] [ cos θ 1 j Z 1 sin θ 1 jY 1 sin θ 1 cos θ 1 ] [ 1 0 Y L 2 1 ] ,
where
Y L 1 = Y 1 ( Y 02 j Y 1 cot θ 3 + j Y 1 tan θ 2 ) Y 1 + Y 1 tan θ 2 cot θ 3 + j Y 02 tan θ 2 ,
Y L 2 = Y 1 ( Y 02 j Y 1 cot θ 2 + j Y 1 tan θ 3 ) Y 1 + Y 1 tan θ 3 cot θ 2 + j Y 02 tan θ 3 ,
with Y1 = 1/Z1 and Y02 = 1/Z02.
Substituting (10) into (18) and using (12), the ABCD matrix between ports 1 and 4 is derived as
[ A B C D ] 14 = [ 1 0 Y 1 ( Y 02 j Y 1 cot θ 3 + j Y 1 tan θ 2 ) Y 1 + Y 1 tan θ 2 cot θ 3 + j Y 02 tan θ 2 Y 1 ( Y 02 j Y 1 cot θ 2 + j Y 1 tan θ 3 ) Y 1 + Y 1 tan θ 3 cot θ 2 + j Y 02 tan θ 3 1 ] = [ 1 0 Y 02 ( tan θ 3 j + j 2 ) Y 02 ( tan θ 2 j + j 2 ) tan θ 2 + tan θ 3 + j 2 1 ] = [ 1 0 Y 02 1 ] .
Using the conversion from ABCD matrix to S-parameters, the S-parameters in terms of ports 1 and 4 are obtained with (20) as
[ S 11 S 14 S 41 S 44 ] = [ 1 / 2 1 / 2 1 / 2 1 / 2 ] .
Moreover, when either port 1 or 4 is excited, the two divided waves at ports 2 and 3 are 180° out of phase. To realize the PDR of k2:1 between the output ports, S21 and S31 can be obtained using (13). According to the definition of S-parameters and the use of (15), S21 and S31 are finally simplified as follows,
S 21 = V 2 2 V 1 = k 2 ( 1 k 2 sin 2 θ 2 + k e j θ 2 ) ,
S 31 = V 3 2 V 1 = 1 2 ( 1 k 2 sin 2 θ 2 + k e j θ 2 ) .
Considering the perfect isolation between ports 2 and 3 (Sss23 = 0) and the perfect matching at output ports (Sss22 = 0, Sss33 = 0), as mentioned in Section 2.1, the standard scattering matrix Sstd is derived as
[ S std ] = [ 1 / 2 S 21 S 31 1 / 2 S 21 0 0 S 21 S 31 0 0 S 31 1 / 2 S 21 S 31 1 / 2 ] .
Based on the standard S-parameters (24), the mixed-mode scattering matrix can be obtained as [19]
[ S mm ] = [ S ddAA S dsA 2 S dsA 3 S dcAA S sd 2 A S ss 22 S ss 23 S sc 2 A S sd 3 A S ss 32 S ss 33 S sc 3 A S cdAA S csA 2 S csA 3 S ccAA ] = [ 0 2 S 21 2 S 31 0 2 S 21 0 0 0 2 S 31 0 0 0 0 0 0 1 ] ,
where Ssd denotes differential-mode to single-ended transmission coefficients; Ssc denotes common-mode to single-ended suppression coefficients; Sdd, Scc, and Scd denote differential return loss, common-mode reflection, and differential-mode to common-mode conversion coefficient, respectively; and Sss indicates a single-ended S-parameter.

3. Parameter Analysis

Based on the previous theory analysis, the design parameters of the proposed power divider can be easily calculated. For a given PDR, θ2 and θ3 can be calculated by using (17) and (12), respectively. Figure 3 gives the calculated values of θ2 and θ3 for the different PDRs from 0 to 30 dB when Z1 = Z02 = R = Z01/2. It shows that the PDRs are controlled by means of the electrical lengths of θ2 and θ3. For various PDRs from 0 to 30 dB, θ2 and θ3 are always less than 90°, which implies that the size of the proposed BTU power divider will be less than that of the existing BTU power divider [18,19].
To verify the design Equation (8), (10), (12), and (17), three sets of design parameters are calculated according to the PDRs of 0 dB, 10 dB, and 20 dB. In these three cases, all the electrical parameters of the TLs are the same, except for the values of θ2 and θ3 with Z02 = Z1 = R = 50 Ω, Z01 = 2Z02 = 100 Ω. Two quarter-wavelength impedance transformers are applied for matching Z01 to the standard 50-Ω port, which has the characteristic impedance of 2 Z 02 . The calculated values of θ2 for the PDRs of 0 dB, 10 dB, and 20 dB are 54.74°, 18.18°, and 5.73°, respectively. For the three cases, the values of θ3 are 54.74°, 80.67°, and 87.13°, respectively. The mixed scattering parameters are given in Figure 4. When port A is excited in differential mode, the |Ssd2A| values at f0 in Figure 4a for the three cases are −3.010, −0.414, and −0.043 dB, respectively, and the |Ssd3A| values are −3.010 dB, −10.415 dB, and −20.046 dB, leading to the desired PDRs of 0 dB, 10 dB, and 20 dB. Perfect isolation between ports 2 and 3 and perfect impedance matching at ports 2 and 3 are achieved at f0 for various PDRs, as shown in Figure 4b.
When port A is excited in the common mode, |SccAA| at f0 is always 0 dB, and the transmission parameters of |Scc2A| and |Scc3A| at f0 are all less than −65 dB, implying that no power transfers from the common-mode port A to ports 2 and 3, as shown in Figure 4c. Figure 4d shows that the phase difference between Ssd3A and Ssd2A is constant at 180° for a PDR of 0 dB. As the PDR increases, the out-of-phase bandwidth will decrease.

4. Implementation and Performance

For the verification of the proposed theory, three prototypes I, II, and III are designed with a center frequency of f0 = 1.0 GHz for PDRs of 10 dB, 20 dB, and ∞ dB, respectively. The circuit is implemented on the PTFE/woven-glass substrate with a relative permittivity of 2.65 and a thickness of 1.5 mm.

4.1. Prototype I for a PDR of 10 dB

In this case, the output-port termination impedance Z02 is selected as 50 Ω. According to Section 2, it is determined that Z1 = R = Z02 = 50 Ω, Z01 = 100 Ω, and θ1 = 180°. The values of θ2 and θ3 are calculated by using Equations (12) and (17) as 18.18° and 80.67°, respectively. Using the TL synthesis tool ADS Linecalc, the physical dimensions of TLs are calculated. In order to take account of the distributed inductance effect of via holes for optimal physical dimensions of TLs, final dimensions are obtained by using the HFSS EM simulation. The final dimensions of the prototype I are given in Table 1. As shown in Figure 5, two λ/4 impedance transformers with the width of W1 are used for matching the impedance Z01 of 100-Ω to 50-Ω input-port impedance. The lengths of two λ/4 impedance transformers are L1 and L7, respectively. The width of the branch lines is W2 for the characteristic impedance of Z1 = 50 Ω. Besides, based on the available chip resistors, the grounded resistance R is selected as 51 Ω.
The simulated and measured mixed S-parameters of the proposed 10-dB BTU power divider are shown in Figure 6. At the center frequency of f0 = 1.0 GHz, the measured |Ssd2A|, as shown in Figure 6a, is −0.472 dB and |Ssd3A| is −10.478 dB, meeting the requirement for a PDR of 10 dB. At f0, the measured differential return loss is 24.2 dB, and the fractional bandwidth (FBW) of the return loss better than 10 dB is about 23.4% (from 0.896 GHz to 1.133 GHz). Figure 6b shows that the measured isolation between output ports 2 and 3 at f0 is 38.2 dB, and it is better than 15 dB over 0.842 GHz to 1.203 GHz (35.3%). In Figure 6c, the common-mode reflection |SccAA| is greater than −1 dB from 0.766 GHz to 1.237 GHz (47.0%). The mode conversion coefficient at the balanced port |SdcAA| is less than −15 dB over the entire frequency range of interest. The common-mode suppression is better than 15 dB from 0.869 GHz to 1.092 GHz (22.7%) with a maximum common-mode suppression of 36.5 dB at 0.979 GHz. In Figure 6d, the measured phase difference between output ports 2 and 3 is 180° ± 5° in the frequency range from 0.944 GHz to 1.100 GHz. An excellent out-of-phase characteristic around the center frequency is obtained.

4.2. Prototype II for a PDR of 20 dB

Compared to prototype I, only θ2 and θ3 need to change for a PDR of 20 dB. Using Equations (12) and (17), θ2 and θ3 are calculated and obtained as 5.73° and 87.13°, respectively. The photograph of the fabricated prototype II is shown in Figure 7. The dimensions of the prototype II are given in Table 2.
The simulated and measured mixed S-parameters of the proposed 20-dB BTU power divider are shown in Figure 8. At the center frequency of f0 = 1.0 GHz, the measured |Ssd2A|, as shown in Figure 8a, is −0.233 dB and |Ssd3A| is −20.121 dB; therefore, the measured PDR is 19.89 dB. At f0, the measured differential return loss is 25.1 dB. The return loss is better than 10 dB from 0.891 GHz to 1.090 GHz (a FBW of about 20.0%). Figure 8b shows that the measured isolation between output ports 2 dB and 3 dB at f0 is 31.4 dB, and it is better than 15 dB from 0.817 GHz to 1.157 GHz (34.4%). In Figure 8c, the common-mode suppression is better than 15 dB from 0.894 GHz to 1.109 GHz (21.5%) with a maximum common-mode suppression of 32.5 dB. The mode conversion coefficient at the balanced port is better than 16.5 dB over the entire frequency range from 0.7 GHz to 1.3 GHz. The common-mode reflection |SccAA| is greater than −1 dB from 0.766 GHz to 1.237 GHz (47.0%). In Figure 8d, the measured phase difference between output ports 2 and 3 is 180° ± 5° from 0.98 GHz to 1.10 GHz. The out-of-phase characteristic around f0 is also obtained.

4.3. Prototype III for a PDR of ∞ dB

For a PDR of ∞ dB, the electrical lengths of θ2 and θ3 are 0° and 90°, respectively. Meanwhile, the termination at port 3 and the isolation resistor are in parallel, which could be merged in a single resistor (i.e., R = 50 Ω / 50 Ω). However, the 25-Ω resistors do not exist as discrete components. So, the available chip resistor R = 24 Ω is chosen for use. Then, the proposed BTU power divider becomes a balun, as shown in Figure 9. The dimensions of the fabricated balun are given in Table 3. The simulated and measured mixed S-parameters of the proposed balun (i.e., the prototype III) are shown in Figure 10.
In Figure 10a, the measured |Ssd2A|, |SddAA|, and |Sss22| at f0 are −0.194 dB, −22.1 dB, and −44.7 dB, respectively. The FBW for the measured return loss better than 10 dB is about 24.7% from 0.886 GHz to 1.136 GHz. In Figure 10b, the common-mode suppression is better than 15 dB from 0.840 GHz to 1.156 GHz (31.7%) with a maximum common-mode suppression of 33.6 dB. The measured |SdcAA| is less than −13 dB from 0.7 GHz to 1.3 GHz with a minimum common-mode to differential-mode conversion coefficient of −36.6 dB.

4.4. Performance Comparison

The comparison of the proposed BTU arbitrary power divider with previous works is summarized in Table 4. The PDR of the proposed BTU power divider is considerably larger than that of [18,19,20,21], which is attributed to the proposed configuration without a need for the high-impedance transmission lines (HITL). The cost of the large PDR is the FBW of the proposed BTU power divider less than that of [18,19,21], which is reasonable and acceptable. The size of the proposed BTU power divider is less than that of [18,19,20,21], which is mainly because θ2 and θ3 values are always less than 90° for various PDRs. Furthermore, good common-mode suppression (CMS), high isolation, and large return loss are also obtained for arbitrary PDRs.

5. Conclusions

In this paper, a BTU Gysel-type power divider with arbitrary PDR and out-of-phase characteristics has been presented. It can be easily synthesized with the prescribed PDR. The proposed configuration includes five-section of moderate-impedance TLs, which have the same characteristic impedances but different electrical lengths. The PDR is controlled by the electrical lengths of the TLs, which can avoid the limitation of the high impedance TLs on the PDR. The FBW is 20.0–24.7% for various PDRs. Furthermore, the proposed BTU Gysel-type power divider is also useful for high-power applications.
Further work is required to broaden the bandwidth. Based on the proposed configuration, the research on dual-band BTU arbitrary power divider could be carried out.

Author Contributions

Z.Z., Z.W. and Y.F. contributed to the overall study design, analysis, and writing of the manuscript. S.F., H.L. and Z.N.C. provided technical support and revised the manuscript. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported in part by the National Natural Science Foundation of China under Grant 61871417 and Grant 51809030, in part by the Natural Science Foundation of Liaoning Province under Grant 2019-MS-024 and Grant 2020-MS-127, and in part by the Fundamental Research Funds for the Central Universities under Grant 3132020206 and Grant 3132020207.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. The proposed balanced-to-unbalanced (BTU) arbitrary power divider.
Figure 1. The proposed balanced-to-unbalanced (BTU) arbitrary power divider.
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Figure 2. Transmission part of the proposed BTU arbitrary power divider.
Figure 2. Transmission part of the proposed BTU arbitrary power divider.
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Figure 3. Electrical length versus power division ratio (PDR).
Figure 3. Electrical length versus power division ratio (PDR).
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Figure 4. Mixed scattering parameters for three cases of PDR. (a) Ssd and Sdd. (b) Output ports isolation and return loss. (c) Ssc, Scc, and Sdc. (d) Phase difference between output ports.
Figure 4. Mixed scattering parameters for three cases of PDR. (a) Ssd and Sdd. (b) Output ports isolation and return loss. (c) Ssc, Scc, and Sdc. (d) Phase difference between output ports.
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Figure 5. Photograph of the fabricated 10-dB BTU power divider.
Figure 5. Photograph of the fabricated 10-dB BTU power divider.
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Figure 6. Performances of the proposed 10-dB BTU power divider. (a) |Ssd2A|, |Ssd3A|, and |SddAA|. (b) Output ports isolation and return loss. (c) |SccAA|, |Ssc2A|, |Ssc3A|, and |SdcAA|. (d) Phase difference between the output ports.
Figure 6. Performances of the proposed 10-dB BTU power divider. (a) |Ssd2A|, |Ssd3A|, and |SddAA|. (b) Output ports isolation and return loss. (c) |SccAA|, |Ssc2A|, |Ssc3A|, and |SdcAA|. (d) Phase difference between the output ports.
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Figure 7. Photograph of the fabricated 20-dB BTU power divider.
Figure 7. Photograph of the fabricated 20-dB BTU power divider.
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Figure 8. Performances of the proposed 20-dB BTU power divider. (a) |Ssd2A|, |Ssd3A|, and |SddAA|. (b) Output ports isolation and return loss. (c) |SccAA|, |Ssc2A|, |Ssc3A|, and |SdcAA|. (d) Phase difference between the output ports.
Figure 8. Performances of the proposed 20-dB BTU power divider. (a) |Ssd2A|, |Ssd3A|, and |SddAA|. (b) Output ports isolation and return loss. (c) |SccAA|, |Ssc2A|, |Ssc3A|, and |SdcAA|. (d) Phase difference between the output ports.
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Figure 9. Photograph of the fabricated balun.
Figure 9. Photograph of the fabricated balun.
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Figure 10. Performances of the proposed balun. (a) |Ssd2A|, |Sss22| and |SddAA|. (b) |SccAA|, |Ssc2A|, and |SdcAA|.
Figure 10. Performances of the proposed balun. (a) |Ssd2A|, |Sss22| and |SddAA|. (b) |SccAA|, |Ssc2A|, and |SdcAA|.
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Table 1. Dimensions of the prototype I (unit: mm; referring to Figure 5).
Table 1. Dimensions of the prototype I (unit: mm; referring to Figure 5).
L1L2L3L4L5L6L7W1W2
48.79.0550.011.337.6593.148.72.34.1
Table 2. Dimensions of the prototype II (unit: mm; referring to Figure 7).
Table 2. Dimensions of the prototype II (unit: mm; referring to Figure 7).
L1L2L3L4L5L6L7W1W2
48.72.5551.09.336.985.848.72.34.1
Table 3. Dimensions of the prototype III (unit: mm; referring to Figure 9).
Table 3. Dimensions of the prototype III (unit: mm; referring to Figure 9).
L1L2L3L4L5L6W1W2
53.351.17.037.9115.253.32.34.1
Table 4. Performance comparison.
Table 4. Performance comparison.
Ref.TypePhaseHITLf0 (GHz)PDR (dB)CMS (dB)Isolation (dB)RL (dB)FBW (%)Size
(λg × λg)
[18]BTUOOPNeeded23>20~18~25~430.73 × 0.45
[19]BTUOOPNeeded2534.927.727.7~440.48 × 0.48
[20]UTBIPNeeded23>20>20~22~210.72 × 0.51
[21]UTBIPNeeded2335.441.237.8~370.75 × 0.51
Prototype IBTUOOPNone11036.538.224.223.40.45 × 0.29
Prototype IIBTUOOPNone12032.531.425.120.00.44 × 0.28
Prototype IIIBTUOOPNone133.6-22.124.70.42 × 0.30
UTB: Unbalanced-to-balanced. UTU: Unbalanced-to-unbalanced. OOP: Out-of-phase. IP: In-phase. HITL: High impedance transmission lines. PDR: Power division ratio. CMS: Common mode suppression. RL: Return loss. FBW: Fractional bandwidth.

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MDPI and ACS Style

Zhu, Z.; Wang, Z.; Fu, Y.; Fang, S.; Liu, H.; Chen, Z.N. Unlimited Power Division Ratio of Microstrip Balanced-to-Unbalanced Gysel-Type Arbitrary Power Divider. Electronics 2020, 9, 1124. https://doi.org/10.3390/electronics9071124

AMA Style

Zhu Z, Wang Z, Fu Y, Fang S, Liu H, Chen ZN. Unlimited Power Division Ratio of Microstrip Balanced-to-Unbalanced Gysel-Type Arbitrary Power Divider. Electronics. 2020; 9(7):1124. https://doi.org/10.3390/electronics9071124

Chicago/Turabian Style

Zhu, Zihui, Zhongbao Wang, Ye Fu, Shaojun Fang, Hongmei Liu, and Zhi Ning Chen. 2020. "Unlimited Power Division Ratio of Microstrip Balanced-to-Unbalanced Gysel-Type Arbitrary Power Divider" Electronics 9, no. 7: 1124. https://doi.org/10.3390/electronics9071124

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