Regulated Charge Pumps: A Comparative Study by Means of Verilog-AMS

Abstract

This paper proposes a comparative study of regulation schemes for charge-pump-based voltage generators using behavioral models in Verilog- Analog Mixed Signal (AMS) code. An accurate and simple model of the charge pump is first introduced. It allows reducing the simulation time of complex electronic systems made up by both analog and digital circuits while maintaining a good agreement with transistor-level simulations. Finally, a comprehensive comparative study of the different regulation schemes for charge pumps is reported which allows the designer to choose the most suitable topology for a given application and Charge Pump (CP) operative zone.

1. Introduction

In the incoming scenario of the connected world, emerging applications such as the Internet-of-Things (IoT), the Wireless Sensor Networks (WSNs) and the Wireless Body Networks (WBNs) employ self-powered sensor nodes to gather data and share them with the other nodes [1,2,3]. Systems on a Chip (SoCs), designed for these nodes, integrate several analog and digital electronic circuits targeted to execute a heterogeneous set of tasks. Some of these circuits are used to interface with real world signals and external ICs, such as power and data converters, clock sources, phase locked loops, sensors and actuators. Others, instead, work in multiple voltage/current domains which support several modes, such as standby, low power or reduced clock mode [1].

The interaction between analog and digital blocks needs to be verified to ensure not only correct connectivity of the integrated circuit but also SoC performance within specified requirements. To achieve a proper design of such complex SoCs, robust pre-silicon verification methodologies need to be implemented. The high-level view of the single circuit needs for Analog Mixed Signal (AMS) simulations that target the various features and modes [4,5,6]. Defining and implementing these simulations with good accuracy is a complex task as well as it is, in most cases, computationally intensive.

Looking from the manufacturing point of view, large simulation times could extend the needed time to put the product on the market (Time-to-Market), which is, as is well known, a crucial constraint for any commercial electronic product. For this purpose, to check the various blocks, it is important to evaluate the possible advantage of using a behavioral view rather than a SPICE-type view for all the analog blocks within a SoC [4,5,6,7]. The widely adopted Verilog-AMS is a hardware description language which allows for the behavioral abstraction of the circuits with reduced simulation time and links the verification of analog and digital domains in a coherent framework [5,8].

Among the analog blocks present in a modern SoC, DC-DC converters represent a fundamental sub-system that allows for adapting the input voltage of the overall system to that required by the single blocks. To give an example, the energy-autonomy of the nodes is achieved by scavenging energy from the environment (ambient or body) using different kinds of energy harvesters, such as photovoltaic cells, thermoelectric generators and vibrational sensors [1,9,10,11,12]. Nevertheless, due to the heavy dependence of their output voltage from the operating conditions, these transducers are often unsuitable to directly feed the circuit where they are applied. For this reason, a power management unit (PMU) is mandatory employed to adapt the voltage and power levels with the maximum conversion efficiency.

Figure 1 shows a simplified block diagram of such a PMU for energy-harvesting applications [13,14,15,16,17]. The scheme reported in Figure 1 represents the most general architecture of a PMU for energy-harvesting applications from solar cells or thermoelectric generators. The model adopted in Figure 1 for the energy harvester, made up by a voltage source with an internal resistance in parallel with a capacitor, is suitable, to model PV cells and thermoelectric generators. The circuit is also suitable to model the output of an AC-DC converter (bridge rectifier) connected to a piezoelectric harvester. The input voltage, V_IN, provided by the external harvester, feeds the auxiliary circuitry which is geared toward the cold start of the primary boost converter. The first amount of harvested energy is conveyed to an intermediate accumulation element (capacitor C_INT) and, after its voltage has reached a target value (typically above the transistor threshold voltage), the stored charge is successively used to start-up the primary converter, switching-on the input source and enabling the gate control signals. Such operations are often flanked by a maximum power point tracker (MPPT), which controls the various sub-blocks in order to preserve the maximum power transfer from the source to the load. Finally, the primary converter is locally managed to obtain a precisely stable output voltage or to optimize power consumption in function of the required load current.

The converters (auxiliary and primary) are implemented by using bulk, boost or bulk-boost topologies, which are made-up by energy-storage components (capacitors and/or inductors) and active devices aimed to switch the stored energy from the input source to the load during defined time slots.

Among the converter types, inductor-based converters are mainly suitable for applications requiring power levels typically larger than hundreds of milliwatt [18,19,20]. However, inductive converters usually require external bulky inductors, as they are unsuitable for fully monolithic implementation. On the other hand, as the main advantage of switched-capacitor converters, the full integration on a silicon substrate is allowed thanks to the high storable energy densities of the capacitive components. Thus, when the output voltage is higher than the input one (boost topology), the converters based on Charge Pump (CP) circuits are the most suited and hence are the widest adopted topologies [9,10,18].

Focusing on CP converters and, in particular, the regulated primary boost converter, as highlighted in Figure 1, this paper aims to review their widely adopted regulation schemes and provides a design tool for reducing simulation time and to choose the optimum architecture according to the specific design constraints, which exploit AMS simulations.

The paper is organized as follows. The Section 2 introduces CPs, describing the behavioral model derived and its validation through transistor-level simulations. The Section 3 reports the overview of the regulation schemes. In particular, each of which has been mathematically analyzed to develop the behavioral view and then simulated and analyzed through their behavioral Verilog-A model. The Section 4 reports the regulation schemes’ comparison. Finally, the conclusion and final remarks are included in the Section 5.

2. CPs Behavioral Model

The simplified block scheme of a N-stage CP is shown in Figure 2. In its simplest version, each stage is implemented by a diode (or diode connected transistor) and a capacitor [19]. To get rid of the voltage drop of each diode, a common adopted topology adopts, for each stage, the dual-branch cross-coupled one (also referred in literature as latched CP [20,21]) whose schematic is shown in the red-dashed box of Figure 2.

In this topology, the gate voltage of the MOSFETs is boosted by the clock amplitude during the conduction phase. This allows the voltage drop of the charge transfer switches, which connect capacitors of two adjacent stages, to be nullified. Therefore, each stage can be modeled with a constant on-resistance equal to R. It is worth noting, however, that the same model can be adapted to any other type of switch, such as a sub-threshold diode-connected or bootstrapped MOS transistor, etc. [10,18,22]. Each pumping capacitor of the considered CP topology has a constant value, C/2. Moreover, the two parasitic contributions C_B = βC/2 and C_T = αC/2, being α and β technology-dependent parameters, model the stray capacitances connected to the bottom and top plate of the main capacitor, respectively. The stages are driven by two counterphase clock signals, CK and CKn, having a frequency equal to f, a duty-cycle δ whose range is 0 < δ ≤ 0.5, and an amplitude V_CK, assumed equal to the input voltage V_IN. Finally, CP load is modelled with the pair C_L and R_L, which is fed by the output current I_L.

In literature, CPs are often assumed to operate within a Slow Switching Limit (SSL), and, under this working regime, they have been modelled, both for the transient and the steady-state behavior, by an equivalent RC-circuit [23]. However, voltage, power and area constraints of the modern applications also require sometimes the CP working in Fast Switching Limit (FSL) [24]. Thus, with this in mind, in the following, to develop the Verilog-AMS model, we will consider the CP block scheme model reported in Figure 3, which allows us to take into account a wide operating frequency range (i.e., both SSL and FSL).

In particular, considering the CP model in Figure 3, the ideal power conversion in terms of input voltage, V_IN, multiplication is provided by the transformer and the input conductance, G_IN, models loss at the input and is given by:

$$G_{IN}=\frac{V_{CK}}{V_{IN}}\left(\alpha +\beta \right)\frac{N}{1+\alpha }Cf=\frac{V_{CK}}{V_{IN}}\left(\alpha +\beta \right)N_{eff}Cf$$

(1)

where N_eff is the effective number of stages. In particular, N_eff represents the number of stage, N, reduced by a factor due to the charge partition between the stage capacitance and its top plate parasitic. In other words, N_eff models the power loss due to continuous commutations of the stray capacitances.

By using the switch-resistance model introduced in [24] and the dynamic CP model in [23], we can find the fundamental equations which describe transient, steady-state and power breakdown by means of settling time, output I/V characteristic (V_OUT as function of I_L) and power conversion efficiency, η, respectively expressed by:

$$T_S=R_{CP}\left(C_{CP}+C_L\right)\ln \left(\frac{N_{eff}{V}_{CK}+V_{IN}}{\left(N_{eff}{V}_{CK}+V_{IN}\right)-V_{TARG}}\right)$$

(2)

$$V_{OUT}=\left(N_{eff}{V}_{CK}+V_{IN}\right)-R_{CP}{I}_L$$

(3)

$$\eta =\frac{V_{OUT}{I}_L}{V_{IN}{I}_{IN}}\approx \frac{V_{OUT}{I}_L}{V_{IN}\left[\left(N_{eff}+1\right)I_L+V_{IN}{G}_{IN}\right]}$$

(4)

where V_TARG is the target output voltage, and R_CP and C_CP are the output impedance and self-capacitance of the charge pump, respectively, given by:

$$R_{CP}=\frac{R}{\delta }\left[\frac{f_n}{f}\left(\coth \left(\frac{f_n}{f}\right)+\cosh \left(\frac{f_n}{f}\right)\right)\right]$$

(5a)

$$C_{CP}=\frac{4N^2+3N+2}{12\left(N+1\right)}C\mathrm{for}\mathrm{even}N$$

(5b)

$$C_{CP}=\frac{4N^2-N-2}{12\left(N+1\right)}C\mathrm{for}\mathrm{odd}N$$

(5c)

It is worth noting that, in (5a), the term f_n indicates the natural frequency of the inter-stage charge transferring and its value is equal to [(C + C_T) (R/δ)]⁻¹.

In conclusion, considering the CP block scheme model in Figure 3, the fundamental Equations (1)–(5), by using the Verilog-A code we can derive the behavioral model reported in Figure A1 of the Appendix A. Referring to this code, the electrical current supplied to the pump consists of a term useful for its operation and a term dissipated onto the stray capacitors. The output voltage is evaluated by using (3). Output self-capacitance, C_OUT, and the output resistance, R_OUT, have been accounted for as real functions of the normalized frequency, fn/f, which contains the CP parameters. The amplitude of the clock signal is externally defined by Vck and not set equal to the input signal. In addition, auxiliary parameters are provided by dynamically changing the number of stages (dN), the duty cycle (dduty) and the operative frequency (dF). These last parameters, for the sake of simplicity, are realized through electrical signals. Of course, if a parameter variation is not needed, the corresponding signal can be connected to ground. Moreover, since the number of stages is limited by Nmax, the total capacitance is Nmax C. Additionally, when the charge pump works with a number of stages lower than Nmax, the total capacitance is uniformly distributed along the stages.

It is worth noting that Verilog-A can run on an AMS simulator, but it represents a subset of the Verilog-AMS, which is also able to be compiled/simulated using a transistor level SPICE-like simulator (for example Cadence Spectre). On the other hand, to run a Verilog-AMS code, an AMS simulator is mandatory.

In order to verify the effectiveness of the proposed model, several CPs with a different number of stages have been designed and implemented both at transistor level and by using the Verilog-A model, and then simulated with Spectre. In particular, after setting V_IN = 0.5 V, δ = 0.5, R = 5 kΩ, C = 100 pF, α = 0.01 and β = 0.1, resulting in a natural frequency f_n ≈ 1 MHz, different simulations have been performed for clock frequency values ranging from 10 to 100 MHz. Figure 4a shows the voltage at the output node of a 4- and 8-stages CP with an output capacitance value equal to the total CP capacitance and a 1-MHz clock frequency obtained for the transistor level and the Verilog-A model. Moreover, to show the Verilog-A model accuracy, during any phase (transient and steady-state) and for any condition (load and no-load), a current load of 10 µA was applied only after the CP output voltage reaches its maximum value.

By inspection of Figure 4a, it can be easily observed that the time response of the Verilog-A model very accurately predicts the transistor level simulation, the relative error always being lower than 0.7%. Moreover, Figure 4b,c shows the output resistances of the two CPs as function of the clock frequency and the power efficiency, η, as function of the output current load. In both cases, the effectiveness and accuracy of the Verilog-A model is demonstrated to describe the steady-state and transient behaviors of the CP from slow to fast switching limits and power breakdown.

Simulation results are summarized in

Table 1. Simulation results summary for N = 4 and N = 8.

	View	VOUT,MAX (V)	TS@90% (µs)	PIN (µW)	VOUT @IL = 10 µA (V)	ROUT (kΩ)
4-stages CP	SPICE	2.48	48.1	37.21	1.879	60.1
	Verilog-A	2.48	47.9	36.69	1.872	60.8
	Error%	0.00	0.42	1.4	0.37	1.17
8-stages CP	SPICE	4.46	180.1	66.68	3.351	110.9
	Verilog-A	4.46	179.1	66.38	3.329	113.1
	Error%	0.00	0.56	0.45	0.66	1.98

, it is apparent that also settling time and input power demand are accurately modeled. Finally, a high accuracy is also shown on the maximum output voltage for charge pumps with a different number of stages and assuming various scenarios for the top-plate stray capacitance as depicted in Figure 4d.

The computation times needed to simulate the charge pumps at transistor level and by using the Verilog-A model and considering the same simulation window, t_sim, set twice the time to reach the 90% of the maximum output voltage, are summarized in

Table 2. Computation time comparison.

Case	SPICE		Verilog-A		Max Gain
	@10 kHz	@100 MHz	@10 kHz	@100 MHz
N = 1, CL = 100 pF	34 ms, @tsim = 1 ms	3.72 s, @tsim = 20 µs	9 ms	9 ms	4 × 105
N = 2, CL = 200 pF	127 ms, @tsim = 5.8 ms	8.45 s, @tsim = 88 µs	9 ms	9 ms	9 × 105
N = 3, CL = 300 pF	318 ms, @tsim = 16.5 ms	21.5 s, @tsim = 0.2 ms	9 ms	9 ms	2.4 × 106
N = 4, CL = 400 pF	646.9 ms, @tsim = 35 ms	45.6 s, @tsim = 0.4 ms	10 ms	10 ms	4.6 × 106
N = 5, CL = 500 pF	1.21 s, @tsim = 63.4 ms	77.52 s, @tsim = 0.8 ms	10 ms	10 ms	7.8 × 106
N = 6, CL = 600 pF	1.98 s, @tsim = 104 ms	129 s, @tsim = 1.2 ms	10 ms	10 ms	1.29 × 107
N = 7, CL = 700 pF	3.14 s, @tsim = 158 ms	188.22 s, @tsim = 1.8 ms	10 ms	10 ms	1.88 × 107
N = 8, CL = 800 pF	4.58 s, @tsim = 231 ms	287.8 s, @tsim = 2.6 ms	10 ms	10 ms	2.88 × 107
N = 9, CL = 900 pF	6.4 s, @tsim = 315 ms	374.1 s, @tsim = 3.5 ms	10 ms	11 ms	3.4 × 107
N = 10, CL =1000 pF	8.92 s, @tsim = 427 ms	514.6 s, @tsim = 4.7 ms	10 ms	10 ms	5.15 × 107

. Of course, as expected, the proposed behavioral model is more efficient. Indeed, the gain, defined as the ratio between the computation time of the Verilog-A model over that of the SPICE model, ranges from 0.4 × 10⁶ up to 51.5 × 10⁶.

3. Regulation Techniques for Charge Pumps

The voltage at the output of the CP must be regulated in order to set a stable output voltage with constraints imposed by the load. Such constraints depend on the specific application and the supplied circuit type (i.e., purely capacitive, purely resistive or mixed). As an example, in non-volatile memory applications, such as NOR Flash and, more recently, 3D NAND memories [25,26], CP circuits are used to provide operation voltages for a single or multiple word lines (WLs), which exhibit a purely capacitive behavior. For these CPs, the main design specs are settling time and voltage conversion efficiency (VCE). VCE is defined as the ratio between the actual and the ideal output voltage. On the other hand, in energy-autonomous wireless nodes, the equipped sockets, such as sensors, actuators, communication and data-storage sub-systems, consume both static and dynamic power. In these contexts, the load is both capacitive and resistive and an efficient managing of the gathered energy assumes the primary importance. Consequently, power conversion efficiency constitutes the main constraint for these CPs [10,11,22]. Finally, in the CP used in the cold-start of energy-harvesting circuits based on thermoelectric generators, the load is both capacitive and resistive but the main specifications are VCE and settling time [13,15,16,17].

Ideally, in a conventional regulated N-stages CP, the output voltage can be adjusted from V_IN to (N + 1) V_IN by changing one or more CP parameters according to the reference voltage, V_TARG. Based on the parameter on which they act, regulation schemes could be classified into:

• Adaptive schemes;
• Output resistance modulation schemes;
• Clock amplitude modulation schemes.

In particular, in the adaptive schemes, the stages are rearranged to allow for different CP voltage levels or works within the maximum power efficiency zone at the defined output voltage. In the output resistance modulation schemes, to adapt the CP output resistance to the load, the clock frequency or the duty cycle are changed, thus achieving a target output power or maintaining the maximum power transfer. In the clock amplitude modulation schemes, it is adjusted the clock amplitude, V_CK, (i.e., providing it different from the input voltage, V_IN) in order to reduce switching power losses or to speed-up the output transient response.

Each of these techniques are briefly discussed and analytically described in the following.

3.1. Regulation Scheme Based on the Adaptive Number of Stages

Adaptive schemes are mainly adopted in applications where the various system sub-blocks need to be supplied with a wide-range voltage. The on-chip voltage generator can be implemented by a cascade of CPs, extremely reduced to a single stage, where each single stage is turned on/off, or rearranged to generate different voltage levels, maintaining high performances for the overall system (e.g., settling time or power efficiency).

Adaptive schemes proposed in literature can be classified into two different categories, namely open-loop and closed-loop schemes. In the first one, the number of stages is set by an external device, such as a DSP or a µ-controller, in order to modify the level of the output voltage in un-regulated mode or to speed-up the transient behavior (Figure 5a) [27,28]. On the other hand, in closed-loop schemes, a block that searches for the optimum number of stages is exploited to adapt the number of active stages with the actual voltage gain, in order to optimize the whole system efficiency (Figure 5b) [29,30]. In the latter scheme, which is the widest adopted one, the generator often includes a further control feedback loop to set the output voltage at a reference voltage.

The number of stages is an integer number higher than unity; hence, only a discrete set of output voltages can be generated, as shown by the staircase plot in Figure 6a. In literature, several papers deal with this topic and introduce design strategies with the aim of evaluating the optimum number of stages, N_OPT, under the silicon area [28,31]. In particular, in case we have a pure capacitive load, the optimum number of stages that minimize the settling time was analytical derived in [28], and its value is given by (Note that the value expressed by (6) must be rounded to the nearest integer.)

$$N_{OPT}\approx \frac{4}{3}\left(1+\alpha \right)\left(k-1\right)$$

(6)

where k = V_OUT/V_IN is the CP voltage gain. Since N_OPT, expressed by (6), is greater than the minimum number of stages (i.e., N_min = (1 + α) (k − 1)), a possible implementation of the adaptive approach could be based on the adoption of a double-state charge pump, where the number N is commuted between N_Opt and N_min, to speed-up transient behavior [28]. Moreover, another possible adaptive approach application can be represented by an implementation to generate a finite set of output voltages composed by (i + 1)V_IN with i = 1, 2, 3, …, N [27].

Considering power-starved applications, the optimization strategy is focused on maximizing power efficiency. At this purpose, the CP must work between the SSL and the FSL, where the output CP resistance can be assumed to be equal to N_eff/fC [32]. And, in order to generate the reference output voltage, such value must be set according to:

$$\frac{N_{eff}}{fC}=\frac{\left(N_{eff}+1\right)V_{IN}-V_{OUT}}{I_L}$$

(7)

Substituting (1) and (7) in (4), the power efficiency is expressed as a function of the voltage gain, k = V_OUT/V_IN, as:

$$\eta =\frac{k}{\left[\left(N_{eff}+1\right)+\frac{\left(\alpha +\beta \right){\left(N_{eff}\right)}^2}{\left(N_{eff}+1\right)-k}\right]}$$

(8)

It is worth nothing that (8) does not depend neither on the output current, nor on the total CP capacitance. Relationship (4) versus the voltage gain for different values of N and β, assuming α = 0, is shown in Figure 6b. By inspecting this figure, it is apparent that the power efficiency reaches its highest values in a limited range of k and it rapidly decreases for higher conversion ratios.

Changing the number of active CP stages, as appear in Figure 7b, we get a right shift on the plot of η, therefore, for a specific k value, it exists an optimal number of stages, which allow the highest efficiency [28] and it is given by:

$$N_{Opt}=\left[\left(1+\sqrt{\frac{\alpha +\beta }{1+\alpha +\beta }}\right)\left(1+\alpha \right)\left(k-1\right)\right]$$

(9)

Starting from this result, wide-output CPs with reconfigurable stages to select the optimal number of active stages to achieve the maximum efficiency at a given voltage gain were proposed in the literature [27,29,33,34]. In particular, the maximum required output voltage sets the maximum number of stages, thus we get N_MAX = (1 + α) (V_OUT,MAX/V_IN − 1).

Considering both plots in Figure 7, a simple but effective strategy can be realized with the use of a thermometer control of the number of stages, setting its value to the integer nearest to (k − 1), and the possibility to rearrange the remaining (N_MAX − k)-stages to increase the pumping capacitance of the single active stage [31]. For this purpose, the plot in Figure 6b suggests that the optimum number of stages, given by (9), should be maintained for the inherent zone, which is delimited by the intersection with the adjacent curves. As an example, if k = 3.5, then N_Opt = 3, and this number must be set for k from a gain k₂₃ to k₃₄ given by the intersection of the η-curves for N = 2 to 3 and N = 3 to 4, as highlighted in Figure 7b. The various gain thresholds, k_i(i+1) with i = 1, 2, …, N − 1, can be calculated by:

$$k_{i\left(i+1\right)}=\left(i+1\right)-\frac{\sqrt{{\left[\left(\alpha +\beta \right)\left(2i+1\right)+1\right]}^2+4\left(\alpha +\beta \right)\left(i^2-1\right)}-\left[\left(\alpha +\beta \right)\left(2i+1\right)+1\right]}{2}$$

(10)

Given the value of the coefficients α and β, the normalized gain threshold can be evaluated and used to implement the optimal N-finder, as done in [33].

As shown in Figure 7a, the transistor-level implementation of the optimal N-finder is made up by a ladder of window comparators, which compares the input weighted values and the output voltage (division factor of the ohmic ladders is set in relationship (10) trough by the gain threshold) and a digital circuit that selects the number of active stages. The Verilog-A description of the adaptive topology, according to Figure 7, is reported in the Appendix A (Figure A2).

The adaptive scheme has been applied on the 8-stage CP presented and analyzed in the previous section, and its Verilog-A model has been simulated using Spectre. In particular, the parameters set in the previous section have been left unchanged, while several simulations have been carried by sweeping the voltage gain, k, from 1 to 6. Gain thresholds k_i(i+1) are automatically calculated by the code as a function of the various parameters, and Figure 7b reports their values for different scenarios.

The simulation results are plotted in Figure 8. In particular, Figure 8a shows the open-loop output voltage varying the number N from 0 to 6. Inspection of the figure allows one to show how, step by step, the dynamic behavior changes, due to the arranging of the pumping capacitance. It also appears that the fastest response is obtained at the minimum output voltage level, whereas the slowest response corresponds to the maximum output voltage level. In Figure 8b, power conversion efficiency versus the voltage gain is reported. The undulating trend curves confirm that the adaptive topology guarantees an efficiency at the highest values for each gain and condition (different values for α and β).

It is worth noting that, although the rearranging strategy is the best solution in terms of area occupation, the pumping capacitance redistribution changes the operative zone of the CP. In fact, the natural frequency, f_n, which is normally independent from the number of stages, becomes proportional to N/N_MAX (i.e., it is a function of N). To give a practical example, the considered CP considered has f_n ≈ 1 MHz when N = N_MAX = 8, while during the adaptive control N could sweeps from 1 to N_MAX and in the worst case (i.e., N = 1) the natural frequency reaches f_n ≈ 125 kHz. For a given clock frequency, such as for example 1 MHz, the CP will work in the FSL zone, and the benefit gained by the rearranging strategy is loss. Two possible solutions to solve this drawback are the operative frequency reduction, or the RC product increase to compensate the decrease of f_n. Unfortunately, the first choice would reduce the current CP capability, while the second one would increase the silicon area occupation.

3.2. Regulation Schemes Based on Output Resistance Modulation

The output resistance modulation is a widely adopted regulation scheme to set the output voltage under different output load condition. This kind of feedback is commonly used in various application fields and, as shown in Figure 9, it is made-up by the N-stage CP, a voltage divider, a voltage comparator and, depending on the controlled parameter (i.e., clock frequency or duty cycle), a Voltage Controlled Oscillator (VCO) [35,36,37,38] or a Pulse Width Modulator (PWM) [39,40].

Focusing on the frequency-based modulation, the clock frequency acts on the CP output impedance to regulate the output voltage and to tune it according to the reference voltage. However, from Equation (5a), as confirmed by the trend of the curves in Figure 4b, the output impedance value can be changed only if the CP works within SSL. This condition limits the maximum operative frequency and, therefore, the regulation range. Anyway, the regulation range can be increased by proper pumping capacitance and CP transistors re-sizing. The remaining limits are given by the minimum and the maximum VCO frequency, f_min and f_MAX, respectively, which define the absolute limits of the regulation range.

Since the regulation acts at the steady state, a proportional control of the CP output resistance can be assumed, and we can write:

$$\frac{N_{eff}}{Cf}=R_{SSL,MAX}\left[1+A_{VCO}\left(k_{VD}{V}_{OUT}-V_{TARG}\right)\right]$$

(11)

where R_SSL,MAX = N_eff/f_minC is the maximum CP output resistance, A_VCO, expressed in (V⁻¹), is the gain of the cascade between OP and VCO and k_VD is the voltage partition coefficient of the voltage divider. Thus, within the control range, the closed-loop function for the output voltage results is as follows:

$$V_{OUT}=\frac{\left[\left(N_{eff}+1\right)V_{IN}-R_{SSL,MAX}{I}_L\right]+\left(A_{VCO}{R}_{SSL,MAX}{I}_L\right)V_{TARG}}{1+k_{VD}\left(A_{VCO}{R}_{SSL,MAX}{I}_L\right)}$$

(12)

and, assuming A_VCO k_VD >> 1, the output voltage in (12) approaches the value V_TARGET/k_VD.

The behavioral model of the control chain is reported in the Appendix A (Figure A3). The variation of the clock frequency is proportional to the difference between the scaled CP output voltage and the reference voltage. Furthermore, frequency range can be set from fmin to fmax. The closed-loop output voltage and the controlled clock frequency of the 8-stage CP regulated with the output resistance modulation in scheme in Figure 9, as a response to an output current and an input voltage variation are depicted in Figure 10. As expected, the output voltage follows the target one with a restrained error expressed as:

$$\epsilon =k_{VD}\frac{1-\left[\left(N_{eff}+1\right)\frac{V_{IN}}{V_{TARG}}-\frac{R_{SSL,MAX}{I}_L}{V_{TARG}}\right]}{1+k_{VD}\left(A_{VCO}{R}_{SSL,MAX}{I}_L\right)}$$

(13)

With the aim of comparing the regulation schemes, two performance parameters commonly adopted for voltage regulators have been considered, namely line and load regulation. In particular, the earlier is defined as the ability of the output voltage to maintain its specified output voltage over changes in the input voltage, and is defined by:

$$LineR=\frac{\partial V_{OUT}}{\partial V_{IN}}=\frac{\left(N_{eff}+1\right)}{1+k_{VD}\left(A_{VCO}{R}_{SSL,MAX}{I}_L\right)}$$

(14)

The load regulation is referred to the output current variation rather than the input voltage variation, and it is defined as:

$$LoadR=\frac{\partial V_{OUT}}{\partial I_L}=R_{SSL,MAX}\frac{A_{VCO}\left[k_{VD}\left(N_{eff}+1\right)V_{IN}-V_{TARG}\right]-1}{{\left[1+k_{VD}\left(A_{VCO}{R}_{SSL,MAX}{I}_L\right)\right]}^2}$$

(15)

Assuming a high gain A_VCO = 1000 V⁻¹ and a partition coefficient k_VD = 0.1, with an output current of 10 µA, the error, line and load regulation are 0.14%, 0.011 and 185.8 Ω, respectively.

Different from the frequency-based type, the duty cycle-based modulation schemes act on the CP output impedance when it works in FSL, where the output impedance value changes as a function of the duty cycle (i.e., R_OUT,FSL = (N_eff + 1) R/δ). This limits the minimum operative frequency, which can be extended by a proper stage components re-sizing. Other limits are due by the minimum and the maximum duty cycle of the pulse width modulator, δ_min > 0 and δ_MAX ≤ 0.5, respectively. Like the frequency-based scheme, a proportional control of the CP output resistance can be assumed, and we can write:

$$\frac{\left(N_{eff}+1\right)R}{\delta }=R_{FSL,MAX}\left[1+A_{PWM}\left(k_{VD}{V}_{OUT}-V_{TARG}\right)\right]$$

(16)

where R_FSL,MAX = (N_eff + 1)R/δ_min is the maximum output resistance offered by the CP in FSL, A_PWM, expressed in (V⁻¹), is the gain of the cascade between OP and PWM, k_VD is the voltage partition of the voltage divider and δ_min is the minimum duty cycle. Within the control range, the closed-loop function for the output voltage is given by:

$$V_{OUT}=\frac{\left[\left(N_{eff}+1\right)V_{IN}-R_{FSL,MAX}{I}_L\right]+\left(A_{PWM}{R}_{FSL,MAX}{I}_L\right)V_{TARG}}{1+k_{VD}\left(A_{PWM}{R}_{FSL,MAX}{I}_L\right)}$$

(17)

which has a similar expression of (12). Again, assuming A_PWM k_VD >> 1, the output voltage in (17) approaches V_TARGET/k_VD.

The behavioral model of the control feedback based on the output resistance modulation this is reported in the Appendix A Figure A4. In particular, by referring to the listed code in Figure A4, the variation of the clock duty cycle is made proportional to the difference between the scaled CP output voltage and the reference voltage. Furthermore, the duty cycle range can be set from δmin to δmax.

The closed-loop output voltage of the whole system has the response to an output load and an input voltage variation shown in Figure 11. As expected, assuming a high gain A_PWM = 1000 V⁻¹, the output voltage follows the target one with a restrained error even lower than 1%, while line and load regulation, valued as given in (14) and (15), respectively, are 0.1 and 1.05 Ω.

3.3. Regulation Schemes Based on Clock Amplitude Modulation

Although rarely adopted, regulation schemes based on clock amplitude modulation offer a good compromise between circuit complexity and overall performances. In these schemes, the amplitude of the clock signals is adjusted to target a specific output voltage. This kind of feedback is made-up at least by the N-stages CP, a voltage divider, a linear comparator and an auxiliary DC-DC converter which, depending on the targeted application, can reduce [41] or boost [42] the input voltage V_IN to feed the buffers that provide the clock signals (Figure 12).

The clock amplitude affects the maximum CP output voltage (i.e., V_OUT,MAX = N_effV_CK + V_IN) and, specifically, it tends to tune the CP output voltage according to the target voltage value. Therefore, the control is apparently independent from the CP working zone, SSL or FSL. However, it is worth nothing that the CP output resistance limits the CP output current capability; therefore, the regulation range could be limited mainly when CP works in the deep-SSL zone. Moreover, by inspection of (1), input current caused by switching losses can be decreased, making V_CK < V_IN [41]; vice-versa, by inspection of (2), a boosting of the clock amplitude with respect to the input voltage (V_CK > V_IN) can lead to a settling time reduction [42]. Since the two action affects the CP performance in an opposite way, for these control schemes’ application, field can be divided into low-power and high-speed applications, for the earlier and the latter approach, respectively.

A linear modulation of the controlled parameter has been assumed within the control range, hence:

$$V_{CK}=V_{IN}{A}_{VM}\left(V_{TARG}-k_{VD}{V}_{OUT}\right)$$

(18)

where A_VM, expressed in (V⁻¹), is the gain of the cascade between comparator and auxiliary DC-DC converter, here re-called voltage modulator, while k_VD is again the voltage partition coefficient of the voltage divider. Closed-loop function for the output voltage is simply expressed by:

$$V_{OUT}=\frac{\left(N_{eff}{A}_{VM}{V}_{TARG}+1\right)V_{IN}-R_{CP}{I}_L}{1+k_{VD}\left(N_{eff}{A}_{VM}{V}_{IN}\right)}$$

(19)

Of course, assuming A_VM k_VD >> 1, we see that the output voltage in (19) approaches that of V_TARGET/k_VD.

The behavioral model of the control chain is reported in Figure A5 of the Appendix A, where clock amplitude variation can be set from Vck_min ≥ 0 to a Vck_max arbitrarily selectable.

The closed-loop output voltage of the system versus the output current and input voltage variations is depicted in Figure 13a,b, for the reduced mode, 0 ≤ V_CK ≤ V_IN, and Figure 13c,d for the boosted mode, V_IN ≤ V_CK ≤ 2V_IN. As expected, for a high gain A_VM k_VD = 100, the output voltage approaches the target one with an average error equal to 0.1%.

Line and load regulation acquire two different expressions for this kind of control, thus:

$$LineR=\frac{\partial V_{OUT}}{\partial V_{IN}}=\frac{N_{eff}{A}_{VM}\left(V_{TARGET}+k_{VD}{R}_{CP}{I}_L\right)+1}{{\left[1+N_{eff}{A}_{VM}{k}_{VD}{V}_{IN}\right]}^2}$$

(20)

$$LoadR=\frac{\partial V_{OUT}}{\partial V_{IN}}=\frac{R_{CP}}{1+N_{eff}{A}_{VM}{k}_{VD}{V}_{IN}}$$

(21)

The numerical values for the simulated case are 0.15 and 112.2 Ω, respectively. As compared to the previous analysed schemes, the number of stages further increases the open-loop gain of the feedback, improving line and load regulations.

4. Comparison

The behavioral models of the regulation schemes treated in the previous section allows to highly reduce the simulation time of this kind of mixed signal systems. Moreover, they provide the designer a way to efficiently analyze and compare different solutions, according to the specific design constraints and applications. For this purpose, Figure 14 shows the power conversion efficiencies of the schemes considered and simulated in the previous sections within their regulation ranges. By inspection of Figure 14, the clock amplitude schemes appear to be most efficient when the system must provide relatively high current levels. On the other hand, the frequency modulation scheme is best suited for lower current levels.

Finally,

Table 3. Comparison between the regulation schemes.

	Scheme	Control Range	Line Reg.	Load Reg.	Working Zone	Typ. Application
N	Adaptive	Depend by primarily feedback			SSL	Low power
ROUT	Frequency	Narrow	<0.1	<200 Ω	SSL	General
	Duty cycle	Middle	>0.1	<2 Ω	FSL	General
VCK	Reducing	Wide	>0.1	<200 Ω	SSL/FSL	Low power
	Boosting	Narrow	>0.1	<200 Ω	SSL/FSL	High speed

summarizes the features of each regulation scheme. A qualitative comparison shows that clock amplitude-based schemes can regulate over the widest control range and for all the operative conditions, vice-versa the commonly adopted frequency-based regulation scheme has a narrow output current range. Additionally, adaptive schemes can be used to minimize the input power consumption of the CP-based voltage regulator.

5. Conclusions

In this paper, a behavioral model for charge pumps operating in a wide-range of frequencies has been developed, adopting the Verilog-AMS language. The proposed Verilog-AMS code describes for the first time in literature a comprehensive model of the charge pump, which takes into account transient and steady-state equivalent parameters changes due to operation conditions (from Slow to Fast Switching Limit) and a complete frame of the power consumption. This study has been proposed with the aim of providing the designer with simulation tools that accurately follow the transistor-level response while allowing a huge reduction of the simulation time. Indeed, the proposed model allows for a huge reduction in the simulation time (about six orders of magnitude) as compared to a transistor-level schematic, while maintaining an excellent accuracy (error below 1%).

The model has been exploited to carry out an in-depth analysis of the main regulation schemes usually adopted in regulated DC-DC converters, providing an exhaustive comparison when the charge pump works into all the operative conditions. This study gives the designer a handy and effective tool to select the best regulation scheme according to the given design parameters. Indeed, by adopting the proposed design methodology, the best circuit architecture can be selected without performing time-consuming transistor-level simulations.