Phase-Shift PWM Converter with Wide Voltage Operation Capability

Abstract

A soft switching three-level pulse-width modulation (PWM) converter is presented for industrial electronics with wide voltage range operation, such as solar power or fuel cell applications. Phase shift PWM scheme is used on the input-side to accomplish the zero voltage turn-on on power switches and improve the converter efficiency. Three-level diode-clamp circuit topology is adopted in the presented circuit to lessen the voltage ratings on active devices for high voltage applications. Three sub-circuits with the different turns-ratio of transformers can be selected in the presented converter in order to achieve 10:1 (V_in,max = 10V_in,min) wide input voltage operation when compared to the conventional multilevel converter. The proposed circuit is a single-stage converter instead of two-stage converter to realize wide voltage operation. Therefore, the presented converter has less component counts. Finally, the design procedure and experiments with a 300W laboratory circuit are presented and discussed to confirm the circuit analysis and converter performance.

1. Introduction

Renewable energy power conversions have been widely developed to improve and overcome the energy shortage and air pollution from fossil fuels. Wind power and solar power are the most attractive energy sources in modern power generation systems. Power electronic techniques are widely used in the wind power and solar power conversion system to provide the stable voltage output. However, the output voltage of solar panels and wind turbine generators is variable with the wide variation, due to the output voltage value, is related to solar intensity or wind speed. The classical two-stage or three-stage converters are usually adopted [1,2,3] to overcome the wide voltage variation problem of solar panels and or wind turbine generators, and also provide the stable output voltage. Unfortunately, the classical two-stage or three-stage circuit topologies have high power losses and low efficiency. The series-parallel connected converters have been presented in [4,5,6,7] to have wide voltage operation. However, the drawbacks of these circuit topologies are many circuit switches and components in these circuit topologies and the circuit reliability and efficiency are reduced. Phase shift pulse-width modulation (PWM) full-bridge or half-bridge converters [8,9,10,11,12] have developed to present zero voltage switching (ZVS) and wide voltage operation. The control scheme is more difficult to be implemented by the general analog integrated circuit. The resonant converters [13,14,15,16,17,18,19] are widely used in the consumer power supplies for their advantages of low switching loss, high efficiency, and galvanic isolation. The inductor-inductor-capacitor (LLC) circuit topology is the most practical resonant converter with high frequency operation when compared to the different resonant circuit topologies. Unfortunately, the input or output voltage range in circuit topologies [4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19] is less than 4:1 (i.e., V_in,max ≤ 4V_in,min) voltage range. Three-level or multi-level converters [20,21,22,23] with neutral-point diode-clamp, flying capacitor, and series-connected full-bridge circuit topologies are often adopted for high voltage operation to reduce the voltage ratings on active devices. Three-level ZVS converters [24,25,26,27,28] can further eliminate the switching losses for medium voltage applications. However, the wide voltage operation is seldom discussed and investigated in conventional three-level soft switching converters. The input voltage range of the three-level converter that is discussed in [20,21,22,23,24,25,26,27,28] is less than 4:1 voltage range operation. For some wind power or solar power applications, the input voltage of DC converters might be greater than 6:1 or 8:1 voltage range, i.e., V_in,max ≥ 6 or 8 V_in,min.

A ZVS three-level DC/DC converter is discussed and then investigated to have 10:1 (80 V ~ 800 V) wide input voltage operation and ZVS operation on active devices. The presented three-level converter has three winding turns and three auxiliary switches on the output-side to achieve wide voltage range operation. Three auxiliary switches on the secondary-side are active or inactive and three different turns-ratio of the isolated transformer are connected to the output load based on the input voltage value. Thus, three equivalent sub-circuits can be operated in the proposed converter to achieve wide voltage operation. Three-level neutral-point diode-clamp converter is adopted on the input-side to have the advantages of low voltage rating and soft switching operation on active devices and increase circuit efficiency. The phase shift PWM operation is used to control the active devices of three-level converter. The leading-leg switches are easily turned on under ZVS operation. The presented circuit has less component counts with better circuit efficiency to achieve 10:1 wide voltage operation when compared to conventional two-stage DC converters. The proposed converter has much wider input voltage operation range as compared to conventional single-stage DC converters with 2:1 or 4:1 voltage range (10:1 voltage range from 80 V ~ 800 V). The paper is organized, as follows. Section 2 discusses the circuit structure. The circuit operation of the presented converter is provided in Section 3. In Section 4, the circuit characteristics and design procedures are provided. In Section 5, the experiments examine the converter performance and advantages of the presented converter. Subsequently, the conclusion of the presented circuit is discussed in Section 6.

2. Circuit Structure

Figure 1a presents the circuit configuration of the presented circuit topology. Three-level diode clamped converter, including S₁ ~ S₄, C₁, C₂, C_f, D_a, D_b, L_r, and T₁, is adopted to lessen the voltage stress on power switches for medium input voltage applications. On the secondary-side, three different winding turns, n_s1, n_s1 + n_s2 and n_s1 + n_s2 + n_s3, with alternating current power switches Q₁ ~ Q₃ are used to provide three different DC voltage gains and extend the voltage range operation. Each switch of Q₁ ~ Q₃ are implemented by two power MOSFETS with back-to-back connection. When Q₁ ~ Q₃ are off, the back-to-back body diodes of two MOSFETs are reverse biased and no current will flow through Q₁ ~ Q₃. The presented converter has three sub-circuits, according to the input voltage range. If V_in is in the low voltage range V_in,L = V_in,min ~ 2V_in,min, the switch Q₃ turns on and Q₁ and Q₂ turn off (Figure 1b). The turns-ratio (n_s1+n_s2+n_s3)/n_p of transformer T is used in Figure 1b to maintain high voltage gain. In the low input voltage operation, diodes D₁ ~ D₄ are off. If V_in is in the medium voltage range V_in,M = 2V_in,min ~ 4V_in,min, switch Q₂ turns on and Q₁ and Q₃ turn off (Figure 1c). The secondary turns n_s1+n_s2 are adopted on the secondary-side. Similarly, switch Q₁ turns on and Q₂ and Q₃ turn off in Figure 1d when V_in is in the high voltage range V_in,H = 4V_in,min ~ 10V_in,min. D₃ ~ D₆ are reverse biased in this sub-circuit. The low turns-ratio n_s1/n_p is used under the high input voltage range. The secondary winding turns n_s1, n_s1 + n_s2 or n_s1 + n_s2 + n_s3, are connected to the output load to achieve three different DC voltage gains, according to the switching states of Q₁ ~ Q₃. Therefore, the presented circuit can accomplish the wide voltage operation. The soft switching operation on power switches is also realized due to the phase-shift PWM operation.

3. Circuit Operation

The presented converter is operated with the phase-shift PWM scheme. The corresponding switches Q₁ ~ Q₃ are controlled to be on or off, so that the proper secondary winding turns n_s1, n_s1 + n_s2 or n_s1 +n_s2 + n_s3 are connecting to the output road to accomplish wide voltage operation due to the input voltage value. In the presented circuit, it assumes that L_m >> L_r, C₁ = C₂, C_S1 = ... = C_S4 = C_oss, C_f >> C_oss, n_s1 = n_s2 = n_s3/2 and V_C1 = V_C2 = V_in/2. The circuit can achieve 10:1, i.e., V_in,max = 10V_in,min, wide input voltage operation. Three sub-circuits, as shown in Figure 2, can be selected in the presented converter based on the input voltage ranges, V_in,L = V_in,min ~ 2V_in,min, V_in,M = 2V_in,min ~ 4V_in,min, and V_in,H = 4V_in,min ~ 10V_in,min.

3.1. Low Input Voltage Range (Q₃ on; Q₁, Q₂ off)

If V_in is in the low voltage range V_in,min ~ 2V_in,min. The secondary-side switch Q₃ turns on and Q₁ and Q₂ turn off (Figure 1b). The winding turns n_s1 + n_s2 + n_s3 are connected to the output inductor. The transformer turns-ratio is n_L = n_p/(n_s1 + n_s2 + n_s3). The DC voltage gain is calculated as G_DC,L = V_o/V_in.L = d_e/n_L, where d_e is the effective duty cycle and V_in,L denotes V_in in low input voltage range. Figure 2a shows the PWM waveforms under low input voltage range. Figure 2b–k show the equivalent circuits for states 1–10 respectively in a switching period.

State 1 [t₀,t₁]: In state 1, S₁ and S₂ are conducting and v_Lm ≈ V_C1 = V_in/2 owing to L_m >> L_r. The diode D₅ is forward biased and v_Lo = V_in/(2n_L) − V_o. The primary-side current is given in Equation (1).

i_Lr(t) = i_Lr(t₀) + (V_in/(2n_L) − V_o)(t − t₀)/(n_LL_o)

(1)

At time t₁, S₁ turns off. Since i_Lr(t₁) > 0, C_S1 is charged from 0 V and C_S4 is discharged from V_in/2.

State 2 [t₁, t₂]:S₁ turns off at time t₁. C_S1 (C_S4) is charged (discharged) from 0 V (V_in/2). C_S1 and C_S4 are about several hundreds of picofarads. Therefore, i_Lr and i_Lo are almost constant in state 2. If the stored energy in L_o and L_r is greater than the stored energy in C_S1 and C_S4, i.e., $\left(L_r+n_L^2{L}_o\right)i_{Lr}^2\left(t_1\right)\ge C_{oss}{V}_{in}^2/2$, then v_CS4 will be decreased to zero at t₂. The time duration in state 2 is obtained in (2).

Δt₁₂ = t₂ − t₁ = C_ossV_in/i_Lr(t₁) = n_LC_ossV_in/i_Lo(t₁)

(2)

The dead time t_d between the gate signals of S₄ and S₁ should be greater than time duration Δt₁₂ in state 2 to ensure the ZVS operation of S₄ after t₂.

State 3 [t₂, t₃]: The body diode D_S4 is forward biased due to i_Lr(t₂) > 0 and v_CS4(t₂) = 0. Therefore, S₄ turns on after time t₂ to accomplish soft switching turn-on. Because L_m >> L_r and the leg voltage v_ab = 0, it can obtain the primary-side winding voltage and secondary-side winding voltage are all equal to zero. Diodes D₅ and D₆ are all forward biased, v_Lo = −V_o and i_Lo decreases. The primary-side current is calculated in Equation (3).

$$i_{Lr}\left(t\right)=i_{Lr}\left(t_2\right)-\left(V_{Da,d}+V_{S2,d}\right)\left(t-t_2\right)/L_r$$

(3)

where V_Da,d and V_S2,d are the drop voltages on diode D_a and switch S₂. i_D5 (i_D6) decreases (increases) in this state. The slopes of i_D5 and i_D6 are expressed in Equation (4).

$$d{i}_{D6}\left(t\right)/dt=-d{i}_{D5}\left(t\right)/dt=n_L\left(V_{Da,d}+V_{S2,d}\right)/2L_r$$

(4)

The state 3 ends at time t₃ when S₂ is off.

State 4 [t₃, t₄]: This state starts at time t₃ when S₂ turns off. Owing to i_Lr at t₃ is positive, C_S3 (C_S2) is discharged (charged) from V_in/2 (0 V). D₅ and D₆ still conduct in this state. The primary-side winging voltage v_Lm = 0. If the energy in the inductor L_r is greater than the energy in capacitors C_S2 and C_S3, i.e., $L_r{i}_{Lr}^2\left(t_3\right)\ge C_{oss}{V}_{in}^2/2$, then the capacitor v_CS3 will be decreased to zero. The time duration in state 4 is calculated as Δt₃₄ = t₄ − t₃ = C_ossV_in/i_Lr(t₃) = n_LC_ossV_in/i_Lo(t₃). The dead time t_d between the gate signals of S₃ and S₂ should be greater than time interval Δt₃₄ to have the soft switching turn-on of S₃.

State 5 [t₄, t₅]: Because i_Lr(t₄) > 0 and v_CS3(t₄) = 0, D_S3 conducts and S₃ turns on after t₄ to have ZVS operation. The leg voltage v_ab = −V_C2 = −V_in/2. Since D₅ and D₆ all conduct, v_Lr equals −V_in/2 and i_Lr decreases in this state. i_D5 (i_D6) is decreased (increased) to 0 (i_Lo) at time t₅. The slopes of i_D5 (i_D6) are calculated in Equation (5).

$$d{i}_{D6}\left(t\right)/dt=-d{i}_{D5}\left(t\right)/dt=n_L{V}_{in}/4L_r$$

(5)

At time t₅, i_D5 is equal to zero ampere and the time interval of state 5 is expressed as Δt₄₅ = t₅–t₄ ≈ 4L_rI_o/(n_LV_in). The duty loss in state 5 is calculated as d_loss,5 = Δt₄₅/T_sw = 4L_rI_of_sw/(n_LV_in), where f_sw is the switching frequency and T_sw is the switching period, as both D₅ and D₆ are still conducting in this state. The PWM waveforms in the states 6–10 are symmetry to waveforms in the states 1–5. Thus, the circuit analysis and discussion of the states 6–10 are neglected.

3.2. Medium Input Voltage Range (Q₂ on; Q₁, Q₃ off)

If V_in is in the medium voltage range, 2V_in,min ~ 4V_in,min. The secondary-side switch Q₂ turns on and Q₁ and Q₃ turn off (Figure 1c). The winding turns n_s1 + n_s2 are connected to the inductor L_o. The transformer turns-ratio under medium voltage range is n_M = n_p/(n_s1 + n_s2). The DC voltage gain is expressed as G_DC,M = V_o/V_in.M = d_e/n_M, where V_in,M denotes V_in in medium input voltage range. The proposed converter has less voltage gain under medium input voltage range and larger voltage gain under low input voltage range since n_L < n_M. Figure 3a illustrates the main PWM circuit waveforms under medium input voltage range. There are ten operating states for every switching cycle. Figure 3b–k provide these ten equivalent circuits.

State 1 [t₀,t₁]: This state starts at time t₀ when S₁ and S₂ are conducting. Because L_r << L_m, the primary-side voltage v_Lm ≈ V_C1 = V_in/2. D₃ conducts and the inductor voltage v_Lo = V_in/(2n_M) − V_o. Power is delivered from C₁ to R_o in state 1. The primary-side current i_Lr(t) increases and equals i_Lo(t)/n_M.

State 2 [t₁, t₂]: This state starts at time t₁ if S₁ turns off. C_S1 (C_S4) is charged (discharged) from 0V (V_in/2). If the inductor energy $\left(L_r+n_M^2{L}_o\right)i_{Lr}^2\left(t_1\right)/2$ is greater than the capacitor energy $C_{oss}{V}_{in}^2/4$, then v_CS4 is equal to zero at t₂.

State 3 [t₂, t₃]: This state starts at time t₂ when v_CS4 = 0. Owing to i_Lr(t₂) > 0, D_S4 is forward biased and S₄ turns on after t₂ to have ZVS operation. Because v_ab = 0, the primary-side winding voltage and secondary-side winding voltage are all zero voltage. Therefore, D₃ and D₄ are conducting, v_Lo = −V_o and i_Lo decreases. The state 3 ends at time t₃ when S₂ turns off.

State 4 [t₃, t₄]: At t₃, S₂ turns off. Since i_Lr(t₃)>0, C_S3 is discharged from V_in/2 to 0V at time t₄. D₃ and D₄ still conduct in this state. If the inductor energy $L_r{i}_{Lr}^2\left(t_3\right)/2$ is greater than the capacitor energy $C_{oss}{V}_{in}^2/4$, then v_CS3 is equal to zero at t₄.

State 5 [t₄, t₅]: At t₄, v_CS3 is equal to zero. D_S3 conducts and S₃ turns on after t₄ to achieve ZVS operation since i_Lr(t₄) > 0. The leg voltage v_ab = −V_C2 = −V_in/2. Owing to D₃ and D₄ conduct in state 5, v_Lr equals −V_in/2 and i_Lr decreases. The diode current i_D3 will decrease to 0 at time t₅. The PWM waveforms in states 6–10 are symmetrical to waveforms in states 1–5, so that the circuit analysis and discussion of states 6–10 are ignored.

3.3. High Input Voltage Range (Q₁ on; Q₂, Q₃ off)

When V_in is in the high voltage range V_in,H = 4V_in,min ~ 10V_in,min. Switch Q₁ turns on and Q₂ and Q₃ turn off (Figure 1d). The winding turns n_s1 are connected to the inductor L_o. For high input voltage range, the transformer turns-ratio is n_H = n_p/n_s1 and the DC voltage gain is given as G_DC,H = V_o/V_in.H = d_e/n_H, where V_in,H denotes V_in in high input voltage range. The proposed converter has the lowest voltage gain under high input voltage range since n_H > n_M > n_L. Figure 4a gives the PWM waveforms for high input voltage range and Figure 4b–k show the equivalent circuits for ten operating states in every switching cycle.

State 1 [t₀,t₁]: The state 1 starts at time t₀ when S₁ and S₂ both conduct. Then, then magnetizing voltage v_Lm ≈ V_C1 = V_in/2. Since D₁ is conducting, the inductor voltage v_Lo = V_in/(2n_H) − V_o, and i_Lo increases.

State 2 [t₁, t₂]: At time t₁, S₁ turns off. C_S1 (C_S4) is charged (discharged) from 0 V (V_in/2). If the inductor energy $\left(L_r+n_H^2{L}_o\right)i_{Lr}^2\left(t_1\right)/2$ is greater than the capacitor energy $C_{oss}{V}_{in}^2/4$, then v_CS4 = 0 at time t₂.

State 3 [t₂, t₃]: At time t₂, v_CS4 = 0. Since i_Lr > 0, D_S4 is conducting. Switch S₄ can turn on after time t₂ to have zero voltage switching operation. The primary-side winding voltage and secondary-side winding voltage are equal to zero and D₁ and D₂ are both conducting since v_ab = 0. The inductor voltage v_Lo = −V_o and i_Lo decreases.

State 4 [t₃, t₄]: Switch S₂ turns off at time t₃. i_Lr(t₃) > 0 discharges C_S3 from V_in/2 to 0 V at time t₄. As D₁ and D₂ both conduct in state 4, the primary-side winging voltage v_Lm = 0. If the inductor energy $L_r{i}_{Lr}^2\left(t_3\right)/2$ is greater than the capacitor energy $C_{oss}{V}_{in}^2/4$, then C_S3 will be discharged to zero voltage.

At time t₄, v_CS3(t₄) = 0. Since i_Lr(t₄) > 0, D_S3 is conducting and S₃ turns on after t₄ to achieve ZVS. In this state, v_ab = −V_C2 = −V_in/2, v_Lr = −V_in/2 and i_Lr decreases. At time t₅, the commutation interval of D₁ and D₂ is completed and i_D1 is decreased to 0. The circuit operation of the states 6–10 are similar to the circuit analysis of the states 1–5. Therefore, the circuit discussion of the states 6–10 are ignored.

4. Circuit Characteristics and Design Procedures

The presented three-level converter with different secondary winding turns is controlled with phase-shift PWM operation to realize wide input voltage operation. The secondary switches Q₁ ~ Q₃ turn on or off to accomplish the different DC voltage gain in order to control the load voltage based on the different input voltage range. The output voltage is calculated in Equation (6).

$$V_o=\{\begin{array}{c}{d}_e{V}_{in}\left(n_{s1}+n_{s2}+n_{s3}\right)/n_p,if{V}_{in,min}<V_{in}<2V_{in,min}\left(lowinputvoltagerange\right)\\ d_e{V}_{in}\left(n_{s1}+n_{s2}\right)/n_p,if2V_{in,min}<V_{in}<4V_{in,min}\left(mediuminputvoltagerange\right)\\ d_e{V}_{in}{n}_{s1}/n_p,if4V_{in,min}<V_{in}<10V_{in,min}\left(highinputvoltagerange\right)\end{array}$$

(6)

where d_e = d − d_loss,5 and d is the duty cycle of leg voltage v_ab. The average current on L_o equals to the load current I_o. The average diode currents I_D1 = … = I_D6 = I_o/2. The average switch currents of Q₁ ~ Q₃ equal I_o. The voltage ratings of switches S₁ ~ S₄ equal V_in,max according to the three-level converter topology. The voltage ratings of D₁ ~ D₆ are expressed as.

V_D1,stress = V_D2,stress = V_in,maxn_s1/n_p

(7)

V_D3,stress = V_D4,stress = V_in,max(n_s1+n_s2)/n_p

(8)

V_D5,stress = V_D6,stress = V_in,max(n_s1+n_s2+n_s3)/n_p

(9)

The output inductance L_o is calculated in Equation (10), based on the given ripple current Δi_Lo.

$$L_o=\left(\frac{V_{in,max}}{2n_H}-V_o\right)d_{e,min}{T}_{sw}/\Delta i_{Lo}=V_o\left(0.5-d_{e,min}\right)T_{sw}/\Delta i_{Lo}$$

(10)

The duty cycle loss in the state 5 depends on L_r and the inductance L_r can be expressed in Equation (11).

$$L_r=n_L{V}_{in,min}{d}_{loss,5}{T}_{sw}/4I_o$$

(11)

The presented circuit is operated under the input voltage range V_in from 80 V ~ 800 V, V_o = 12 V, P_o,rated = 300 W, and f_sw = 150 kHz. The theoretical three input voltage ranges are V_in,L = 80 V ~ 160 V, V_in,M = 160 V ~ 320 V, and V_in,H = 320 V ~ 800 V. If the input voltage is in the low voltage range (V_in = 80 V ~ 160 V), the secondary switch Q₃ is on and Q₁ and Q₂ are off. The winding turns n_s1+n_s2+n_s3 connect to the output filter inductor L_o. When V_in is increased and equal to 160 V (in medium voltage range V_in = 160 V ~ 320 V), then Q₂ is on and Q₁ and Q₃ are off. Afterwards, the winding turns n_s1 + n_s2 connect to the output inductor L_o. Similarly, the input voltage is in the high voltage range from 320 V to 800 V. Switch Q₁ is on and Q₂ and Q₃ are off. Only the winding turns n_s1 connect to L_o. There is a ±20 V voltage tolerance with Schmitt trigger circuit between three voltage ranges to avoid the signal oscillation at the voltages 160 V between low and medium input voltage ranges and 320 V between the medium and high voltage ranges. The Schmitt comparators and logic gates shown in Figure 5 are adopted to provide the PWM signals for each output voltage range. Therefore, the actual three input voltage ranges are V_in,L = 80 V ~ 180 V, V_in,M = 140 V ~ 340 V, and V_in,H = 300 V ~ 800 V.

The proposed converter is assumed to have 90% efficiency at V_in = 80V and full road condition under low input voltage range (80V ~ 180V). The assumed maximum duty cycle d_max of the leg voltage v_ab under V_in = 80 V is 0.48. The duty cycle loss d_loss,5 at the state 5 is assumed 0.15 and the effective duty cycle d_e,max = d_max − d_loss,5 = 0.33. The primary inductance L_r is obtained from (6) and (11).

$$L_r=\eta V_{in,min}^2{d}_{loss,5}{d}_{e,max}{T}_{sw}/4P_o\approx 1.6\mu H$$

(12)

The turn-ratio n_L can be expected in Equation (13).

$$n_L=d_{e,max}{V}_{in,min}/V_o\approx 2.2$$

(13)

In the presented circuit, the turns-ratio of transformer T are n_L = 2, n_M = 4 and n_H = 8, with the primary-side turns n_p = 16, the secondary-side turns n_s1 = n_s2 = 2 and n_s3 = 4 and the magnetizing inductance L_m = 650 μH. For low voltage range, the minimum effective duty cycle d_e,min under the maximum input voltage 180 V is calculated as.

$$d_{e,min}=d_{e,max}{V}_{in,L,min}/V_{in,L,max}\approx 0.147$$

(14)

If the ripple current Δi_Lo is assumed 30% of I_o,max under V_in,L,max = 180 V (low input voltage range). The output filter inductance L_o can be derived in Equation (15).

$$L_o=d_{e,min}{T}_{sw}\left(V_{in,L,max}/n_L-V_o\right)/\Delta i_{Lo}\approx 8.2\mu H$$

(15)

The actual output inductance L_o = 8 μH is used in the presented circuit. Under the minimum input voltage, the switches S₁ ~ S₄ have the maximum current stress. The switch root-mean-square (rms) currents are approximated in Equation (16).

$$i_{S1,min}=..=i_{S4,min}=I_{o,rated}/\left(n_L\eta \sqrt{2}\right)\approx 9.8A$$

(16)

The voltage rating of active devices S₁ ~ S₄ is V_in,max/2 = 400 V. The MOSFETs IPW60R070P6 (650V/33A) are used for switch S₁ ~ S₄ and Q₁ ~ Q₃. The average diode currents i_D1,av ~ i_D6,av are I_o,rated/2 = 12.5 A. The maximum voltage stress of D₁ ~ D₆ are approximately V_in,max/n_L = 800 V/2 = 400 V. The ultrafast recovery diodes APT30DQ60BG (600 V/30 A) are adopted for diodes D₁ ~ D₆. The other passive components in the prototype circuit are C_o = 470 μF/35 V, C₁ = C₂ = 150 μF/450 V, C_f = 1 μF/630 V, and D_a and D_b are DSEI30-12A with 1200 V/26 A voltage/current stress. The control block of the proposed circuit is given in Figure 5. Two Schmitt comparators and logic gates are adopted to determine three input voltage ranges by using the switching status of Q₁ ~ Q₃. The phase-shift PWM control integrated circuit UCC3895 is adopted for producing the PWM signals of S₁ ~ S₄. The voltage regulator TL431 and optocoupler PC817 are adopted to control the load voltage. The type 3 voltage control [29] with two zeros and three poles are used to have the enough phase margin at crossover frequency at 8 kHz.

5. Experimental Results

The test results that are based on the circuit components are shown in

Table 1. Prototype Circuit Parameters.

Items	Symbol	Parameter
Input voltage	Vin	80 V ~ 800 V
Output voltage	Vo	12 V
Rated output current	Io	25 A
Switching frequency	fsw	150 kHz
Input capacitors	C1, C2	150 μF/450 V
Voltage balance capacitor	Cf	1 μF/630 V
Power switches	S1 ~ S4,Q1 ~ Q3	IPW60R070P6
Rectifier diodes	D1 ~ D6	APT30DQ60BG
Clamp diodes	Da, Db	DSEI30-12A
Winding turns of T	np, ns1, ns2, ns3	16, 2, 2, 4
inductance	Lr	1.6 μH
Magnetizing inductance	Lm	650 μH
Output inductance	Lo	8 μH
Output capacitance	Co	470 μF/35 V

derived in the previous section are demonstrated to confirm the circuit performance. Figure 6, Figure 7 and Figure 8 show the test waveforms of the presented circuit under low, medium, and high input voltage ranges, and the rated output power. Figure 6a provides the measured PWM waveforms of switches S₁ ~ S₄ under V_in = 80 V and the rated output power 300 W. Figure 6b provides the PWM signals of switches Q₁ ~ Q₃ on the secondary-side. Switch Q₃ is on and Q₁ and Q₂ are off due to the V_in = 80V being in the low voltage range. Figure 6c,d provide the measured main currents on the input and output sides. It can observe that the diodes D₅ and D₆ are conducting due to Q₃ is in the on-state. The currents i_D1 ~ i_D4 are all zero due to Q₁ and Q₂ are off. Figure 6e–h provide the experimental waveforms of the presented circuit under V_in = 175 V and P_o = 300 W. Figure 6e gives the PWM signals of S₁ ~ S₄. Q₁ and Q₂ are off and Q₃ is on as shown in Figure 6f due to V_in = 175 V is in the low voltage range. Figure 6g,h present the main currents on the input and output sides. From Figure 6c,g, the ripple current Δi_Lo at 80 V input voltage is less than the ripple current Δi_Lo at 175 V input voltage due to the duty cycle of the converter leg voltage at V_in = 80 V case is larger than the duty cycle at V_in = 175 V condition. The measured waveforms in Figure 6 are almost conformed with the theoretical waveforms in Figure 2 under low input voltage range. Figure 7 presents the test results of the presented circuit under the medium input voltage range (V_in = 140 V ~ 340 V) and the rated output power. Figure 7a–d gives the experimental waveforms at V_in = 145 V and P_o = 300 W. Figure 7a,b demonstrate the PWM waveforms of switches S₁ ~ S₄ and Q₁ ~ Q₃. Q₁ and Q₃ are off and Q₂ is on due to the medium input voltage range operation (Figure 7b). Figure 7c,d provide the main currents on the input and output sides. Diodes D₃ and D₄ are conducted in the medium input voltage range and D₁, D₂, D₅, and D₆ are off. Similarly, Figure 7e–h provide the test results of the presented circuit under V_in = 335 V and P_o = 300 W. It is clear that the ripple current Δi_Lo at V_in = 145 V (Figure 7c) is less than the ripple current Δi_Lo at V_in = 335 V (Figure 7g). Figure 8 gives the test results of the proposed circuit under high input voltage range (V_in = 300 V ~ 800 V) and the rated output power. Figure 8a–d provide the measured waveforms at V_in = 305 V and P_o = 300 W. Figure 8e–h demonstrate the test results at V_in = 800 V and P_o = 300 W. For high input voltage range, switch Q₁ is on and Q₂ and Q₃ are off (Figure 8b,f). Therefore, diodes D₃ ~ D₆ are off (Figure 8d,h). Figure 8a,e show the PWM waveforms of S₁ ~ S₄ for V_in = 305 V and 800 V, respectively. Figure 8c,g provide the measured currents i_Lr, i_D1, i_D2 and i_Lo for V_in = 305 V and 800 V, respectively. Figure 9 shows the test results of S₁ (the leading-leg switch) at V_in = 80 V, 400 V and 800 V conditions. Figure 9a,b show the measured results of S₁ at 20% and 100% loads under V_in = 80 V input. The drain voltage v_S1,d is reduced to zero voltage before S₁ is turned on. Similarly, Figure 9c,d provide the measured waveforms of S₁ at 20% and 100% loads under V_in = 400 V input. Figure 9e,f demonstrate the measured waveforms of S₁ at 20% and 100% loads under V_in = 800 V input, respectively. The other leading-leg switch S₄ has the same turn-on/turn-off characteristics as switch S₁. From the experimental waveforms in Figure 9, the leading-leg switches S₁ and S₄ can turn on at ZVS from 20% to 100% rated load. Figure 10 provides the experimental results of the lagging-leg switch S₂ at V_in = 80 V, 400 V, and 800 V. Figure 10a,b show the test results of S₂ for 20% and 50% rated power under 80V input case. It can be observed that S₂ is turned on at hard switching operation at 20% load (Figure 10a) and soft switching operation at 50% load (Figure 10b). Figure 10c,d provide the test results of S₂ for V_in = 400 V and 800 V, respectively, under the rated power. From the experimental waveforms that are shown in Figure 10, the lagging-leg switches S₁ and S₂ are almost turned on at hard switching operation. Figure 11 gives the measured converter efficiencies under different voltage ranges. Basically, the converter has larger duty cycle at the low input voltage in each voltage range. The larger duty cycle will result in less root mean square current on the primary-side and less conduction losses. The circuit efficiency at V_in = 80 V is better than the circuit efficiency at V_in = 175 V under a low input voltage range. Similarly, the circuit efficiency at V_in = 305 V is better than the circuit efficiency at V_in = 800 V under high input voltage range operation. The circuit efficiency under the high input voltage range is better than the low input voltage range since the presented circuit has larger the primary-side current under low input voltage range. The synchronous rectifiers with low turn-on resistance instead of rectifier diodes can be adopted on the secondary side to reduce the conduction losses in order to increase the circuit efficiency. The Litz wire [30] can be adopted to avoid the skin effect on winding resistance to reduce the copper losses on transformer and output inductor. The more power loss analysis of power semiconductors, inductors, transformers, and capacitors on power converters has been discussed in [31].

6. Conclusions

In solar power system, the input voltage from solar panel is wide variation due to the different solar intensity in day and night. The conventional two-level or three-level converter cannot be operated under wide voltage operation. In this paper, a three-level diode-clamped DC/DC converter with three auxiliary secondary turns is presented and then discussed to provide the capability of 10:1 wide voltage range operation for solar power converters to supply the isolated power supply for control board demand. Three sets of secondary windings are adopted in the presented circuit to overcome the wide input voltage variation in solar power converters. The proposed converter can operate at three input voltage ranges to supply the stable DC voltage at the output load due to three different secondary winding turns connected to output side. The PWM scheme is adopted to control the load voltage in each input voltage range. The leading-leg switches in the three-level converter can be realized with ZVS operation due to the large inductor energy on the output inductor. The lagging-leg switches are almost operated at hard switching operation due to the limited energy stored on the leakage inductor of transformer. The large leakage inductor or external inductor can be used on the input side to overcome this disadvantage. However, the large leakage inductor will increase the duty cycle loss in state 5. The future work of this project will investigate the new snubber circuit or auxiliary circuit added on the output side to lessen the freewheel current. Thus, the duty cycle loss can be expected to reduce and the soft switching operation range of the lagging-leg switches can be extended. The proposed converter can be used in the solar power system with wide input voltage variation from solar panel to provide the standalone power unit for control system demand. Finally, the test results prove the performance and feasibility of the presented circuit.