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Communication

The Optimization of Program Operation for Low Power Consumption in 3D Ferroelectric (Fe)-NAND Flash Memory

by
Myeongsang Yun
1,†,
Gyuhyeon Lee
1,†,
Gyunseok Ryu
1,
Hyoungsoo Kim
2 and
Myounggon Kang
1,*
1
Department of Electronics Engineering, Korea National University of Transportation, Room No. 307, IT Building, 50 Daehak-ro, Chungju-si 27469, Chungbuk, Republic of Korea
2
Department of Electrical and Computer Engineering, California State Polytechnic University, Pomona, CA 91768, USA
*
Author to whom correspondence should be addressed.
†
These authors contributed equally to this work.
Electronics 2024, 13(2), 316; https://doi.org/10.3390/electronics13020316
Submission received: 24 November 2023 / Revised: 5 January 2024 / Accepted: 9 January 2024 / Published: 11 January 2024
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Abstract

:
This paper proposes an optimized program operation method for ferroelectric NAND (FE-NAND) flash memory utilizing the gate-induced drain leakage (GIDL) program and validated through simulations. The program operation was performed by setting the time for the unselected cell to reach the pass voltage (Vpass) to 0.1 µs, 0.2 µs, and 0.3 µs, respectively. As the time for the unselected word line (WL) to reach Vpass increases, the channel potential increases due to a decrease in the electron–hole recombination rate. After the program operation, the threshold voltage (Vth) shift of the selected cell and the pass disturb of the unselected cells according to the Vpass condition were analyzed. Consequently, there was a more significant change in Vth among selected cells compared to the time for unselected cells to reach Vpass as 0.1 µs. The findings of this study suggest an optimal program operation that increases slowly and decreases rapidly through the variation of Vth according to the program operation. By performing the proposed program operation, we confirmed that low-power operation is achievable by reducing the WL voltage by 2 V and the bit line (BL) voltage by 1 V, in contrast to the conventional GIDL program.

1. Introduction

Semiconductor technology is pivotal in modern society, serving as an indispensable foundation across diverse fields. As the demand for semiconductors continues to surge, NAND flash memory technology and performance are constantly evolving, with innovations that encompass enhanced speed, increased density, and reduced power consumption [1,2,3,4,5,6,7,8,9]. Nevertheless, 2D NAND flash memory is continuously being replaced by 3D NAND flash memory due to technical obstacles such as limited cell density, interference, finite lifespan, and persistent downscaling challenges [10,11,12,13,14]. Moreover, 3D NAND flash memory surpasses 2D NAND flash memory in both performance and capacity, and researchers continue to explore new structures and innovative technologies in the realm of 3D NAND flash memory [15]. The introduction of FE-NAND flash memory aimed to address the issue of high program voltage (VPGM) associated with the charge-trap flash (CTF) structure [16,17]. Ferroelectric field-effect transistors (FE-FETs) fabricated using hafnia-based ferroelectrics are attracting attention as next-generation memory devices due to their low operating voltage, excellent data retention, and fast switching speed.
It has intrinsic, non-volatile memory properties due to its two stable polarization states that can be switched. In addition, it has the advantage of being compatible with existing complementary metal oxide semiconductor manufacturing processes, and the conformal deposition of ferroelectric films is possible even in vertical structures such as 3D NAND flash memory through atomic layer deposition. Accordingly, research is continuing on 3D FE-NAND flash memory, which adds a ferroelectric thin film to the gate stack of existing NAND flash cells [18]. This study is concerned with the GIDL erase method employed in the CTF structure that was adapted for use in the program operation of FE-NAND flash memory cells [19]. Implementing the GIDL program makes it feasible to perform normal memory operations while maintaining the conventional 3D NAND flash memory structure and wiring method despite the distinctive operational traits of FE-NAND. Furthermore, even in multi-string operation, GIDL can be selectively generated for the BL to be programmed, thereby enabling the same program operation as the conventional 3D NAND flash memory structure.
In this study, we employed the Synopsys Sentaurus Technology computer-aided design (TCAD) tool to analyze the Vth of the selected cell and the pass disturb of the unselected cell, depending on the time required for the unselected WL to reach the Vpass during the GIDL program operation [20]. In addition, we proposed optimal voltage conditions for the program operation proposed here. Therefore, we confirmed that low-power program operation is achieved by reducing the WL voltage by 2 V and the BL voltage by 1 V, compared with the conventional GIDL program.

2. Structure of the Proposed Program Operation

Figure 1 shows a cross-sectional view of FE-NAND flash memory, which was generated using Synopsys Sentaurus structure editor. The configuration includes memory transistors for WL0, WL1, and WL2, along with string select line (SSL) and ground select line (GSL) transistors. Here, WL1 represents the selected cell. As detailed in Figure 1 and in Table 1, the structure comprises SiO2, Poly-Si, HfO2, and a metal gate. The cross-section in Figure 1 was simulated as a gate-all-around (GAA) structure using the cylindrical command. In addition, models were employed to consider doping concentration dependence, high field saturation, trap scattering mobility, and Trap-Assist-Tunnel (TAT) effects in the device simulations. Also, simulations of the V-NAND structure’s operation included the utilization of Shockley–Read–Hall (SRH), Schenk band-to-band recombination, and tunneling models.
Figure 2 shows a voltage–timing diagram for each node employed in the GIDL program operation of the FE-NAND flash memory. The duration for the unselected cell to reach Vpass was configured as follows: Case 1 with 0.1 µs, Case 2 with 0.2 µs, and Case 3 with 0.3 µs. When a voltage of VPGM = 10 V is applied to the selected BL and Vcc = 2 V is applied to the SSL, the channel potential increases. Selective programming was achieved by applying GND to the selected WL, Vpass = 7 V to the unselected WL, and GND to the GSL.

3. Simulation Results

Figure 3a shows the channel potential of the selected string at 0.5 µs during program operation in Case 1, Case 2, and Case 3. The channel potential of the selected string increases sequentially in the order of Case 1, Case 2, and Case 3. Figure 3b presents the channel recombination rates in Case 1, Case 2, and Case 3 during the program operation at 0.1 µs. This explains why the channel potential is highest in Case 3 [21,22,23]. In Case 1, the recombination rate is the highest, and it progressively decreases towards Case 2 and Case 3. When the unselected cell operates at 0.1 µs, Case 3 exhibits the lowest Vpass. A higher Vpass leads to a reduction in electron and hole density within the channel due to recombination, ultimately resulting in a decrease in the channel potential.
Figure 4a represents the I−V curve of the selected cell (WL1) measured at 0.6 µs after programming in all cases. Vth increases from 1.789 V in Case 1 to 2.211 V in Case 3. As the channel potential increases during the GIDL program, the potential difference with the selected cell also increases, resulting in it being most programmed in Case 3. Figure 4b,c show the pass disturb of unselected cells (WL0, WL2) measured at 0.6 µs after program operation in all cases [24,25,26]. The Vth shifted more in both adjacent cells from Case 1 to Case 2 and Case 3. In the Case 3 programming, a pass disturb of 0.18 V was observed in WL0, and a pass disturb of 0.17 V occurred in WL2.
The following results were obtained by comparing to the conventional method of 0.5 µs. In this case, the time for the unselected cell to reach Vpass was fixed at 0.1 µs, and then the timing at which Vpass decreases was varied to 0.3 µs and 0.4 µs. This approach is in contrast to the proposed program operation method.
Figure 5a represents the I−V curve of the selected cell, measured at 0.6 µs after programming in all cases. As previously mentioned, it was confirmed that there was no effect on Vth, as the recombination rate remained consistent. Figure 5b presents the pass disturb of an unselected cell, measured at 0.6 µs after program operation in all cases. Based on the measurement results, the most significant shift in Vth occurs when Vpass decreases at 0.3 µs. As the decrease time becomes faster, a smaller value of Vpass is applied within the same time frame. This results in an increased potential difference, subsequently leading to a higher pass disturb.
Hence, in contrast to the proposed program operation method, an analysis conducted at various time points when Vpass decreases after reaching the unselected cell revealed that the shift in the Vth of the selected cell had a negligible impact, while the pass disturb due to a substantial Vth shift in the unselected cell had a significant effect.
It has been confirmed that low-power program operation is achievable by implementing Case 3, as proposed in this paper. Therefore, the optimal BL/WL voltage conditions during low-power program operation were found by analyzing the program of the selected cell and the disturb of the adjacent unselected cell while reducing it by 1 V increments using TCAD simulation.
Figure 6a,b show the Case 3 timing graph and table of the disturbance of the Vth of the selected cell and the adjacent unselected cell during the program operation according to the WL/BL voltage by applying the Case 3 method. In the Case 1 program operation, where the time for the unselected cell to reach Vpass is 0.1 µs, corresponding to conventional GIDL program operation, the Vth of WL1 is 1.789 V, and the Vth shift due to disturb on WL0 and WL2 is 0.129 V and 0.135 V, respectively. Subsequent TCAD simulations confirmed that WL = 5 V and BL = 9 V are the optimal voltage conditions for low-power program operation in the proposed Case 3 during GIDL program operation.
In Figure 7a,b, a comparison is made between the selected cell and I−V curves of WL0 and WL2 under the conditions of BL = 10 V and WL = 7 V, representing Case 1, which corresponds to conventional GIDL program conditions, which were made after program operation was performed in Case 3 under the conditions of BL = 9 V and WL = 5 V.
As depicted in Figure 7a, it is evident that there is nearly the same degree of change in Vth. Specifically, Vth = 1.792 V is observed during optimal voltage condition program operation using the Case 3 method, whereas Vth = 1.789 V is seen during conventional GIDL program operation. Furthermore, Figure 7b presents a graph comparing the application of an optimal voltage in the programming process using the Case 3 method with the pass disturb of the unselected cell adjacent to the conventional GIDL program. The analysis revealed that the program disturb increased compared to the conventional GIDL program. However, the increase in disturb, approximately 0.05 V, does not pose significant operational issues. Therefore, the proposed program operation has optimized low-power functionality compared to the conventional FE-NAND operation [19].

4. Conclusions

In this study, to optimize the programming method in the 3D FE-NAND flash memory structure, the GIDL program was applied. The voltage applied to the unselected cell was then analyzed under different cases. With an increase in the time it takes for the unselected cell to reach Vpass, the electron–hole recombination rate decreases while the channel potential increases. Consequently, the Vth of the selected cell increased, and the pass disturb of the unselected cell also escalated. In conclusion, we confirmed that the program effect is most pronounced in Case 3, characterized by the increase of channel potential. On the contrary, it was observed that as the time for the voltage to drop after reaching Vpass increases, there is a corresponding increase in the occurrence of pass disturb. Hence, it was established that controlling the Vpass time to slowly increase and rapidly decrease yielded the optimal outcome for low-power program operation. Subsequently, following the optimized programming method, BL/WL voltage was reduced by 1 V through TCAD simulation. As a result of these simulations, it was affirmed that low-power program operation could be achieved by lowering the WL voltage by 2 V and the BL voltage by 1 V compared to the conventional GIDL program operation. Therefore, it is expected that this study will make effective contributions when transitioning from the CTF V-NAND structure to the FE-NAND structure in the future.

Author Contributions

Methodology, paper writing, investigation, conceptualization, M.Y. and G.L.; validation and investigation, M.Y., G.L., G.R. and H.K.; project administration, funding acquisition, editing, and supervision, M.K. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported by the Institute for Information and Communications Technology Planning and Evaluation (IITP) grant funded by the Korean government (MSIT) (2021-0-01764-001, Charge-Storage-Memory-Based PIM Development). In addition, this research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF), funded by the Ministry of Education (2018R1A6A1A03023788), and this research was supported by National R&D Program through the National Research Foundation of Korea(NRF) funded by Ministry of Science and ICT (2021M3F3A2A03017693).

Data Availability Statement

Data is contained within the article.

Conflicts of Interest

The authors declare no conflicts of interest.

References

  1. Park, K.T.; Nam, S.; Kim, D.; Kwak, P.; Lee, D.; Choi, Y.; Choi, M.; Kwak, D.; Kim, D.; Kim, M.; et al. Three-Dimensional 128 Gb MLC Vertical NAND Flash Memory with 24-WL Stacked Layers and 50 MB/s High-Speed Programming. IEEE J. Solid State Circuits 2014, 50, 204–213. [Google Scholar] [CrossRef]
  2. Cheong, W.; Yoon, C.; Woo, S.; Han, K.; Kim, D.; Lee, C.; Choi, Y.; Kim, S.; Kang, D.; Yu, G.; et al. A Flash Memory Controller for 15-μs Ultra-Low-Latency SSD Using High-Speed 3D NAND Flash with 3-μs Read Time. In Proceedings of the 2018 IEEE International Solid-State Circuits Conference-(ISSCC 2018), San Francisco, CA, USA, 11–15 February 2018. [Google Scholar]
  3. Choi, Y.J.; Suh, K.D.; Koh, Y.N.; Park, J.W.; Lee, K.J.; Cho, Y.J.; Suh, B.H. A High Speed Programming Scheme for Multi-level NAND Flash Memory. In Proceedings of the Symposium on V.L.S.I. Circuits, Digest of Technical Papers, Honolulu, HI, USA, 13–15 June 1996. [Google Scholar]
  4. Takeuchi, K.; Tanaka, T.; Tanzawa, T. A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories. IEEE J. Solid State Circuits 1998, 33, 1228–1238. [Google Scholar] [CrossRef]
  5. Takeuchi, K. Novel Co-design of NAND Flash Memory and NAND Flash Controller Circuits for sub-30 Nm Low-Power High-Speed Solid-State Drives (SSD). IEEE J. Solid State Circuits 2009, 44, 1227–1234. [Google Scholar] [CrossRef]
  6. Kim, M.K.; Kim, I.J.; Lee, J.S. CMOS-Compatible Ferroelectric NAND Flash Memory for High-Density, Low-Power, and High-Speed Three-Dimensional Memory. Sci. Adv. 2021, 7, e1341. [Google Scholar] [CrossRef] [PubMed]
  7. Park, C.; Talawar, P.; Won, D.; Jung, M.; Im, J.; Kim, S.; Choi, Y. A High Performance Controller for NAND Flash-Based Solid State Disk. In Proceedings of the 21st IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, CA, USA, 12–16 February 2006. [Google Scholar]
  8. Kgil, T.; Mudge, T. Flashcache: A NAND Flash Memory File Cache for Low Power Web Servers. In Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, Seoul, Republic of Korea, 22–25 October 2006; pp. 103–112. [Google Scholar] [CrossRef]
  9. Compagnoni, C.M.; Goda, A.; Spinelli, A.S.; Feeley, P.; Lacaita, A.L.; Visconti, A. Reviewing the evolution of the NAND flash technology. Proc. IEEE 2017, 105, 1609–1633. [Google Scholar] [CrossRef]
  10. Kang, M.; Park, I.H.; Chang, I.J.; Lee, K.; Seo, S.; Park, B.G.; Shin, H. An Accurate Compact Model Considering Direct-Channel Interference of Adjacent Cells in sub-30-nm NAND Flash Technologies. IEEE Electron Device Lett. 2012, 33, 1114–1116. [Google Scholar] [CrossRef]
  11. Kang, M.; Lee, K.; Chae, D.H.; Park, B.G.; Shin, H. The Compact Modeling of Channel Potential in sub-30-nm NAND Flash Cell String. IEEE Electron Device Lett. 2012, 33, 321–323. [Google Scholar] [CrossRef]
  12. Park, M.; Kim, K.; Park, J.H.; Choi, J.H. Direct Field Effect of Neighboring Cell Transistor on Cell-to-Cell Interference of NAND Flash Cell Arrays. IEEE Electron Device Lett. 2008, 30, 174–177. [Google Scholar] [CrossRef]
  13. Jeong, W.; Im, J.W.; Kim, D.H.; Nam, S.W.; Shim, D.K.; Choi, M.H.; Yoon, H.J.; Kim, D.H.; Kim, Y.S.; Park, H.W.; et al. A 128 Gb 3b/cell V-NAND Flash Memory with 1 Gigabit per Second I/O Rate. IEEE J. Solid State Circuits 2015, 51, 204–212. [Google Scholar]
  14. Choi, E.S.; Park, S.K. Device Considerations for High Density and Highly Reliable 3D NAND Flash Cell in near Future. In Proceedings of the 2012 International Electron. Devices Meeting, San Francisco, CA, USA, 10–13 December 2012. [Google Scholar] [CrossRef]
  15. Ham, I.; Jeong, Y.; Baik, S.J.; Kang, M. Ferroelectric Polarization Aided Low Voltage Operation of 3D NAND Flash Memories. Electronics 2020, 10, 38. [Google Scholar] [CrossRef]
  16. Seo, Y.; An, H.; Yeong Song, M.; Geun Kim, T. Charge Trap Flash Memory Using Ferroelectric Materials as a Blocking Layer. Appl. Phys. Lett. 2012, 100, 173507. [Google Scholar] [CrossRef]
  17. Wang, S.; Takahashi, M.; Li, Q.H.; Takeuchi, K.; Sakai, S. Operational Method of a Ferroelectric (Fe)-NAND Flash Memory Array. Semicond. Sci. Technol. 2009, 24, 105029. [Google Scholar] [CrossRef]
  18. Kim, G.; Lee, S.; Eom, T.; Kim, T.; Jung, M.; Shin, H.; Jeong, Y.; Kang, M.; Jeon, S. High performance ferroelectric field-effect transistors for large memory-window, high-reliability, high-speed 3D vertical NAND flash memory. J. Mater. Chem. C 2022, 10, 9802–9812. [Google Scholar] [CrossRef]
  19. Choi, S.; Choi, C.; Jeong, J.K.; Kang, M.; Song, Y.H. A Novel Structure and Operation Scheme of Vertical Channel NAND Flash with Ferroelectric Memory for Multi String Operations. Electronics 2020, 10, 32. [Google Scholar] [CrossRef]
  20. Synopsys Inc. Sentaurus Device User Guide; Version 2014.09; Synopsys Inc.: Mountain View, CA, USA, 2014. [Google Scholar]
  21. Sah, C.T.; Shockley, W. Electron-Hole Recombination Statistics in Semiconductors Through Flaws with Many Charge Conditions. Phys. Rev. 1958, 109, 1103–1115. [Google Scholar] [CrossRef]
  22. O’Neil, M.; Marohn, J.; McLendon, G. Dynamics of Electron-Hole Pair Recombination in Semiconductor Clusters. J. Phys. Chem. 1990, 94, 4356–4363. [Google Scholar] [CrossRef]
  23. Moser, J.; Grätzel, M.; Gallay, R. Inhibition of Electron-Hole Recombination in Substitutionally Doped Colloidal Semiconductor Crystallites. Helv. Chim. Acta 1987, 70, 1596–1604. [Google Scholar] [CrossRef]
  24. Zhang, Y.; Jin, L.; Zou, X.; Liu, H.; Zhang, A.; Huo, Z. A novel program scheme for program disturbance optimization in 3-D NAND flash memory. IEEE Electron Device Lett. 2018, 39, 959–962. [Google Scholar] [CrossRef]
  25. Torsi, A.; Zhao, Y.; Liu, H.; Tanzawa, T.; Goda, A.; Kalavad, P.; Parat, K. A Program Disturb Model and Channel Leakage Current Study for sub-20 Nm NAND Flash Cells. IEEE Trans. Electron Devices 2010, 58, 11–16. [Google Scholar] [CrossRef]
  26. Shim, K.S.; Choi, E.S.; Jung, S.W.; Kim, S.H.; Yoo, H.S.; Jeon, K.S.; Joo, H.S.; Oh, J.S.; Jang, Y.S.; Park, K.J.; et al. Inherent Issues and Challenges of Program Disturbance of 3D NAND Flash Cell. In Proceedings of the 4th IEEE International Memory Workshop, Milan, Italy, 20–23 May 2012. [Google Scholar]
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Figure 1. Cross-sectional view of the 3D FE-NAND structure.
Figure 1. Cross-sectional view of the 3D FE-NAND structure.
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Figure 2. The program operation of the FE-NAND flash memory using GIDL.
Figure 2. The program operation of the FE-NAND flash memory using GIDL.
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Figure 3. Phenomenon in the channels during the operation of the program for Case 1 (BL = 10 V, WL = 7 V), Case 2 (BL = 10 V, WL = 7 V), and Case 3 (BL = 10 V, WL = 7 V): (a) selected string channel potential (b) for each case channel recombination rate at 0.1 µs.
Figure 3. Phenomenon in the channels during the operation of the program for Case 1 (BL = 10 V, WL = 7 V), Case 2 (BL = 10 V, WL = 7 V), and Case 3 (BL = 10 V, WL = 7 V): (a) selected string channel potential (b) for each case channel recombination rate at 0.1 µs.
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Figure 4. Comparison of I−V curves for different proposed Cases: (a) changes in the Vth of the selected cell; (b,c) changes in pass disturb for adjacent unselected cells.
Figure 4. Comparison of I−V curves for different proposed Cases: (a) changes in the Vth of the selected cell; (b,c) changes in pass disturb for adjacent unselected cells.
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Figure 5. Comparison of I−V curves based on the decreasing time while keeping Vpass arrival time fixed at 1 μs: (a) changes in the Vth of the selected cell; (b) changes in pass disturb for unselected cells.
Figure 5. Comparison of I−V curves based on the decreasing time while keeping Vpass arrival time fixed at 1 μs: (a) changes in the Vth of the selected cell; (b) changes in pass disturb for unselected cells.
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Figure 6. A simulation measuring program and disturb while gradually reducing WL and BL voltages by 1 V each, using the optimized approach: (a) Case 3; (b) table. The table indicated the optimal voltage conditions.
Figure 6. A simulation measuring program and disturb while gradually reducing WL and BL voltages by 1 V each, using the optimized approach: (a) Case 3; (b) table. The table indicated the optimal voltage conditions.
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Figure 7. Comparison of I−V curves between Conventional Case 1 (BL = 10 V, WL = 7 V) and the optimized approach, Case 3 (BL = 10 V, WL = 7 V): (a) changes in the Vth of the selected cell; (b) changes in pass disturb for unselected cells.
Figure 7. Comparison of I−V curves between Conventional Case 1 (BL = 10 V, WL = 7 V) and the optimized approach, Case 3 (BL = 10 V, WL = 7 V): (a) changes in the Vth of the selected cell; (b) changes in pass disturb for unselected cells.
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Table 1. Parameters of FE-NAND.
Table 1. Parameters of FE-NAND.
ParametersValue
SiO2 thickness20 nm
Poly-Si channel thickness20 nm
HfO2 thickness10 nm
Gate length (WL, SSL, GSL)40 nm
Spacer length40 nm
Selected cellWL1
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Yun, M.; Lee, G.; Ryu, G.; Kim, H.; Kang, M. The Optimization of Program Operation for Low Power Consumption in 3D Ferroelectric (Fe)-NAND Flash Memory. Electronics 2024, 13, 316. https://doi.org/10.3390/electronics13020316

AMA Style

Yun M, Lee G, Ryu G, Kim H, Kang M. The Optimization of Program Operation for Low Power Consumption in 3D Ferroelectric (Fe)-NAND Flash Memory. Electronics. 2024; 13(2):316. https://doi.org/10.3390/electronics13020316

Chicago/Turabian Style

Yun, Myeongsang, Gyuhyeon Lee, Gyunseok Ryu, Hyoungsoo Kim, and Myounggon Kang. 2024. "The Optimization of Program Operation for Low Power Consumption in 3D Ferroelectric (Fe)-NAND Flash Memory" Electronics 13, no. 2: 316. https://doi.org/10.3390/electronics13020316

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