Investigation of Electro-Thermal Performance for TreeFET from the Perspective of Structure Parameters

Abstract

In this work, the electro-thermal properties of TreeFET, which combines vertically stacked nanosheet (NS) and fin-shaped interbridge (IB) channels, are investigated in terms of interbridge width (W_IB), nanosheet space (S_NS) and nanosheet width (W_NS) by TCAD simulation. Electrical characteristics such as electron density distributions, on/off-state current (I_ON, I_OFF), subthreshold swing (SS) and self-heating effects (SHE) such as lattice temperature and thermal resistance (R_th) are systematically studied to optimize the performance of TreeFET. The result shows that a smaller W_IB mitigates the short-channel effects and increases the electron concentration in NS channels but increases thermal resistance. A larger S_NS increases the on-state current while compensating for the gate drive loss and mitigating the thermal coupling effect between NS channels but results in longer conduction paths of carriers and heat, which hinders further improvements. Moreover, a suitable W_NS is required to lessen the decline of gate controllability induced by IB channels. Hence, suitable geometry parameters should be selected to achieve a compromise between thermal and electrical performance.

1. Introduction

In order to satisfy the scaling-down demand and to mitigate the short channel effect (SCE), silicon-based multi-gate devices such as FinFETs, GAAFETs, Forksheets and CFETs have been proposed [1,2,3,4,5]. In pursuit of low power dissipation (LP) and high performance (HP) targets as the technology nodes scale down, GAAFETs with unique gate structures are expected to become mainstream devices [6,7,8]. Stacked nanosheet GAAFETs (NSFETs) are one of the most compelling candidates for GAAFETs due to their excellent gate controllability, design flexibility with variable W_NS and high drive current per footprint [9,10,11,12]. To further alleviate the impact of SCE on NSFETs, the overlap structure is used by introducing a barrier between the channel and source/drain, which reduces I_OFF [13].

To improve performance beyond NSFETs, a novel TreeFET device that combines FinFETs and stacked nanosheets was proposed [14]. By using interbridge channels, TreeFETs provide a higher drive current than NSFETs without the additional footprint. Furthermore, TreeFETs are compatible with NSFETs manufacturing process by simply not etching the sacrificial layers completely to form the interbridge, and Chien-Te Tu et al. successfully demonstrated the feasibility and outstanding performance of GeSi-Ge TreeFET in the experiment [15]. Modified devices based on TreeFETs have been reported, such as Si channel tree-shaped junctionless NSFET, Si channel tree-type reconfigurable FETs and Si-SiGe channel Fishbone FETs [16,17,18]. Due to the confined geometry structure of TreeFET, where the NS and IB channels are fully surrounded by the low thermal conductivity gate dielectric, SHE should be thoroughly investigated [19,20,21]. In addition, the increased power density aggravates the heat dissipation of TreeFET.

Since TreeFETs are potential devices for design requirements, it should be of great interest to investigate and co-optimize the electro-thermal performance from the perspective of structural parameters in terms of W_IB, S_NS and W_NS. In this work, the device structure, simulation setup and calibration efforts with the experimental data are given in Section 2. In Section 3, the influence of W_IB, S_NS and W_NS on the electro-thermal performance is thoroughly investigated. Finally, the conclusion is given in Section 4.

2. Device Structure and Simulation Calibration

2.1. Device Structure

Figure 1 shows the structure of the Si-channel TreeFET, and its parameters are listed in

Table 1. Device parameters.

Symbol	Parameter	Value
LG	Gate length	12 nm
TNS	Nanosheet thickness	5 nm
WNS	Nanosheet width	10–40 nm
SNS	Nanosheet space	5–40 nm
WIB	Interbridge width	3–7 nm
LSD	Source/drain length	13 nm
LSP	Spacer length	5 nm
TBulk	Bulk thickness	100 nm
EOT	Equivalent oxide thickness	1 nm
CGP	Contacted gate pitch	48 nm
Nch	Channel doping	1015 cm−3
NSD	Source/drain doping	1021 cm−3
NBulk	Bulk doping	5 × 1018 cm−3

. The simulation was based on the Sentaurus TCAD and performed under the condition of V_GS = V_DS = 0.7 V. Nanosheet thickness (T_NS) was fixed at 5 nm. The source/drain was modeled as a cuboid. TiN with flexible and controllable work function was used as the gate metal [22]. The source/drain contact resistance was set to 1 × 10⁻⁹ Ω cm⁻² [23]. Under the condition of the same EOT (Equivalent oxide thickness), devices with high-k materials suffer from poor heat dissipation due to their small physical thickness and reduced carrier mobility; SiO₂ was chosen as the gate dielectric [24,25]. In order to reduce the impact of random doping fluctuations in the channel on the electrical performance of the device, the doping concentration of the channel and source/drain region is 1 × 10¹⁵ cm⁻³ and 1 × 10²¹ cm⁻³, respectively, and bulk region doping with 5 × 10¹⁸ cm⁻³ was used to suppress the subthreshold leakage [26].

The thermal conductivity of different regions, according to the published work, is shown in

Table 2. Thermal properties.

Material	Thermal Conductivity (WK−1 m−1)
Gate metal (TiN)	19.2
Bulk region (Si)	148
Source/Drain region (Si)	16.61
Channel region (Si)	8.07
Spacer (Si3N4)	18.5
SiO2	1.4

[27]. SHE was investigated in terms of lattice temperature and R_th. The ambient temperature was assumed to be 300 K for the simulated devices under normal operations. Affected by phonon boundary scattering and interface traps, the hetero-interfacial-thermal resistance (HITR) of Si/SiO₂ was set as 2 × 10⁻⁴ cm²K/W [28,29]. Referring to the thermal resistance of BEOL at different VIA densities in 14 nm FinFET, the initial boundary thermal resistance at the gate, source and drain were 2 × 10⁻⁶ cm²K/W, and the conventional measurement configuration was set up, and the substrate was set up as the main heat dissipation path [30].

2.2. Calibration

In order to ensure the accuracy of the simulation and calculation, the density gradient model was adopted for the quantum confinement effect. The Philips unified mobility model was used to account for the effects of electron–hole scattering, lattice scattering and ionized impurity scattering. Thin-layer mobility model and enhanced Lombardi model were adopted to account for the effects of phonon boundary scattering and surface roughness scattering. The extended Canali model was considered to account for degraded mobility under the effects of high-field velocity saturation. Moreover, the Shockley–Read–Hall recombination model with doping dependence is adopted, and the thermodynamic model and diffusion–drift model were considered for SHE.

The experimental data used for calibration come from the IBM Stacked Nanosheet Gate-All-Around Transistor, and the calibration data are shown in Figure 2 [9]. For I–V calibration to reflect the true performance measurement of the data, the work function of the metal gate and the saturation velocity was adjusted to match the experimental data in the subthreshold region and saturation region. Note that the TreeFET without IB channels (NSFET) was used in the calibration. After the I_d-V_g curve was accurately matched with the experimental data, the IB channels were added for subsequent experiments.

3. Investigation of Electrical and Thermal Characteristics

3.1. Impact of IB Width

The impact of W_IB on the electrical characteristics with different S_NS at W_NS = 20 nm is illustrated in Figure 3. I_ON and I_OFF with various W_IB are shown in Figure 3a,b, respectively. At each fixed S_NS, it is observed that I_ON rises with the decrease in W_IB, and I_OFF increases with W_IB increasing. The wider channel width reduces the potential barrier height in the conduction band energy of the channel, resulting in an increase in I_OFF. The ON/OFF current ratio (defined as log10 (I_ON/I_OFF)) and SS under different W_IBs are shown in Figure 3c,d. I_ON/I_OFF is larger, with improved SS for smaller W_IB. A narrow W_IB helps to improve the inversion in the channels, which results in the improvement of the gate control ability. However, TreeFET with smaller W_IB suffers more surface scattering and quantum confinement effects, which impedes performance improvement.

Figure 4 shows the electron density of channel cross sections with different W_IB at 3/5/7 nm. Note that the trend of electron density in channel cross sections with different widths is similar for different S_NS; S_NS = 15 nm is selected to demonstrate the variation in electron density. As indicated in Figure 4, although the wider W_IB has a larger channel cross-sectional area, which reduces the equivalent resistance in the IB channel region, the distance between the side gate and the connections of NSs and IBs increases, and the gate at the corners needs to control both IBs and NSs, resulting in a decrease in the gate control capability and the electron density of the inversion layer in connections and corners. Moreover, it was found that the electron density of the center of the middle NS is seriously degraded due to the connection of IBs, compared with the top and bottom NSs.

TreeFET with W_IB = 3 nm has better gate control ability, but its IB channels turn on later than TreeFET with W_IB = 5 nm due to the quantum confinement effect and more surface roughness scattering. The threshold voltage (V_th) is extracted by the constant current criterion (I_con = 100 nA). Figure 5 shows the electron density of channel cross sections with different W_IB = 3/5 nm when S_NS = 15 nm at different overdrive voltages (V_OV, V_OV = V_GS − V_th). As shown in Figure 5a, when V_OV = 0.1 V, the electron density of NS channels in TreeFET with W_IB = 3 nm is larger than that of IB channels. Moreover, the electron density of IB channels is lower compared to TreeFET with W_IB = 5 nm, which implies that TreeFET with smaller W_IB has a higher threshold voltage. Note that the connection of middle NS at W_IB = 3 nm has a larger electron density than that of W_IB = 5 nm. As the gate voltage increases to V_OV = 0.5 V in Figure 5b, more electron concentrates in all channels, and the electron density of 3 nm IB channels exceeds that of 5 nm IB channels because of better gate control.

The total line electron density (N_ed) is obtained by integrating the electron density over the entire channel region. As shown in Figure 6, the N_ed is compared with different W_IBs. As W_IB increases from 3 nm to 5 nm, N_ed drops by 19.4%, and the electron density in the IB channel region decreases from 27.6% to 25.3% of the total channel region. Therefore, to achieve good electrical performance, it is necessary to maintain a W_IB of 5 nm or less.

3.2. Impact of NS Space

Figure 7 shows the impact of S_NS on the electrical characteristics with different W_IB at W_NS = 20 nm. As shown in Figure 7a,b, both I_ON and I_OFF increase with the increase in S_NS at fixed W_IB, which is mainly attributed to the increased cross-sectional area of the channel region. Note that the increasing trend of I_ON slows down with the increase in S_NS and Slope1 > Slope2 > Slope3. It can be seen from Figure 7c that when the W_IB is smaller than 5 nm, the ON/OFF current ratio shows an upward trend with the increase in S_NS, and when the W_IB is larger than 5 nm, the trend is the opposite. This phenomenon can be attributed to the fact that the increase in S_NS makes the increase in I_OFF much higher than I_ON when W_IB is larger than 5 nm. Figure 7d shows that SS decreases with the increase in S_NS due to the better gate control ability in IBs under the condition of higher S_NS.

Figure 8 shows the electron density of channel cross sections with different S_NS at 10/20/40 nm at V_GS = V_DS = 0.7 V, and Figure 9a shows the N_ed is compared when W_NS = 20 nm. Figure 10 illustrates the electric field of channel cross sections at S_NS = 10/20/40 nm, and the inset shows the short and long carrier paths at different S_NS, respectively. A median W_IB = 5 nm is chosen in Figure 8, Figure 9 and Figure 10. It can be observed that with the increase in S_NS, more electrons concentrate in the top NS and both IBs, and N_ed rises slightly in the middle NS while remaining almost invariable in the bottom NS and even drops at S_NS = 40 nm. The IB channels have a larger contact area with the spacer and the source/drain (S/D) as S_NS increases, which has smaller extension resistance, contact resistance, surface scattering and a better gate control capability, which leads to a larger N_ed. Figure 9b illustrates the proportion of IB current to the total current and total NS current. Note that the total current is the sum of the total NS current and total IB current. The increase in S_NS makes the channel area increase and resistances decrease. It can be observed that the IB current ratio is 17.4%/33.8%/54.1% at S_NS = 10/20/40 nm, respectively. The total NS current rises by 14% with the increase in S_NS from 10 nm to 20 nm but decreases by 11.5% from 20 nm to 40 nm. However, as shown in Figure 10, as S_NS continues to increase, the S/D parasitic series resistance (R_S/D) increases due to the increased height of the S/D region, the voltage of the bottom channel is divided, and the top channel has a larger potential difference than the bottom channel and has a higher electric field intensity [31]. This is the reason why the N_ed of the upper part in IB is higher than the lower part, and the N_ed of the bottom NS is reduced at S_NS = 40 nm. Moreover, the channel with a long distance from the S/D contact further hinders its performance improvement due to its longer carrier path and increased R_S/D, resulting in the uptrends of I_ON in Figure 7a and IB current ratio in Figure 9b slowing down with the increase in S_NS and causing the total NS current to decrease at S_NS = 40 nm.

3.3. Trade-off of Electro-Thermal Performance

The temperature distribution of N-type NSFET and TreeFET is shown in Figure 11, and T_peak is defined as the peak temperature of the channel cross section. It can be seen from Figure 11a,b that T_peak locates at the channel region near the drain side. The electric field intensity at the drain side is larger at V_GS = V_DS = 0.7 V. Moreover, confined by the gate dielectric material with low thermal conductivity (K_SiO2 = 1.4 WK⁻¹ m⁻¹) and Si/SiO₂ thermal boundary resistance, maximum lattice temperature (T_{L, MAX}) is usually at the boundary between the channel and drain. Therefore, the TreeFET, as a similar structure to the NSFET, which has a larger I_ON and more heat generation per footprint, suffers severe self-heating effects.

Figure 12a,b show T_{L, MAX} and R_th (defined by R_th = (T_{L, MAX} − T_ambient)/(V_DS × I_DS), T_ambient = 300 K) of different S_NS at W_IB = 3/4/5 nm. It can be seen that T_{L, MAX} increases with the increase in S_NS and the decrease in W_IB, which is mainly due to the increase in I_ON. As the W_IB decreases, the thermal resistance increases due to the intensified phonon-boundary scattering, while as the W_IB increases, the cross-sectional area of the IB increases, which improves the heat dissipation towards BEOL and increases the heat flux exchange among channels.

As S_NS increased, R_th rapidly decreased and then increased. Part of the heat is conducted through S/D to the BEOL; the substrate is the main heat dissipation path, and the other part is conducted through the gate dielectric layer, metal gate and spacer area between the channel layer. Thus, a severe thermal coupling effect exists [32,33,34]. The thermal coupling effect is weakened with the increase in S_NS due to the increase in IB, which connects NSs and conducts heat. Moreover, the increasing temperature degrades the thermal conductivity of Silicon material. Heat is mainly dissipated through the bulk and substrate. As the S_NS continues to increase, the overall thermal conduction path of the channel becomes longer, which causes worse heat dissipation and results in more total heat generating in the top channel and the increase in R_th, as shown in Figure 11c and Figure 12b, respectively.

Figure 13 shows the thermal properties of the DC power of the device. Figure 13a shows the curve of ΔT and DC power of TreeFET under different IB parameters, where ΔT = T_{L, MAX} − T_ambient, P = V_DS × I_DS, and the slope represents the thermal resistance of the device at this power. It can be observed in Figure 13a that TreeFET with a larger W_IB and S_NS has a smaller thermal resistance. Moreover, with the increase in power, lattice temperature rises, and the phonon scattering intensifies, which leads to the degradation of the thermal conductivity of silicon material. Figure 13b–e show the thermal distribution of TreeFET with different W_IB and S_NS at the same power of 80 μw. As shown in Figure 13b,c, with the same W_IB = 3 nm, TreeFET with S_NS = 5 nm has a higher lattice temperature. Additionally, as the S_NS increases to 20 nm, the thermal coupling effect is weakened, and the self-heating effect is improved, which results in a lower lattice temperature. As shown in Figure 13c,d, when the W_IB increases from 3 nm to 5 nm, the heat dissipation capability of the device is enhanced, the thermal resistance is reduced, and the lattice temperature is decreased. Note that with the increase in S_NS, the T_peak of the device gradually moves towards the center of the device. Figure 13d,e show that as the S_NS increases from 20 nm to 40 nm, the average heat dissipation path of the channel increases, and the heat dissipation capacity degrades.

In summary, a wide W_IB is favorable for heat dissipation capability, and a narrow W_IB has a better gate control capability but suffers from a greater quantum confinement effect. A suitable S_NS is key to achieving good electro-thermal performance, but a too-large S_NS also leads to an increase in thermal resistance and a low space utilization where an additional nanosheet can be stacked as an alternative. Therefore, S_NS should be 20–30 nm to reach the compromise of electro-thermal performance.

3.4. Impact of NS Width

NSFET has a continuous range of active widths for additional design flexibility. TreeFET retains the unique advantages of NSFET, which can maximize the effective channel width (W_eff) in the same footprint.

The simulations with various W_IB and S_NS under the conditions of different W_NS (W_NS = 10/20/30/40 nm) are investigated. All devices require narrower and higher IB to maintain a good gate control capability. W_SW = W_IB/W_NS is defined as the specific width. Figure 14 shows the schematic diagram of the specific width and NS total line electron density degradation. As shown in Figure 14a, the electron concentration in the NS channels is more sensitive to the change in W_IB with a smaller W_NS and a larger W_SW. TreeFET with a larger W_SW and a smaller W_NS at the same W_IB has a larger proportion of electron concentration degradation in the NS channels shown in Figure 14b.

Figure 15 shows I_ON, total IB electron density, total NS electron density and R_th with different S_NS under the condition of different W_NS = 10/20/30/40 nm and W_IB = 4 nm. Note that I_ON and total NS electron density are normalized by the W_NS. As shown in Figure 15a,b, the total IB electron density is less affected by W_NS and TreeFET, with smaller W_NS having larger I_ON per footprint due to better gate control capability and additional IB channels. Figure 15c shows the impact of the normalized total NS electron density with the different IB channels. As S_NS increases, the degradation of electron density improves. For W_NS = 10 nm, although it has the highest total NS electron density without IB, the presence of the IB channels severely impairs the gate control capability of NS channels, leading to a sharp drop in total NS electron density. As shown in Figure 15d, the trend of thermal resistance with S_NS and W_NS is similar to that shown in Figure 12b. With the increase in W_NS, the cross-sectional areas of the channel regions increase, which enhances the heat dissipation capacity of the device and decreases R_th. The heat dissipation capacity of the device tends to be gradually saturated, which is less affected by the IB channel and S_NS. The thermal resistance R_th of the device decreases with the increase in W_NS, and the heat dissipation capability of the device gradually tends to be saturated, which is less affected by variation in W_IB and S_NS.

Figure 16 shows the cutline in the center of the middle NS channel and the distribution of electron density along the cutline with different W_NS under S_NS = 20 nm. It can be seen that since the middle NS channel is connected to two IB channels, the electron density at the center of the NS channel is significantly reduced due to the reduction in the gate control capability. Moreover, the peak of electron density in the center of the NS channel of the device with W_NS = 10 nm is smaller compared with TreeFET with W_NS = 20/40 nm due to the larger W_SW, which also explains the phenomenon of Figure 15c. Therefore, devices with different W_NSs also require a suitable S_NS to maintain the electro-thermal properties.

In summary, TreeFET has a higher normalized current per footprint when the W_NS is small, but the IB channels seriously deteriorate the gate control ability of the NS channel. Therefore, W_NS should be at least greater than 10 nm, and W_SW should be small. When the W_NS is larger, the thermal resistance is lower, and the gate control capability of NS channels is weakened, which has little influence on the IB channels. W_NS provides a choice to make trade-offs between thermal properties and electrical performance.

4. Conclusions

In this work, TreeFET with different geometry parameters is systematically investigated by TCAD simulation. The investigation of the electro-thermal properties of the device is discussed by adjusting W_IB, S_NS and W_NS. The results show that a smaller W_IB and a higher S_NS improve the SCE, which avoids the gate control capability degradation of the NS channel. On the other hand, a higher S_NS increases I_ON and improves the heat dissipation capability, but longer carrier paths for bottom-side channels and heat conduction paths for middle-side channels hinder further improvements in electro-thermal performance. In addition, a suitable W_NS and W_SW are required to maintain high electron density in NS channels. To pursue better electro-thermal performance, W_IB should be 5 nm or less, S_NS should be 20–30 nm, and W_NS should be at least larger than 10 nm. These characteristics indicate that the TreeFET can become a promising alternative device for further performance optimizations, and the systematic investigation lays a foundation for design requirements. The reasonable geometric parameters are expected to be selected flexibly in different applications.