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Article

A Multiple Interpolation Algorithm to Improve Resampling Accuracy in Data Triggers

by
Mengtao Cao
1,2,
Fangyuan Xu
1,2,
Hanbo Jia
2,*,
Lei Zhou
3,
Eryou Ji
3 and
Jin Wu
3,*
1
University of Chinese Academy of Sciences, Beijing 100049, China
2
Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
3
Acela Micro Company Limited, Suzhou 215124, China
*
Authors to whom correspondence should be addressed.
Electronics 2023, 12(6), 1291; https://doi.org/10.3390/electronics12061291
Submission received: 3 February 2023 / Revised: 3 March 2023 / Accepted: 6 March 2023 / Published: 8 March 2023
Browse Figures
Versions Notes

Abstract

:
To address the problem of low trigger accuracy during trigger resampling and variable sampling rate trigger resampling using a fixed sampling rate analog-to-digital converter (ADC), this paper proposes an interpolation method combining sinc interpolation and linear interpolation to improve accuracy, based on a digital trigger. After behavior simulation verification and actual field programmable gate array (FPGA) test verification, the data collected by two 3GSps 12-bit ADCs were subjected to 8-times sinc interpolation followed by 16-times linear interpolation processing, after which the original trigger resampling accuracy was increased by 128 times and the sampling rate could be realized to vary between 100 MHz and 1 GHz. A signal–noise ratio (SNR) of 46.80 dBFS, a spurious free dynamic range (SFDR) of 45.91 dB, and an effective number of bits (ENOB) of 7.48 bits were obtained by direct trigger resampling without algorithm processing in the behavior simulation. Meanwhile, an SNR of 58.98 dBFS, an SFDR of 60.96 dB, and an ENOB of 9.42 bits were obtained by trigger resampling after algorithm processing. Due to the influence of analog link signal loss and signal interference on the development board, an SNR, SFDR and ENOB of 51.97 dBFS, 61.26 dB, and 8.32 bits, respectively, were obtained from the trigger resampling in the FPGA test. The experimental results show that the algorithm has not only improved the triggering accuracy but has also improved the SNR, SFDR, and ENOB parameters.

1. Introduction

In the current scientific field, measurement is the process by which scientific researchers obtain specific values for objective things to understand a process. With the development of technology, people have officially entered the electronic age from the electrical age. With the development of the electronic age, major changes have taken place in weaponry, communications, aerospace, and medical care. Testing signals is characterized by more and more complex time-domain signals, higher and higher frequencies to be tested, and higher and higher requirements for measurement. A trigger is the key to capturing a signal in a timely and accurate manner [1]. Methods of triggering are divided into digital triggering and analog triggering. Compared with digital triggering, due to the inconsistency of the noise source, analog triggering has a relatively large jitter when measuring high-speed signals, and the accuracy of triggering is also limited by the performance of analog devices. With the improvement of trigger accuracy requirements, digital triggers are increasingly becoming the first choice.
An oscilloscope as one of the most widely used time-domain measuring instruments. The triggering function is the key performance of an oscilloscope. It enables the oscilloscope to isolate specific signal events for detailed analysis and to realize the stable display of a repeated waveform. Optical coherence tomography (OCT) is an imaging technique used in industrial and clinical applications [2], requiring high trigger accuracy and the implementation of variable sampling rates for data acquisition.
Most of the signals to be measured today are continuously changing analog quantities [3], but most of the information to be processed is digital. It is necessary to convert the analog signal quantities into digital ones, which requires the use of analog-to-digital converters (ADC). The interaction between the analog and digital worlds has been a challenge [4]. ADCs act as a bridge between analog and digital signals [5], transforming analog signals that vary continuously in both the time domain and amplitude at the input into equivalent digital signals that are discrete in the time domain and quantized in amplitude [6,7]. After ADC conversion, the generated digital signal is further processed using digital signal processing (DSP) or a microcontroller unit (MCU) [8].
In the process of data acquisition using ADCs, the time interval of data acquisition is limited by the sampling rate of the ADC. To improve the accuracy of data acquisition without changing the sampling rate, interpolation processing is often used to process the data. The interpolation algorithm is a method for evaluating the function value for any intermediate value of the self-adjusting variable [9], and the main function of interpolation is to improve the resolution of the curve to make it closer to the real waveform [10]. Among the interpolation methods, sinc interpolation is theoretically the best, and the use of sinc interpolation does not distort the signal of the sample [11,12]. However, sinc interpolation is more resource intensive, so its number of interpolation multiples is typically limited by controller resources. Linear interpolation, compared to the sinc interpolation approach, uses first-order linear equations to calculate linearly interpolated data from the two closest data points, which is relatively fast and consumes fewer resources to process, but introduces a large number of interpolation errors [13]. Therefore, linear interpolation is not suitable for achieving high-accuracy interpolation processing.
Many attempts have been made to improve the accuracy of data acquisition by using interpolation algorithms for data processing, among which Vinzenz Bandi et al. designed an SS-OCT data acquisition system with two input channels for data acquisition at a sampling rate of 500 MHz, and used linear interpolation processing for the acquired data so that the rate of an A-scan could reach 100 KHz [14]. A. Bossen et al. used non-uniform fast Fourier variation for the data acquired by OCT to process the data in real-time, which can be done at a sampling rate of 100 MHz and the rate of an A-scan can reach 50 KHz [15]. Baptiste Joly et al. used cubic spline interpolation for the data acquired by a time of flight (TOF) acquisition system, which allows the resolution of data acquisition in the interval of 200–300 ps [16]. Tao Han et al. proposed a spline interpolation for spectral resampling in swept-source OCT (SS-OCT), which was used to improve the resolution of data acquisition and the signal-to-noise ratio after data acquisition [17]. Y.sun et al. used one-dimensional spline interpolation to reduce the triggering time interval of the virtual oscilloscope from 12.5 ns to 0.1 ns [18]. K.park used interpolation processing to reduce the trigger time interval of the oscilloscope from 4 ns to 7.8 ps [19]. C.F. Ye et al. used FPGA to implement an interpolation algorithm to reduce the trigger time interval of a time-of-flight mass spectrometer to 390 ps [20]. But in the current high-precision trigger resampling application scenario, where the trigger signal rate can reach the level of GHz, the use of a MHz-level sampling rate cannot meet the current application requirements of the environment, while trigger sampling accuracy requirements have reached a single ps level for the sampling rate, and interpolation has high requirements.
In today’s common high-precision trigger resampling application scenarios, such as oscilloscopes, mass spectrometers not only have strict requirements for trigger accuracy, but also have requirements for real-time data processing. With the advancement of very large-scale integration (VLSI) technology, FPGA chips have larger capacity, higher performance and lower power consumption than before, making FPGA the best choice for current control and algorithms [21]. Compared with application-specific integrated circuits (ASIC), FPGA have great advantages in speed, precision and flexibility [22]. Traditional ASIC can only implement a specific function, but FPGA has reconfigurable characteristics, making its design very flexible [23,24]. Designers can flexibly configure and adjust according to the performance and efficiency required by users [25,26]. Compared with traditional ASIC, the design, implementation, and testing cycle of designers on FPGA may only take a few hours, while it may take months on ASIC [27]. Compared with custom dedicated chips, FPGA has a lower design cost [28]. At the same time, compared with using a central processing unit (CPU) or graphics processing unit (GPU) for data processing, FPGA can process data in real time.
The traditional increase in trigger resampling is mostly an interpolation method. Where the improved effectiveness of an interpolation method is large relative to the consumption of resources, if an interpolation method with less resource consumption is used, it will introduce a relatively large interpolation error. To get a better interpolation effect with less resource consumption, an interpolation method combining sinc interpolation and linear interpolation is proposed in this paper to improve the accuracy of trigger resampling. This combines the advantages of small sinc interpolation errors and the simplicity of linear interpolation processing. Firstly, the sinc interpolation with a relatively small error is performed, and then the linear interpolation is performed on this basis. We achieved better interpolation results with relatively small resource consumption.
In this paper, the overall algorithm architecture is given in Section 2 to describe the principle of algorithm implementation. The resampling performance comparison under different sinc interpolation multipliers and different filter parameters is given in Section 3. The root mean square (RMS) [29] values of the trigger point and ideal trigger point under different sinc interpolation multipliers and different filter parameters are given in Section 4. The performance and RMS data of resampling after sinc interpolation and linear interpolation processing are given in Section 5. The results of actual tests are given in Section 6. The conclusions are given in Section 7.

2. Principles of Overall Algorithm Design

2.1. Principle of High-Precision Trigger Resampling

Trigger acquisition is only carried out when the trigger conditions are met, and data that do not meet the trigger conditions are discarded. In this design, data acquisition is required when the signal of the trigger channel passes through the zero point, so the trigger mode selected is the edge trigger. When the data of the trigger channel change from a negative number to a positive number, the trigger data is collected. The schematic diagram of trigger collection is shown in Figure 1.
In this design, to reduce the resources consumed, only when the trigger condition is satisfied does the data need to be saved, and only the data that satisfy the trigger condition are targeted when the data are interpolated and processed. The data that meet the trigger conditions are kept in the collected raw data, and data are inserted into the two reserved raw data. The trigger signal and valid data in the original data and the inserted data are re-found to obtain the final required valid data. A schematic diagram of the process is shown in Figure 2.
According to the ideal edge trigger situation, the data to meet the edge trigger should be at the location of the value of 0. However, in the actual situation, it is difficult to pick up the data at 0, so we can only find the data closest to 0 as the trigger signal. As can be seen from Figure 2, after interpolation of the original data compared with the original trigger signal, the interpolated data are closer to 0, and the saved data are more accurate and closer to the data we need. The trigger situation after interpolation is shown in Figure 3.

2.2. The Principle of Combining Sinc Interpolation and Linear Interpolation

Sinc interpolation is a commonly used interpolation process, and the error of sinc interpolation shows an exponential convergence to zero with the increase of the interpolation base [30]. However, it is not possible to use infinite data to fit the interpolated data in practical applications, and finite-length data are used to fit the interpolated data in practical applications. When finite-length data are used to fit the interpolation points, truncation errors are introduced [30], so it is necessary to choose the appropriate sinc interpolation multiplier and finite-length data. The selection of the sinc interpolation multiplier and the selection of the fitted data are described in Section 3 Linear interpolation only uses adjacent interpolation bases for interpolation processing [10], which is relatively simple to calculate. The combination of sinc interpolation and linear interpolation in this design is shown in Figure 4.
Figure 4 divides the overall interpolation algorithm into three parts. The first part saves the data that satisfy the edge trigger in the collected raw data and selects the data of suitable length for sinc interpolation data fitting. The second part is to perform sinc interpolation on the finite-length data selected, find again the data that meet the edge trigger after sinc interpolation, and save the data. The third part is to perform linear interpolation on the data saved in the second part and find the data that meet the edge trigger in the data after the linear interpolation process, which is the final required data.

2.3. Principle of Waveform Reconstruction after Resampling

Under the condition of trigger acquisition, the data obtained after resampling are separate data, and the separate data obtained after resampling need to be stitched into continuous waveform data during the subsequent data processing. If, in the original data that meet the edge-triggered data, there is a temporal relationship, then the data obtained after resampling should also be restored in accordance with the order of edge triggering. Resampling data recovery can be divided into three steps:
(1)
Determine the data that meet the edge trigger in the finite length of the original data, and record them in the order of time.
(2)
Save the resampled data obtained after the sinc interpolation and linear interpolation processing.
(3)
The resampled data after sinc interpolation and linear interpolation are stitched together in the order of the trigger signals in the original data.
As shown in Figure 5a,b, there are four trigger points in the trigger signal channel, which are located at the 2nd, 6th, 11th, and 15th data points in the trigger signal data channel. After trigger resampling, the four resampling data points can be obtained, and the time domain waveform of data stitching after resampling should be as shown in Figure 5b to obtain the required resampling waveform according to the sequence of the trigger signal in time.

3. Performance Comparison under Different Parameters

In the sinc interpolation process, the interpolated data have the problem of mirror spectrum. In order to address the effect of the mirrored spectrum, it is necessary to design a suitable filter to eliminate the mirrored spectrum. In this design, the interp function in MATLAB is used to design the sinc interpolation. The interp function completes the sinc interpolation process according to the interpolation multiplier and the parameters of the filter. In this design, the results of sinc interpolation are compared from two aspects. Firstly, the performance of the interpolation multiplier of 2/4/6/8/10 is compared under the condition that the filter parameters are default, and the appropriate interpolation multiplier is selected. Then, the appropriate filter parameters are selected according to the determined interpolation multiplier to complete the overall selection of interpolation multiplier and filter parameters for sinc interpolation. This section focuses on the performance corresponding to different interpolation multiples under the condition that the filter parameters are default, and Section 4 focuses on the performance corresponding to different filter parameters under the selected interpolation multiples. The performance comparison is mainly shown by taking a 701 MHz-resampled 15 MHz signal as an example. Table 1 shows the performance of resampling the 15 MHz signal without using the algorithm to process the 701 MHz signal, Figure 6a shows its corresponding spectrum, and Figure 6b shows the time domain waveform recovered after resampling.
Figure 7a shows the comparison of the performance parameters of the filter parameters in the default state with the interpolation multiplier of 2/4/6/8/10. The specific performance parameters are given in Table 2, from which we can see that the performance is gradually getting better with the increase in the interpolation multiplier, and the overall performance is the best when the interpolation multiplier is 8.
Figure 7b shows the comparison curves of the performance under the condition of 8-times interpolation. Changing the filter parameters, the filter parameters are 2/4/6/8/10, and the specific corresponding performance parameters are given in Table 3. With the filter parameters increasing, the overall performance is gradually getting better. In the actual application process, considering the complexity of the implementation and the consumption of resources, at the filter parameters of 6 the performance parameters have met the needs of this design. Therefore, the condition of filter parameter 6 is selected for the sinc interpolation in this design.

4. RMS Values for Different Conditions

The interpolation algorithm is mainly used to improve the accuracy of resampling. Under ideal conditions, the location of the trigger resampling in this design should be at the location of data 0. Due to several limitations, it is impossible to collect the location of data 0 in the actual situation. As such, the purpose of using interpolation algorithm processing is to make the data meet the trigger conditions after processing as close as possible to 0. In order to compare the size of the data satisfying the trigger condition after processing by the interpolation algorithm compared to zero, the root means square (RMS) values are calculated for the combination of the data satisfying the trigger condition. Figure 8a shows the RMS values of the trigger condition data after processing with different sinc interpolation multipliers with default filter parameters. Figure 8b shows the RMS values of the data satisfying the trigger condition after processing with different filter parameters for a sinc interpolation multiplier of 8.
From Figure 8a,b, it can be seen that the RMS values obtained with a sinc interpolation multiplier of 8 and a filter parameter of 6 are significantly lower than those obtained without the interpolation algorithm, which proves that the data satisfying the trigger conditions at this time have a small error compared to the ideal conditions. Therefore, combining the performance and RMS values obtained with different sinc interpolation multipliers and different filter parameters, we chose the condition that the sinc interpolation is 8 times the interpolation multiplier and the filter parameter is 6.
Figure 9a shows the spectrum obtained by resampling the 15 MHz signal after sinc interpolation using 701 MHz at a sinc interpolation multiplier of 8 and a filter parameter of 6. Figure 9b shows the time domain waveform obtained by resampling under such conditions. Figure 10 shows the frequency response of the filter under such conditions.

5. The Performance of the Algorithm after Processing

In order to reduce the trigger time accuracy to the ps level, this project used a 3GSps 12-bit ADC for data acquisition, which cannot reach the set demand after 8 times sinc interpolation, so linear interpolation was performed again after the sinc interpolation, and the trigger accuracy was reduced to about 42 ps after 8 times sinc interpolation. To obtain a trigger accuracy in ps units, the linear interpolation process was performed on this basis 16 times, so that the trigger accuracy reached about 2.6 ps.
Figure 11a shows the RMS values of the trigger data after adding 16 times of linear interpolation at different sinc interpolation multipliers. In Figure 11a, it is obvious that the RMS values after adding linear interpolation have significantly decreased compared with those after only sinc interpolation, which proves that the data satisfying the trigger condition tend to zero. Figure 11b shows the various performance parameters for the three different resampling methods. The three resampling methods are: direct resampling without interpolation processing, resampling after sinc interpolation processing, and resampling after sinc interpolation and linear interpolation. It can be seen from Figure 11b that compared with directly resampling without interpolation processing, the other two resampling methods have a great improvement on various performance parameters. Although the performance of resampling with linear interpolation is slightly worse than that of only sinc interpolation, there is a significant improvement in trigger accuracy. Combined with test results and resource consumption, the overall structure of this interpolation algorithm is 8 times sinc interpolation and 16 times linear interpolation.
The spectrograms and recovered time domain waveforms obtained by resampling after combining 8-fold sinc interpolation and 16-fold linear interpolation are given in Figure 12a,b, respectively, and the performance tables after resampling are given in Table 4. Table 5 shows the simulation test results under additional different frequency points.

6. Actual Test Results

The actual verification used Xilinx xc7k480tffg1156-2 FPGA; two Ceyear 1435B signal generators, which can generate waveform signals from 9 KHz to 6 GHz; the AcelaMicro production of the AAD12S3000 data acquisition chip; and an independent-design ADAQ1004 data acquisition board. Figure 13 shows the actual test environment. Table 6 shows the consumption of main resources of this algorithm in FPGA.
The signal generator 1 generates 701 MHZ and 351 MHz trigger signals, the signal generator 2 generates 15 MHZ data signals, data acquisition and processing occurs through acquisition card 3, and the computer 4 displays the waveform after resampling.
Figure 14 shows the recovery graph of the time domain waveform resampled at 701 MHz to 15 MHz in the actual test. From the waveform, it can be seen that it is consistent with the results of behavior simulation, which verifies the correctness of the resampled time domain waveform recovery in the actual test.
Table 7 shows the performance results of the actual test. Figure 15a,b show the spectrogram and recovered time domain waveform obtained by resampling 15 MHz at 701 MHz in the actual test, respectively. From the spectrum, we can see that the results are consistent with the previous simulation, and the attenuation amplitude of the remaining frequency points, except for the main frequency, is below −60 db, which meets the overall design requirements. Since there are few detailed data of other works to compare, a horizontal comparison of detailed data was not carried out here.

7. Conclusions

This paper proposes an interpolation method combining sinc interpolation and linear interpolation to improve the trigger accuracy for the application scenarios of high-precision trigger acquisition and high-precision trigger acquisition with a variable sampling rate, and describes the way to recover the waveform after trigger resampling, completing the closed-loop design from behavior-level simulation to practical application. The method of this design was finally verified and implemented on FPGA. After actual verification, under the condition of using a 3GSps 12-bit ADC for data acquisition, the algorithm reached 51.97 dBFS for SNR, 61.26 dB for SFDR and 8.32 bits for ENOB when resampling a 15 MHz signal using a 701 MHz signal. The algorithm proposed in this paper can further improve the performance results after resampling by increasing the sinc interpolation multiplier and the order of the filter when the amount of resources is large enough, and the algorithm can be applied not only to two data channels but also to data with multiple channels.

Author Contributions

M.C. proposed the idea of the algorithm and implemented it, measured the data, and wrote the manuscript, L.Z. and E.J. refined the algorithm, F.X., L.Z., E.J., H.J. and J.W. reviewed the article and suggested changes. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by Key Research and Development Plan of Shandong Province, China, grant number 2022CXGC010107, and Youth Innovation Promotion Association, Chinese Academy of Sciences, grant number 2021113.

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Gao, L.Z.; He, B.J.; Yang, J.X. Design and implementation of advanced triggering in Digital Phosphor Oscilloscope. In Proceedings of the Icemi 2007: Proceedings of 2007 8th International Conference on Electronic Measurement & Instruments, Xi’an, China, 16–18 August 2007; IEEE: New York, NY, USA, 2007; Volume I, pp. 644–647. [Google Scholar]
  2. Deterre, R.; Khatibi, R.; De Montigny, E.; Khalid, M. High-speed complete optical coherence tomography signal processing solution. In High-Speed Biomedical Imaging and Spectroscopy: Toward Big Data Instrumentation and Management II; SPIE: San Francisco, CA, USA, 2017; Volume 10076. [Google Scholar] [CrossRef]
  3. Wang, J. Analog-to-Digital Conversion Technology and Its Developing Trend. Microelectronics 2005, 35, 221. [Google Scholar]
  4. Homulle, H.; Visser, S.; Charbon, E. A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications. Ieee Trans. Circuits Syst. I Regul. Pap. 2016, 63, 1854–1865. [Google Scholar] [CrossRef] [Green Version]
  5. Zheng, Y.Z.; Zhao, Y.J.; Zhou, N.X.; Wang, H.J.; Jiang, D.Y. A short review of some analog-to-digital converters resolution enhancement methods. Measurement 2021, 180, 109554. [Google Scholar] [CrossRef]
  6. Yuanyuan, Z.; Yanfeng, J. An Overview of Sigma-Delta Analog-to-Digital Converter. Microelectronics 2006, 36, 456–460. [Google Scholar]
  7. Alegria, F.C.; Serra, A.C. ADC transfer curve types—A review. Comput. Stand. Interfaces 2006, 28, 553–559. [Google Scholar] [CrossRef]
  8. Chen, D.D.; Cui, X.H.; Zhang, Q.D.; Li, D.; Cheng, W.Y.; Fei, C.L.; Yang, Y.T. A Survey on Analog-to-Digital Converter Integrated Circuits for Miniaturized High Resolution Ultrasonic Imaging System. Micromachines 2022, 13, 114. [Google Scholar] [CrossRef]
  9. Kannan, E.P.; Vinsley, S.S.; Chithra, T.V. Medical Image Demosaicing Based Design of Newton Gregory Interpolation Algorithm. Intell. Autom. Soft Comput. 2022, 34, 1675–1691. [Google Scholar] [CrossRef]
  10. Xu, P.F.; Jia, Y.J. SNR improvement based on piecewise linear interpolation. J. Electr. Eng. Elektrotech. Cas. 2021, 72, 348–351. [Google Scholar] [CrossRef]
  11. Yaroslavsky, L. Boundary effect free and adaptive discrete signal sinc-interpolation algorithms for signal and image resampling. Appl. Opt. 2003, 42, 4166–4175. [Google Scholar] [CrossRef]
  12. Yaroslavsky, L. Fast signal sinc-interpolation methods for signal and image resampling. Image Process. Algorithms Syst. 2002, 4667, 120–129. [Google Scholar] [CrossRef]
  13. Chan, K.K.H.; Tang, S. High-speed spectral domain optical coherence tomography using non-uniform fast Fourier transform. Biomed. Opt. Express 2010, 1, 1309–1319. [Google Scholar] [CrossRef] [PubMed] [Green Version]
  14. Bandi, V.; Goette, J.; Jacomet, M.; von Niederhausern, T.; Bachmann, A.H.; Duelk, M. FPGA-Based Real-Time Swept-Source OCT Systems for B-Scan Live-Streaming or Volumetric Imaging. In Optical Coherence Tomography And Coherence Domain Optical Methods in Biomedicine XVII; SPIE: San Francisco, CA, USA, 2013; Volume 8571. [Google Scholar] [CrossRef]
  15. Bossen, A.; Remund, S.; Ernst, D.; Meier, C.; von Niederhausern, T.; Duelk, M.; Vemishetty, K. FPGA-Based Non-Uniform Fast Fourier Transform (NUFFT) Algorithm for Real-Time OCT Signal Processing. In Optical Coherence Tomography and Coherence Domain Optical Methods in Biomedicine XVII; SPIE: San Francisco, CA, USA, 2013; Volume 8571. [Google Scholar] [CrossRef]
  16. Joly, B.; Montarou, G.; Vert, P.E. Sampling Rate and ADC Resolution Requirements in Digital Front-End Electronics for TOF PET. IEEE Trans. Nucl. Sci. 2017, 64, 2543–2550. [Google Scholar] [CrossRef]
  17. Han, T.; Qiu, J.R.; Wang, D.; Meng, J.; Liu, Z.Y.; Ding, Z.H. Constrained polynomial fit-based k-domain interpolation in swept-source optical coherence tomography. J. Innov. Opt. Health Sci. 2021, 14, 2140008. [Google Scholar] [CrossRef]
  18. Sun, Y.; Shang, L.; Li, J.; Ge, L. Software Development Based on High Speed PC Oscilloscope for Automated Pulsed Magnetic Field Measurement System. Nucl. Electron. Detect. Technol. 2011, 31, 1259–1264. [Google Scholar]
  19. Park, K.; Park, J. Time-to-digital converter of very high pulse stretching ratio for digital storage oscilloscopes. Rev. Sci. Instrum. 1999, 70, 1568–1574. [Google Scholar] [CrossRef]
  20. Ye, C.F.; Zhao, L.; Zhou, Z.Y.; Liu, S.B.; An, Q. A field-programmable-gate-array based time digitizer for the time-of-flight mass spectrometry. Rev. Sci. Instrum. 2014, 85, 045115. [Google Scholar] [CrossRef]
  21. Shen, Z.; Feng, C. Real-time weak signal detecting using FPGA-based duffing oscillator with auto-damping and high speed ADC. Proc. AIP Conf. Proc. 2017, 1839, 020109. [Google Scholar]
  22. Tiwari, K.A.; Ostreika, A.; Platuziene, J. Efficient FPGA-based FIR–architecture and its significance in ultrasonic signal processing. J. Vibroeng. 2017, 19, 6423–6432. [Google Scholar] [CrossRef] [Green Version]
  23. Xu, G.; Zha, B.; Xia, T.; Zheng, Z.; Zhang, H. A High-Throughput Vernier Time-to-Digital Converter on FPGAs with Improved Resolution Using a Bi-Time Interpolation Scheme. Appl. Sci. 2022, 12, 7674. [Google Scholar] [CrossRef]
  24. Yang, S.-S.; Liu, J.-Q.; Lu, Z.-G.; Bai, Z.-L.; Wang, X.-Y.; Li, Y.-M. An FPGA-Based LDPC Decoder with Ultra-Long Codes for Continuous-Variable Quantum Key Distribution. IEEE Access 2021, 9, 47687–47697. [Google Scholar] [CrossRef]
  25. Desai, M.P.; Caffarena, G.; Jevtic, R.; Márquez, D.G.; Otero, A. A low-latency, low-power FPGA implementation of ECG signal characterization using hermite polynomials. Electronics 2021, 10, 2324. [Google Scholar] [CrossRef]
  26. Sonowal, D.; Bhuyan, M. Linearizing thermistor characteristics by piecewise linear interpolation in real time FPGA. In Proceedings of the 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI), Mysore, India, 22–25 August 2013; pp. 1976–1980. [Google Scholar]
  27. Monir, M.S.; Sayed, W.S.; Madian, A.H.; Radwan, A.G.; Said, L.A. A unified FPGA realization for fractional-order integrator and differentiator. Electronics 2022, 11, 2052. [Google Scholar] [CrossRef]
  28. Parsakordasiabi, M.; Vornicu, I.; Carmona-Galán, R.; Rodríguez-Vázquez, Á. PhD Forum: A Survey on FPGA-Based High-Resolution TDCs; Association for Computing Machinery: New York, NY, USA, 2019. [Google Scholar]
  29. Li, J.W.; Guo, X.; Luan, J.; Wu, D.Y.; Zhou, L.; Huang, Y.K.; Wu, N.X.; Jia, H.B.; Zheng, X.Q.; Wu, J.; et al. A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process. Electronics 2019, 8, 1551. [Google Scholar] [CrossRef] [Green Version]
  30. Mohsen, A.A.K. Accurate function Sinc interpolation and derivative estimations over finite intervals. J. Comput. Appl. Math. 2017, 324, 216–224. [Google Scholar] [CrossRef]
Electronics 12 01291 g001 550
Figure 1. Trigger acquisition schematic.
Figure 1. Trigger acquisition schematic.
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Figure 2. Schematic diagram of the interpolation process.
Figure 2. Schematic diagram of the interpolation process.
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Figure 3. Schematic diagram of the trigger after interpolation.
Figure 3. Schematic diagram of the trigger after interpolation.
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Figure 4. Schematic diagram of the combination of sinc interpolation and linear interpolation.
Figure 4. Schematic diagram of the combination of sinc interpolation and linear interpolation.
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Figure 5. (a) Trigger resampling schematic; (b) Resampling data splicing schematic.
Figure 5. (a) Trigger resampling schematic; (b) Resampling data splicing schematic.
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Figure 6. (a) Spectrum of un-interpolated resampling results; (b) Time domain waveform recovered without interpolation resampling.
Figure 6. (a) Spectrum of un-interpolated resampling results; (b) Time domain waveform recovered without interpolation resampling.
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Figure 7. (a) Performance comparison of different interpolation multipliers under filter parameters of 4; (b) Performance comparison of different filter coefficients with an interpolation multiplier of 8.
Figure 7. (a) Performance comparison of different interpolation multipliers under filter parameters of 4; (b) Performance comparison of different filter coefficients with an interpolation multiplier of 8.
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Figure 8. (a) RMS values corresponding to different sinc interpolation multipliers, using default filter parameters; (b) RMS values corresponding to different filter parameters for a sinc interpolation multiplier of 8.
Figure 8. (a) RMS values corresponding to different sinc interpolation multipliers, using default filter parameters; (b) RMS values corresponding to different filter parameters for a sinc interpolation multiplier of 8.
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Figure 9. (a) The resampling spectrum when the interpolation factor of sinc is 8 and the filter parameter is 6; (b) Resampled time domain waveform with 8× interpolation and a filter factor of 6.
Figure 9. (a) The resampling spectrum when the interpolation factor of sinc is 8 and the filter parameter is 6; (b) Resampled time domain waveform with 8× interpolation and a filter factor of 6.
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Figure 10. The filter frequency response when the interpolation multiplier of sinc is 8 and the filter parameter is 6.
Figure 10. The filter frequency response when the interpolation multiplier of sinc is 8 and the filter parameter is 6.
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Figure 11. (a) Comparison of RMS values for the two interpolation methods; (b) Performance comparison of three resampling methods.
Figure 11. (a) Comparison of RMS values for the two interpolation methods; (b) Performance comparison of three resampling methods.
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Figure 12. (a) Spectrum diagram after sinc interpolation and linear interpolation; (b) Time waveform after sinc interpolation and linear interpolation.
Figure 12. (a) Spectrum diagram after sinc interpolation and linear interpolation; (b) Time waveform after sinc interpolation and linear interpolation.
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Figure 13. Actual test environment.
Figure 13. Actual test environment.
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Figure 14. Actual test recovered time domain waveform.
Figure 14. Actual test recovered time domain waveform.
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Figure 15. (a) Spectrogram of the actual test; (b) Actual test recovered time domain waveform.
Figure 15. (a) Spectrogram of the actual test; (b) Actual test recovered time domain waveform.
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Table
Table 1. Un-interpolated resampling results.
Table 1. Un-interpolated resampling results.
ParameterValue
Sampling Frequency (MHz)701.12
Input Frequency (MHz)15.12
SNR (dBFS)46.80
THD (dB)−66.62
SFDR (dB)45.91
ENOB7.48
Table
Table 2. Performance comparison of different interpolation multipliers under default filter parameters.
Table 2. Performance comparison of different interpolation multipliers under default filter parameters.
Parameter2×4×6×8×10×
Sampling Frequency (MHz)701.12701.12701.12701.12701.12
Input Frequency (MHz)15.1215.1215.1215.1215.12
SNR (dBFS)46.2349.4550.4350.9351.11
THD (dB)−66.26−69.34−72.17−77.82−72.20
SFDR (dB)45.0548.1448.3748.5548.57
ENOB (bit)7.387.928.088.178.19
Table
Table 3. Performance comparison of different filter coefficients with interpolation multiplier of 8.
Table 3. Performance comparison of different filter coefficients with interpolation multiplier of 8.
Parameter2×4×6×8×10×
Sampling Frequency (MHz)701.12701.12701.12701.12701.12
Input Frequency (MHz)15.1215.1215.1215.1215.12
SNR (dBFS)36.9350.9361.0063.7663.99
THD (dB)−61.82−77.82−80.64−79.33−79.90
SFDR (dB)33.8348.5561.1473.7883.64
ENOB (bit)5.848.1669.8410.2910.33
Table
Table 4. Performance table for overall interpolation.
Table 4. Performance table for overall interpolation.
ParameterValue
Sampling Frequency (MHz)701.12
Input Frequency (MHz)15.12
SNR (dBFS)58.98
THD (dB)−62.22
SFDR (dB)60.96
ENOB (bit)9.42
Table
Table 5. Simulation test results of different frequency points.
Table 5. Simulation test results of different frequency points.
ParameterValueValueValueValue
Sampling Frequency (MHz)351.12511.12511.12351.12
Input Frequency (MHz)15.0915.095.125.12
SNR (dBFS)58.7559.5561.6961.65
THD (dB)−63.12−58.46−70.19−69.25
SFDR (dB)63.3860.4861.2773.74
ENOB (bit)9.409.399.939.92
Table
Table 6. The consumption of the main resources of the algorithm in the FPGA.
Table 6. The consumption of the main resources of the algorithm in the FPGA.
ParameterUtilizationAvailable
LUT110,157298,600
Registers96,973124,763
BRAM54955
Table
Table 7. Performance tables for actual testing.
Table 7. Performance tables for actual testing.
ParameterValueValue
Sampling Frequency (MHz)701.123351
Input Frequency (MHz)15.12315.09
SNR (dBFS)51.9752.18
THD (dB)−61.92−60.31
SFDR (dB)61.2663.88
ENOB (bit)8.328.34
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MDPI and ACS Style

Cao, M.; Xu, F.; Jia, H.; Zhou, L.; Ji, E.; Wu, J. A Multiple Interpolation Algorithm to Improve Resampling Accuracy in Data Triggers. Electronics 2023, 12, 1291. https://doi.org/10.3390/electronics12061291

AMA Style

Cao M, Xu F, Jia H, Zhou L, Ji E, Wu J. A Multiple Interpolation Algorithm to Improve Resampling Accuracy in Data Triggers. Electronics. 2023; 12(6):1291. https://doi.org/10.3390/electronics12061291

Chicago/Turabian Style

Cao, Mengtao, Fangyuan Xu, Hanbo Jia, Lei Zhou, Eryou Ji, and Jin Wu. 2023. "A Multiple Interpolation Algorithm to Improve Resampling Accuracy in Data Triggers" Electronics 12, no. 6: 1291. https://doi.org/10.3390/electronics12061291

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