An Energy-Efficient Inverter-Based Voltage Reference Scheme with Wide Output Range Using Correlated Level Shifting Technique

Abstract

A voltage reference is indispensable in Integrated Circuits. To improve the limited linear output voltage range and energy efficiency of a voltage reference, we innovatively propose a switched-capacitor-based programmable voltage reference scheme employing inverter-based OTAs to reduce the power consumption, simultaneously using a novel Correlated Level Shifting (CLS) technique (without active overhead) to enhance the OTA’s DC gain and integral gain. Experimented with SMIC 180 nm CMOS technology, a scheme-based voltage reference realizes a programable output voltage range from 266 to 995 mV at −30 to 120 °C, and the corresponding temperature coefficient (TC) ranges from 82.4 to 99.5 ppm/°C. The power consumption is 976 nW. Furthermore, comparative experiments and evaluations with other schemes have unequivocally verified the superiority of our proposed scheme, characterized by its high energy efficiency and wide output voltage range. The scheme can be suitably deployed in a multitude of novel edge-data processing systems.

1. Introduction

Following the advancement of the Internet of Things, research on low-voltage and low-power signal-conditioning circuits has increasingly become popular because sensing devices are generally powered by batteries. When voltage reference is used as a signal-conditioning circuit supply module, its power consumption is generally required to be at the nanowatt level. A conventional voltage reference generally consists of an Operational Amplifier (Op-Amp) and a Bipolar Junction Transistor (BJT) [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]. Such designs generally consume large amounts of energy. A voltage reference based on subthreshold Complementary Metal–Oxide–Semiconductor (CMOS) combined with BJT was proposed [16], which effectively reduced power consumption but had a poor temperature coefficient (TC). A voltage reference based on switched-capacitor amplifiers was proposed [17], but its power consumption could not be further reduced because of the addition of traditional Operational Transconductance Amplifiers (OTAs). Passive switched-capacitor technology used to achieve ultra-low power benchmarks has been reported [18], but it was only suitable for a small range of temperature difference calculations.

Therefore, in order to further enhance the energy efficiency of a switched-capacitor voltage reference, we first used inverter-based OTAs in place of conventional OTAs in switched-capacitor networks. However, inverter-based OTAs have programable linear output range limitations, so we propose a novel Correlated Level Shifting (CLS) technique [19,20,21,22,23,24] based on a switched-capacitor voltage reference scheme, which further reduces the power consumption (because it does not require additional active overhead). Consequently, the proposed scheme includes the following: (1) a switched-capacitor voltage reference with inverter-based OTAs and (2) a switched-capacitor voltage reference with inverter-based OTAs using the CLS technique.

Compared with conventional schemes [17,18], the experiments show that the proposed scheme is output-programable, energy-efficient and has a wide voltage reference linear output range. As far as the knowledge of the authors, this is the first scheme to systematically combine inverter-based OTAs with CLS and voltage reference.

2. Proposed Voltage Reference Scheme

As depicted in Figure 1, the proposed scheme comprises the following components: a core circuit, a switched-capacitor network and an auxiliary circuit (I_DC and clock generation). The I_DC generation circuit supplies current to the core circuit, which generates two Complementary-To-Absolute Temperature (CTAT) voltages, i.e., V_GS1 and V_GS2. The switched-capacitor network employs these CTAT voltages to output the zero-temperature voltage reference. The scheme incorporates improvements to the OTAs in the switched-capacitor network, enhancing the overall energy efficiency and broadening the range of the output voltage reference. The clock generation circuit supplies the necessary clock signal for the switch-capacitor network.

2.1. Core Circuit

2.1.1. CTAT Voltage Generation Principle

Subthreshold MOS Field-Effect Transistors (MOSFETs) [25,26,27,28,29] have negative temperature characteristics; however, the voltage varies with the process. Therefore, the use of a voltage reference circuit designed using MOSFETs only is more sensitive to the process, voltage, and temperature (PVT). The circuit that generates voltage reference based on diode-cascaded MOSFETs is shown in Figure 2a. However, due to the poor PVT robustness of this structure, the TC is poor.

A more suitable CTAT voltage generation circuit is shown in Figure 2b. The addition of a current source bias improves the PVT characteristics of the CTAT voltage generation circuit. This is because the current source fixes the bias current of the inverter so that the current is unchanged when PVT is perturbed. We need to mention that, driven by fixed bias current I_DC, the source-level potential of transistor M₃ is suppressed, and the output node voltage (V₂) exhibits a negative temperature characteristic, which is dominated by diode-connected transistor M₄.

2.1.2. Core Circuit with CTAT and Inverter-Based OTAs

As shown in Figure 3, M₁, M₂, M₅, M₈ and M₁₁ constitute a current mirror, and the current in each branch is 100 nA. Transistors M₃, M₄, M₆ and M₇ are connected in diode-connected forms to generate CTAT voltages. All MOS transistors operate in the subthreshold region.

The more complex subthreshold-region current Equation (1) is expressed as follows:

$$I_{\mathrm{DS}}=n\mu C_{\mathrm{OX}}\left(\frac{W}{L}\right){\left(\frac{kT}{q}\right)}^2\left\{\mathit{exp}\left[\frac{q}{nkT}\left(V_{\mathrm{GS}}-V_{\mathrm{TH}}\right)\right]\right\}\left[1-\mathit{exp}\left(-\frac{V_{\mathrm{DS}}}{kT/q}\right)\right]$$

(1)

where μ is the carrier mobility, C_OX is the oxide capacitance per unit area, kT/q = V_T is the thermal voltage, V_TH is the threshold voltage and n is the subthreshold slope correction factor typically taken as 1.5.

Assuming that voltage V_DS of MOSFET is much larger than three times kT/q, Equation (1) can be simplified as Equation (2):

$$I_{\mathrm{DS}}=n\mu C_{\mathrm{OX}}\left(\frac{W}{L}\right){\left(\frac{kT}{q}\right)}^2\left\{\mathit{exp}\left[\frac{q}{nkT}\left(V_{\mathrm{GS}}-V_{\mathrm{TH}}\right)\right]\right\}$$

(2)

The calculation Equation (3) for V_GS1 and V_GS2 is expressed as follows:

$$V_{\mathrm{GS}1,2}=V_{\mathrm{TH}}+n{V}_{\mathrm{T}}\mathit{ln}\left[\left(\frac{L}{W}\right){\left(\frac{1}{V_{\mathrm{T}}}\right)}^2\left(\frac{I_{\mathrm{DS}}}{n\mu C_{\mathrm{OX}}}\right)\right]$$

(3)

In Figure 3, by changing the width-length ratio of M₃, M₄, M₆, and M₇, different negative TCs can be obtained. The voltage of the two can be subtracted to obtain the voltage that is positively correlated with temperature. Equation (4) is expressed as follows:

$$\Delta V_{\mathrm{GS}}=V_{\mathrm{GS}1}-V_{\mathrm{GS}2}=n{V}_{\mathrm{T}}\mathit{ln}\left(\frac{m_7}{m_4}\right)$$

(4)

The m₄, m₇ is the width-length ratio of M₄, M₇, respectively.

2.2. Auxiliary Circuit

2.2.1. The I_DC Generation Circuit

The I_DC generation circuit in the proposed scheme is shown in Figure 4. In Figure 4, transistors M₁, M₂, M₃, M₄, M₅, M₆, M₇ and M₈ form the current source start-up circuit. The gate-source voltage of transistor M₂₂, operating in the subthreshold region, exhibits negative temperature characteristics. By utilizing the positive temperature characteristics of the gate-source voltage difference of transistors M₁₈ and M₁₉, a bias is provided to transistor M₁₅, which operates in the deep linear region, to generate the zero-temperature current I_DC and supply power to the subsequent circuits.

The circuit for the generation of I_DC is highly sensitive to variations in device parameters (mismatches). We will discuss this in terms of device parameter design. According to [30,31,32], the mismatch impacts in MOSFETs are expressed as mismatches among several parameters, including μ, C_OX, W, L and V_TH.

Within our scheme, to meet high energy efficiency demands, I_DC is required to provide current at the nanoampere level. To enhance matching and minimize the impact of device mismatches, thereby obtaining more precise current values, our scheme primarily adopts the following measures:

• MOS transistor dimensions are designed based on the principle of unit matching, i.e., all devices are formed by the series and parallel connection of unit devices. In the I_DC circuit, the W and L of the unit device (multiplier = 1) are uniformly set at 3 μm/3 μm;
• As the MOS transistor mismatch is inversely proportional to the square root of the product of the device size (W and L), larger device sizes will average out the random mismatches of various MOS transistor parameters to a greater extent, thereby resulting in a relatively smaller expected mismatch value. In the I_DC circuit, the area is maximized as much as possible under the premise of the MOS transistor operating in the correct region to achieve better matching performance.

The total current of the I_DC generation circuit used is 280 nA, and the temperature characteristic of I_DC is shown in Figure 5. It is worth noting that the proposed switched-capacitor voltage reference is insensitive to the generation of I_DC current.

2.2.2. Clock Generation Circuit

The clock generation circuit of the proposed voltage reference scheme is shown in Figure 6, which utilizes D flip-flops [33] with appropriate delays to generate the required clock control signals through division. Unlike the conventional D flip-flop, the DFF_DELAY module has an additional port called DFF non-overlapping (D_NOL).

The introduction of the D_NOL port is for the purpose of generating non-overlapping clocks. Overlapping clocks can introduce switch switching chaos, preventing capacitors from transferring charge at the correct phase, leading to voltage errors at both plates of the capacitor. Therefore, the non-overlapping of clocks is crucial for generating the correct voltage reference.

Figure 7 displays the circuit diagram of the DFF_DELAY module. As illustrated in Figure 7, the delay unit Time Delay (T_d) is inserted between D_NOL and M₈ gates. Composed of a straightforward inverter, T_d provides flexible control of specific delay durations, substantially lessening the difficulty in designing multiple non-overlapping sequences. Therefore, this non-overlapping clock design technique maintains low circuit complexity and minimal additional power consumption, adhering to the high energy efficiency objective of the scheme.

As discussed in the previous paragraph, the D_NOL port is the core part of generating non-overlapping clocks. Taking a single DFF_DELAY module as an example, the signal Q can only rise after D_NOL has fallen to a low level after a duration of T_d, thereby inducing a signal delay. The sequential interplay of four DFF_DELAY modules ultimately ensures that all clocks are non-overlapping, guaranteeing the accurate transition of all switches.

The clock input frequency is 100 kHz, and the overall power consumption of the clock circuit is 40 nW.

2.3. Scheme 1: Switched-Capacitor Voltage Reference with Inverter-Based OTAs

The proposed voltage reference switched-capacitor network is shown in Figure 8. OTA₁ and OTA₂ are shown in Figure 3, and the sizes of OTA₁ and OTA₂ are obtained using a circuit image generated by V_GS2, which improves the matching of the overall circuit layout. Contrasted with conventional OTAs, the output transconductance of inverter-based OTAs is observed to be nearly twice as much, which implies the inverter-based OTA with a constant current–source bias demonstrates higher energy efficiency than traditional OTAs [17]. Compared with conventional inverter-based OTAs [34], this circuit demonstrates better PVT robustness. We must mention that because the switched-capacitor divider only needs to provide a charge-transfer function in the scheme, the common-mode feedback circuit of the switched-capacitor in the literature [34] is not necessary, which further reduces the area and power of the circuit.

The reset function is executed in phase Ф₁, where the inverter-based OTAs are switched to a unity gain configuration. Offset voltage V_OFF1 (V_OFF2) is sampled on capacitor C_C1 (C_C2) while capacitor C_I1 (C_I2) is reset. At the same time, the input voltage is sampled on capacitor C_S1 (C_S2). The sampling function is executed in phase Ф₂. Because the right plate of capacitor C_C1 (C_C2) is not connected to the ground, the left side of capacitor C_C1 (C_C2) forms an equivalent virtual ground node V_G1 (V_G2), and the collected signal charge is transferred to capacitors C₁ and C₂. Finally, in phase Ф₃, C₁ is imposed on top of C₂, and the two voltages are added to obtain the output reference voltage that is independent of temperature and is stored in capacitor C₃.

To simplify the analysis, only a finite gain is considered without considering the non-ideal effects on the circuit. Thus, the following expression can be obtained, as shown in Equation (5):

$$V_{\mathrm{REF}}\left(n\right)=\frac{C_1{C}_2}{C_1{C}_2+C_1{C}_3+C_2{C}_3}\left[\begin{array}{l}\frac{A{C}_{\mathrm{S}1}}{C_{\mathrm{S}1}+A{C}_{\mathrm{I}1}}{V}_{\mathrm{GS}2}+V_{\mathrm{OFF}1}\frac{C_{\mathrm{I}1}+C_{\mathrm{S}1}}{\left(1+A\right)C_{\mathrm{I}1}+C_{\mathrm{S}1}}+\\ \frac{A{C}_{\mathrm{S}2}}{C_{\mathrm{S}2}+A{C}_{\mathrm{I}2}}\left(V_{\mathrm{GS}1}-V_{\mathrm{GS}2}\right)+V_{\mathrm{OFF}2}\frac{C_{\mathrm{I}2}+C_{\mathrm{S}2}}{\left(1+A\right)C_{\mathrm{I}2}+C_{\mathrm{S}2}}\end{array}\right]+\frac{C_1{C}_3+C_2{C}_3}{C_1{C}_2+C_1{C}_3+C_2{C}_3}{V}_{REF}\left(n-1\right)$$

(5)

Because the coefficient of V_REF (n − 1) must be less than one, we can observe that the output reference quickly stabilizes after the switched capacitor operates. In the case of infinite inverter-based OTA gain, the scale of the input voltage is completely determined by the ratio of the C_S1 (C_S2) and C_I1 (C_I2) capacitors. As long as the proportional relationship between capacitors C_S1 (C_S2) and C_I1 (C_I2) is reasonably controlled, the size of the output reference voltage can be programed. However, because the integral DC gain based on the inverter-based OTAs is generally approximately 30 dB [34], the coefficient term of V_OFF1 (V_OFF2) and the zero temperature-coefficient term must be considered. Although a current-source bias has been used to counter the PVT characteristics, the environment for both the V_OFF1 (V_OFF2) and zero temperature coefficient terms will deteriorate because of the smaller gain of A. In particular, when C_S1 (C_S2) and C_I1 (C_I2) are programable items, the TC substantially increases. In a transistor-level experiment, the results are consistent with the foregoing analysis. To make matters worse, the low integral gain makes the programable reference voltage linear output range obtained by this scheme limited. In addition, the influence of non-ideal factors in the design process must be considered, especially the parasitic capacitance introduced by the inverter-based OTAs input/output switch docking, which can make the scheme unattractive.

2.4. Scheme 2: Switched-Capacitor Voltage Reference with Inverter-Based OTAs Using Correlated Level Shifting (CLS) Technique

To overcome the output range limitation of the voltage reference caused by the low gain of inverter-based OTAs, as shown in Figure 3, we observed that a CLS technique based on inverter-based OTAs was proposed [24], which could significantly improve the DC and the integral gain of inverter-based OTAs.

However, the CLS technique in [24] requires the additional input/output short-circuit inverter to provide the V_CLS reference, which introduces additional active power consumption that is not allowed in low-power designs. Figure 9 shows that the reference core circuit based on our proposed scheme is highly compatible with the CLS technique because the required V_CLS reference can be supplied by negative reference voltage V_GS2, which further avoids additional active power consumption. Thus, the designed architecture can realize a wide reference voltage linear output range in a low-power consumption manner.

To simplify the analysis, Figure 10 shows an example of the equivalent working model of the CLS technique in relation to the voltage reference. By incorporating the C_CLS capacitor and modifying switch timing utilization, this technique can suppress the swing of OTA output to enhance DC gain, bringing the virtual ground node closer to the signal ground node, thereby achieving superior charging precision and a higher DC gain.

Contrasted with the switched-capacitor network in Figure 8, timing utilization has been updated with the addition of new phases, Ф₂₁ and Ф₂₂, and the details of the switching process are as follows: During the Ф₁ phase, the inverter auto-zeroes, C_I resets, and C_S samples the input voltage. When the Ф₂₁ phase (coarse charging stage) arrives, the right plate of C_CLS is connected to the inverter output, and the left plate is linked to a voltage (V_GS2) equal to the inverter’s critical point. The inverter charges C_CLS to make a rough estimate of the output. Then, during the Ф₂₂ phase (fine charging stage), the level shift capacitor C_CLS is inserted, and the output swing is suppressed at the inverter output, shifting V_G towards the ground. As a result, charge redistribution reduces the residual charge on C_S, leading to a complete charge transfer, thereby enhancing effective DC gain.

The complete switched-capacitor voltage reference with inverter-based OTAs using the CLS technique and its timing utilization are shown in Figure 11. Assuming $1+C_{\mathrm{S}}/C_{\mathrm{I}}=sigma1$ and considering the situation with limited gains, its single-ended output expression is expressed as shown in Equation (6):

$$V_{\mathrm{REF}}=\frac{C_{\mathrm{S}}{V}_{\mathrm{IN}}}{C_{\mathrm{I}}}\left[\frac{A}{A+sigma1}\frac{sigma1+A+1+\frac{C_{\mathrm{S}}}{C_{\mathrm{I}}}+\frac{C_{\mathrm{S}}}{C_{\mathrm{CLS}}}{C}_{\mathrm{S}}}{A+1+\frac{C_{\mathrm{S}}}{C_{\mathrm{I}}}+\frac{C_{\mathrm{S}}}{C_{\mathrm{CLS}}}{C}_{\mathrm{S}}}\right]+V_{\mathrm{OFF}}\left\{\frac{C_{\mathrm{I}}+C_{\mathrm{S}}}{\left(1+A\right)C_{\mathrm{I}}+C_{\mathrm{S}}}\left[1-\frac{A}{A+1+\frac{C_{\mathrm{S}}}{C_{\mathrm{I}}}+\frac{C_{\mathrm{S}}}{C_{\mathrm{CLS}}}}\right]\right\}$$

(6)

Compared with Equation (5), V_OFF has an additional coefficient term of $1-A/\left(1+A+C_{\mathrm{S}}/C_{\mathrm{I}}+C_{\mathrm{S}}/C_{\mathrm{CLS}}\right)$, which is a value approaching zero. With the addition of the CLS technique, the offset can be approximately eliminated. In Equation (6), $\left[A/\left(A+sigma1\right)\right]<1$, and the ratio of $\left[sigma1+A+1+C_{\mathrm{S}}/C_{\mathrm{I}}+\left(C_{\mathrm{S}}/C_{\mathrm{CLS}}\right)C_{\mathrm{S}}\right]$ to $\left[A+1+C_{\mathrm{S}}/C_{\mathrm{I}}+\left(C_{\mathrm{S}}/C_{\mathrm{CLS}}\right)C_{\mathrm{S}}\right]$ is greater than 1. Thus, their product is obviously almost close to one and less than one. Therefore, the zero TC is almost exclusively related to the capacitor ratio $C_{\mathrm{S}}/C_{\mathrm{I}}$. As we can observe, the characteristics of this switched-capacitor amplifier are insensitive to the gain of the inverter-based OTAs with the introduction of the CLS technique, which also makes the circuit’s programable scaling voltage–output reference better.

Compared with the simple inverter-based OTA’s voltage reference, obvious advantages can be observed. Compared with that in the literature [24], the bias voltage used for C_CLS is inherent in the proposed scheme. Thus, using one capacitive C_CLS is cost effective because it only uses one passive capacitor overhead.

3. Experiment Result

The proposed scheme was verified through the use of a voltage reference experiment using SMIC 180 nm CMOS technology. The core device parameters shown in Figure 3 and Figure 9 were used as follows: M₆ = M₉ = M₁₂ = 24 μm/4 μm, M₇ = M₁₀ = M₁₃ = 8 μm/4 μm. To reduce the effect of parasitic capacitance on the gain linearity, C_CLS was chosen to have a value of 0.5 pF.

Its layout is presented in Figure 12. The voltage reference occupies an area of 843 μm × 832 μm (including the I_DC generation circuit, clock generation circuit and I/O ports).

Layout matching is a crucial factor in minimizing device mismatch [35]. In this scheme, the performance characteristics of the switched-capacitor voltage reference are contingent on the matching of the proportional devices, thereby imposing stringent requirements for layout matching. To mitigate the impact of device mismatch on the overall circuit, we utilized various matching principles in the layout of this scheme, striving to optimize the layout as much as possible. The specific measures are as follows:

• In the overall layout, devices requiring matching are placed as close as possible, and the orientation is kept consistent;
• In the I_DC circuit, proportional diodes adopt a common centroid layout, and virtual devices are added to the bias circuit devices;
• In the OTA circuit, all current mirrors are arranged in a row, with virtual devices placed on both sides, and current mirrors that need to be replicated are positioned in the middle;
• In the switched-capacitor network, all switches are placed together, and the switch control signal routing is minimized as much as possible. Strictly proportional capacitors are matched with a common centroid layout by choosing a reasonable unit capacitance value, and virtual capacitors are placed around the capacitor array to mitigate process influences.

As shown in Figure 13, the equivalent DC gain increased from 33 to 48 dB with the introduction of CLS, and the linear interval of the integral gain obviously widened. The implementation of the CLS technique in the proposed scheme has facilitated the inverter-based OTA in matching the gain of a conventional OTA with lower power consumption, simultaneously enlarging the linearity of the output range, thereby demonstrating the high energy efficiency of this scheme.

The proposed voltage reference scheme could realize a programable voltage reference voltage output. By changing the sizes of C_S1 (C_S2) and C_I1 (C_I2), the reference output–voltage curve is shown in Figure 14, which shows that the linear output reference voltage could achieve a wide linear output range from 266 to 995 mV within the temperature range of −30 to 120 °C. The worst TC value was 99.5 ppm/°C at 603 mV, and the best TC value was 82.4 ppm/°C at 995 mV.

Figure 15a shows the temperature characteristic curves for five different process corners (TT, SS, FS, SF, and FF) under a temperature range of −30 °C to 120 °C for a specific programming configuration. At 1.2 V power supply voltage, V_REF at the TT process corner was 430 mV, the TC value was 92.6 ppm/°C, and the power consumption was 936 nW. Figure 15b shows the output reference voltage curve as the supply voltage varied. The supply voltage varied from 0.9 to 1.8 V, and the linearity was less than 2%/V.

4. Discussion

Table 1. Performance Comparison.

	This Work	[17]	[29]	[28]	[18]
CMOS Process	180 nm	65 nm	180 nm	350 nm	65 nm
Devices	MOS	BJT + MOS	MOS	BJT + MOS	BJT
Switched-Capacitor	Yes (active)	Yes (active)	No	No	Yes (passive)
Supply (V)	0.9–1.8	0.9–1.8	1.2–1.8	1.2–3.3	0.75
Min VDD (V)	0.9	0.9	1.2	1.2	N/A
Temp Range (°C)	−30–120	−40–100	−40–120	−20–80	−35–80
Reference Voltage (V)	0.266–0.995	0.591 0.872 1.189	1.09	0.553	0.423
Normalized Output Range * (%)	60.8	49.8	N/A	N/A	N/A
TC (ppm/°C)	82.4–99.5	43 (for 0.591) 28 (for 0.872) 33 (for 1.189)	147	394	160
Power (μW)	0.976	40 (for 0.591) 60 (for 0.872) 110 (for 1.189)	0.1	0.11	0.1035
Energy FoM **	14.9 (min TC) 10.1 (max TC)	11.5 23.1 13.1	12.3	1	7.4

* $\mathrm{Normalized} \mathrm{Output} \mathrm{Range}=\frac{\mathrm{Reference} \mathrm{Voltage}}{\mathrm{Supply} \mathrm{Voltage}}\times 100\%$, Supply Voltage is 1.2 V. ** Energy Figure of Merit $\mathrm{FoM}=\frac{\mathrm{Temp} \mathrm{Range}}{{\mathrm{TC}}^2 \times {\mathrm{Power}}^{0.4}}$. Note that, normalization is applied to the FoM with the baseline FoM calculated from [28]. Higher FoM indicate higher energy efficiency of the reference.

lists a summary of the comparison between the proposed voltage reference and other reported schemes. Compared with these schemes, the proposed voltage reference achieved a low TC value of 82.4 ppm/°C. The proposed scheme supports a wide programable voltage reference output range, which is an approximate 20% enhancement compared to the scheme in [17].

To facilitate a more effective energy efficiency comparison between our scheme and others [17,18,28,29], an energy FoM is specifically introduced. This involves a comprehensive analysis of the voltage reference’s temperature range, TC, and power consumption. The derived FoM is presented in Table 1, demonstrating the superiority of our scheme in terms of energy efficiency.

In addition, our scheme has other advantages as follows:

• It can be implemented by a mature 180 nm process, which is economically advantageous compared to advanced processes in [17,18];
• It can be implemented by full MOSFETs, eliminating BJT devices typically used in traditional bandgap references and thus reducing area;
• The scheme-based reference operates within a voltage range of 0.9–1.8 V, exhibiting high resilience to variations in external voltage values.

Of course, there are some limitations and further optimizations to this scheme:

• Consideration should be given to the reuse of the I_DC generation circuit (Figure 4) and clock generation circuit (Figure 6) to reduce overall power consumption, thereby further improving energy efficiency;
• The scheme biases the inverter with a current source (Figure 3), limiting the output range. It can be optimized by using a floating current source;
• The scheme employs the CLS technique, which is limited by the large capacitance area. Future work will employ capacitors with larger capacitance/(unit area) to optimize the layout;
• The scheme does not adopt a high-order calibration. It is not easy to integrate this calibration within switched-capacitor networks in the discrete-time domain. Future work will focus on this to reduce the TC.

5. Conclusions

To achieve higher energy efficiency and a wide programable output range, a novel scheme implementing a switched-capacitor voltage reference with inverter-based CLS OTAs is proposed for the first time.

Compared with the conventional switched-capacitor voltage reference, this scheme represents the first innovative use of inverter-based OTAs in place of conventional OTAs. In contrast with the conventional voltage reference based on subthreshold MOSFETs, the proposed scheme achieves a lower TC. Furthermore, compared with the conventional inverter-based CLS technique, it shows that the proposed novel CLS does not require additional active overhead. The proposed scheme is verified by implementing a voltage reference with SMIC 180 nm CMOS technology, and its linearity is 2%/V under a 0.9–1.8 V power supply. At a supply voltage of 1.2 V, a programable output voltage range of 266 to 995 mV can be achieved in the range from −30 to 120 °C with corresponding TCs that range from 82.4 to 99.5 ppm/°C, and the corresponding power consumption is 976 nW.

The proposed scheme exhibits a high level of energy efficiency and a wide output range (60.8% of the supply voltage), thus making it suitable for low-voltage and low-power supply applications. The scheme has been utilized in high-precision analog-to-digital converters, digital-to-analog converters, and instrument amplifiers. It holds significant potential for future applications in memory processing units and artificial intelligence chips.