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Article

Research on the Optimization of Synchronous Switch Energy Harvesting Circuit Based on Capacitor

College of Equipment Engineering, Shenyang Ligong University, Shenyang 110159, China
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Author to whom correspondence should be addressed.
Electronics 2023, 12(19), 4070; https://doi.org/10.3390/electronics12194070
Submission received: 23 August 2023 / Revised: 19 September 2023 / Accepted: 20 September 2023 / Published: 28 September 2023

Abstract

:
As advanced systems continue to advance and fuse functions expand, the demand for higher power supply requirements for fuses has increased. Consequently, researchers have turned their attention to the recovery of energy from the environment. Piezoelectric energy harvesting has gained significant popularity due to its advantageous characteristics, such as high energy density, ease of implementation, and compact size. However, the presence of various component types within the energy harvesting circuit inevitably results in the generation of reactive power, leading to a reduction in the circuit’s power factor. To address this issue, this paper introduces the adoption of the third-order valley-fill circuit as the power factor correction circuit. The implementation process involves the utilization of Multisim software to simulate the double-limit zero-crossing detection circuit, pulse signal generation circuit, and power factor correction circuit. Furthermore, the aforementioned circuits were subjected to plate-level welding, followed by individual tests to evaluate the effectiveness of the double-limit zero-crossing detection, pulse signal test, and load voltage measurement. These findings unequivocally exemplify the successful accomplishment of the intended objective of augmenting the output power by the third-order valley-fill circuit.

1. Introduction

The advancement of Microelectromechanical Systems (MEMS) technology has led to the increased utilization of low–power devices in ammunition, including MEMS accelerometers [1], MEMS gyroscopes [2], and MEMS actuators [3]. This proliferation of devices has expanded the capabilities of ammunition systems but has also necessitated higher power supply requirements. Achieving a balance between large capacity and small size in the power supply is challenging, particularly for small caliber ammunition and submunitions. Consequently, the demand for power supply in these specific types of ammunition is becoming increasingly stringent. How to save energy and produce electricity efficiently has become a concern of many researchers.
The process of recovering energy from natural environmental systems and converting it into usable energy is called energy harvesting. It is a very practical and meaningful technology to collect energy from the surrounding environment and convert it into energy that can be used by the device.
Ammunition systems involve set–back force (refers to the recoil when the bullets and shells are ejected) and centrifugal force (refers to the outward force generated because the projectile maintains a certain speed on the trajectory) during launch, and wind resistance, centrifugal force, and other environmental forces during flight. Piezoelectric generators can effectively convert external forces in the gun and during flight into electric energy for the use of the system, such as igniting the detonator. As a component connecting the piezoelectric structure and the power supply load, the energy harvesting circuit can convert a certain frequency of alternating current into direct current. Its functions include AC–DC conversion, power conditioning, voltage stabilization, and load matching.
In recent years, the structure and parameters of the recovery circuit have been studied by domestic and foreign scholars. On the one hand, the piezoelectric energy harvesting system is becoming smaller and easier to implement and operate. On the other hand, optimizing the circuit makes the loss of the system smaller and improves the output efficiency. In 2002, Ottmans et al. first applied the standard energy harvesting circuit (SEH) [4] and carried out modeling and theoretical analysis. In 2005, Guyomar et al. developed a parallel synchronous switching circuit (P–SSHI) [5], which used an inductor–capacitor resonant circuit to achieve a voltage flip when the equivalent current of the piezoelectric sensor changed direction at the peak value. This not only increased the voltage at both ends of the piezoelectric sensor but also accelerated the voltage flip direction, resulting in reduced loss. In 2006, Lefeuvre et al. put forward a series of synchronous switch–inductor recovery circuits (S–SSHI) [6], which served switches and inductors between the piezoelectric element and the rectifier bridge. The voltage of the piezoelectric element was nonlinearly synchronized by controlling the on–off of the switch, which improved the open–circuit output voltage and reduced the charge consumption of the equivalent capacitance inside the piezoelectric element, but controlling the on–off time and sequence of the switch was difficult. They also provided a synchronous charge extraction circuit (SECE) [7], which is used to disconnect the piezoelectric element from the rear load circuit for most of the time; this made the SECE have a decoupling effect, and the output power independent of the load. In 2010, Ramadass et al. designed and implemented a high–efficiency piezoelectric vibration energy harvesting chip based on P–SSHI technology [8]. Compared with the standard energy harvesting circuit, the output power increased by about four times. In 2011, Krihely et al. advanced an improved P–SSHI circuit [9]. Under constant harmonic excitation, compared to the standard energy harvesting circuit, the output power was enhanced by 2.3 times. In 2012, Junrui Liang et al. presented an enhanced self–powered SSHI (SP–SSHI) circuit [10]. The experimental results showed that the output power raised two times compared with the full–bridge rectifier circuit. In 2014, Dongyu Shi proposed a new energy recovery interface circuit (SCEI) [11], which combines the SECE circuit and the P–SSHII circuit, and its maximum recovered power is 1.5 times that of the SECE circuit as verified by the theoretical formula derivation and experimental circuit. In 2015, Lu et al. offered a simple and efficient P–SSHI circuit [12], in which two comparators were used to monitor the change of voltage at both ends of the piezoelectric energy harvesting device, and the MOSFET was used to control the on–off of the switch. In contrast to the traditional full–bridge rectifier circuit, the energy harvesting of the self–powered P–SSHI rectifier circuit was improved by 5.8 times. In 2017, Si jun Du et al. presented a synchronous switch harvesting on a capacitor circuit (SSHC) [13]. When the current of the piezoelectric element crossed zero, the SSHC circuit realized the voltage flip of the piezoelectric element through the multi–stage charge transfer between the external capacitance and the internal capacitance of the piezoelectric element. The circuit could improve the piezoelectric flip efficiency, and the output power has heightened by 9.7 times that of the standard piezoelectric energy harvesting circuit. In 2017, Zhiyuan Chen et al. came up with an inductorless capacitor–flipping rectifier for piezoelectric energy harvesting [14]. This new development realized the multi–stage bias flipping of the voltage at both ends of the piezoelectric element and achieved accurate zero–crossing detection. In 2018, Liang Junrui et al. proposed a synchronous three–bias voltage reversal power conditioning circuit [15]. The experimental results showed that the collection power of the circuit was 24.5% higher than that of the P–SSHI circuit. In 2019, based on the traditional SSHC circuit, Mickael Lallart et al. proposed a Synchronized Switch Harvesting on Oscillator (SSHO) circuit [16]. The experimental results showed that the output power of the circuit was increased by 30%. In 2019, Sundeep Javvaji et al. put forward a multi–stage bias flip circuit [17]. The experimental results showed that the voltage flip efficiency of this circuit was as high as 89.5%. In 2020, Xiaoliang Ding et al. designed an enhanced dual–intermediate capacitor energy recovery circuit (E–DICH) [18,19]. The results showed that the recovered power of the E–DICH is load–independent, and its maximum recovered power was improved by 440% and 90% when compared to the SEH circuit and SECE circuit, respectively.
Throughout the trajectory of the projectile, the piezoelectric structure effectively harnesses and transforms the vibration energy present within the airflow resonant cavity of the fuse head into electrical energy. This phenomenon is particularly pronounced due to the projectile’s considerable velocity, resulting in the generation of vibration energy at a significantly elevated frequency, consequently yielding an electric energy output of equally heightened frequency from the piezoelectric structure. The energy harvesting circuit within the ammunition system necessitates the retrieval of electrical energy at a heightened frequency, while simultaneously minimizing energy loss and enhancing the power output of the load. The circuit presented in this paper primarily serves the purpose of rectifying and optimizing the converted electric energy. The precise control of the synchronous switch in the SSHC circuit is achieved through the implementation of a zero–crossing detection circuit and pulse signal generation circuit, enabled by synchronous switch energy harvesting technology. Additionally, a third–order valley–filling circuit is added between the rectifier bridge and the load in order to improve the circuit power factor and achieve the purpose of increasing the output power.

2. Theoretical Model

As shown in Figure 1, during the flight of a projectile, the incoming air flows through a circular nozzle placed at the head of the projectile or the fuse. Initially, the airflow undergoes a transition from laminar to turbulent flow, generating stable pulsating turbulence. Subsequently, the vortex shedding phenomenon occurs (the vortex gradually loses stability in the fluid and breaks away from the fluid) in the airflow from the nozzle outlet, which causes the static airflow in the cavity outside the resonant cavity to form a vortex ring (rotating structure formed in the fluid also known as Carmen Vortex Street). At the sharp edge of the resonant cavity in the front end of the sound pipe, the vortex ring produces an edge tone, which induces the generation of a fluid–dynamic acoustic source [20,21].
The majority of this sound wave propagates through the holes inside the resonant cavity and reaches the bottom of the cavity. After reflection at the bottom of the resonant cavity, it encounters the vortex ring again at the nozzle exit. Due to the “fluid–solid–sound” coupling effect, the sound intensity is amplified, and the enhanced sound wave is propagated back through the holes inside the resonant cavity to its bottom. It is then reflected to the sharp edge, and this process repeats. The superposition of incident and reflected waves inside the resonant cavity eventually forms a standing wave state, resulting in a stable fluid–dynamic acoustic source (the source is sinusoidal). The standing wave as the vibration source directly acts on the transducer to output electrical energy, and the electrical energy processing circuit provides stable electrical energy to the load.
The piezoelectric model of energy harvesting structure is a three–layer cantilever beam structure. The upper and lower ends are connected to two electrodes, respectively, and the piezoelectric material is in the middle, as shown in Figure 2a [22]. When the projectile is flying in the trajectory, the airflow causes the free end of the cantilever beam to deform, and the piezoelectric material attached to the surface of the cantilever beam also deforms with the bending of the cantilever beam. Due to the piezoelectric effect of the piezoelectric material, the electrical energy is output from the upper electrode and the lower electrode of the piezoelectric material, which completes the conversion from mechanical energy to electric energy.
In order to simplify the electromechanical coupling model of the piezoelectric energy harvester, the equivalent circuit method is used to simplify the piezoelectric cantilever model for theoretical calculation and model simulation. The electromechanical coupling of the piezoelectric cantilever beam can be equivalent to a single degree of freedom system of spring–mass–damping, as shown in Figure 2b [23,24]. Since the acoustic source acting on the piezoelectric element is a stable fluid–dynamic acoustic source, which will be assumed to be sinusoidal in the article, the acoustic source acts on the piezoelectric element to cause vibration of the piezoelectric element, and therefore the motion displacement of the piezoelectric element is sinusoidal. Ignoring the loss of resistance of the piezoelectric element, the piezoelectric element can be equivalent to a circuit model with a current source and a capacitor in parallel, as shown in Figure 2c [25].
According to the kinetic law of energy conservation, the electromechanical equation and motion equation of the piezoelectric cantilever beam are
F + F p = M u ¨ + C u ˙ + K P E + K S u + α V
I = α u ˙ C P V ˙
where F denotes the external excitation force applied to the piezoelectric energy harvester; F p  indicates the reaction force generated by the inverse piezoelectric effect on the piezoelectric cantilever beam; u  specifies the equivalent mass displacement; C  refers to the equivalent damping of the piezoelectric energy harvester; K S  dictates the equivalent stiffness coefficient; M  is the equivalent mass, at the same time; V  and I  designate the output voltage and output current of the piezoelectric element, respectively; α  stands for the stress intensity factor of the piezoelectric element; C P  denotes the equivalent capacitance of the piezoelectric element; and K P E  dictates the short–circuit equivalent stiffness coefficient of the piezoelectric element.
The individual parameters in Equations (1) and (2) are calculated as follows:
C P = ε 33 S A x y d 0
α = e 31 A y z l
where ε 33 S  refers to the dielectric constant when S is zero or constant; e 31  stands for the piezoelectric stress factor; d 0  and l  denote the thickness and length of the piezoelectric element respectively; A x y  and A y z  designate the area of the upper and lower surfaces of the piezoelectric element and the lateral area respectively.
Suppose u = U M cos ω t , Equation (2) becomes
I = ω α U M sin ω t C P V ˙
Since I P = ω α U M , Equation (5) becomes
I = I M sin ω t C P V ˙
The RMS value of the open circuit voltage at both ends of the piezoelectric element is
V P = I M 2 ω C P = α U M 2 C P

3. SSHC Circuit of Single Capacitor

In Figure 3a,b, a single capacitor SSHC circuit diagram [26] and a timing diagram of the SSHC circuit [27] are shown. The circuit uses capacitance instead of inductance to realize the charge transfer of capacitance C P . The charge transfer between capacitance  C P  and  C 1  is controlled by opening and closing the switch, which accelerates the flip of the voltage at both ends of the piezoelectric element and improves the energy harvesting efficiency. Figure 3 shows the process of  V P T  flipping from positive to negative in the SSHC circuit of a single capacitor.
The working principle is as follows: in the whole working process, all switches are in the off state most of the time. Figure 3a shows the operation of the circuit before the voltage  V P T  flips from positive to negative, and the output of the piezoelectric element powers the load through the rectifier bridge. When the vibration displacement of the piezoelectric element reaches the maximum value, as shown in Figure 3c, the current  I P  is about to pass zero–point from the positive to negative, and the switch S2 is closed so that the capacitor  C P  charges  C 1 . Charging is completed until the voltages of the two capacitors are equal. At this time, the first phase of the voltage flip is completed, and the switch S2 is disconnected. Therefore, the voltage across  C P  and  C 1  is
V 1 = V P T = C P C P + C 1 V R + 2 V D
where  V 1 V P T V R , and  V D  are the voltages across the  C 1 , piezoelectric element,  R L , and diode conduction voltage, respectively.
As shown in Figure 3d, in the second stage, switch S1 is closed, which leads to the capacitor  C P  being short–circuited, and its voltage drops rapidly to zero, so that switch S1 is disconnected. Hence, the voltage across  C P  and  C 1  at the end of the second phase is
V 1 = C P C P + C 1 V R + 2 V D
V P T = 0
As shown in Figure 3e, in the third stage, switch S3 is closed, capacitors  C P  and  C 1  are connected in reverse parallel, and capacitor  C 1  reverses the charging of  C P  until the voltages of the two capacitors are equal. The third stage of voltage flip–flop is completed, and switch S3 is disconnected. At this time, the voltages  V P T  and  V 1  at the end of the third phase are
V 1 = V P T = C P C 1 ( C P + C 1 ) 2 V R + 2 V D
From Equation (11), it follows that  V P T  after flip–flop can take its maximum value when  C P  and  C 1  take equal values. The voltage flip efficiency is defined as the absolute value of the voltage ratio before and after the reversal; the efficiency of this voltage flip is 25%.
Since the  V P T  does not reach the threshold of diode conduction, the current source will charge the internal capacitor  C P . After reaching the threshold, the diode is turned on and supplies power to the load. When the  I P  passes the zero–point from the negative to positive, the second voltage flip begins.
After the second voltage flip, the voltage at both ends of  C P  and  C 1  is
V 1 = V P T = 5 16 V R + 2 V D
The result  V P T  at the end of the nth voltage flipping stage is
V P T = 1 3 V R + 2 V D n
From Equation (11), the voltage flip efficiency of the single–capacitor SSHC circuit is 33%.
The output voltage  V S  and power  P S  at the two ends of the load are, respectively,
V S = 2 α U M R L π + ( 1 λ ) ω R L C P
P S = V S 2 R L = 4 α 2 U M 2 ω 2 R L [ π + ( 1 λ ) ω R L C P ] 2
The relationship between the output voltage ripple ∆V and the input capacitance Cr of the valley–fill circuit is
V = I 2 f C r = π I ω C r
where ∆I is the ripple amplitude of load current and f denotes the frequency of the circuit.

4. Materials and Methods

4.1. Circuit Design Scheme

In the proposed energy harvesting circuit, the traditional zero–crossing detection is generally realized by a hardware zero–crossing comparator. However, in practical applications, the comparator is easily affected by offset voltage, noise, and harmonics. There is a large error between the zero point of the actual voltage and the extracted zero point, resulting in the output delay of the zero point signal, leading to a decrease in the output power of the circuit. In the traditional SSHC circuit, the discharge time of the capacitor is generally adjusted by manually controlling the value of the capacitor, and then the pulse width of the synchronous control signal is changed. On the one hand, this method is not accurate enough. On the other hand, it cannot adjust the pulse width adaptively, resulting in reduced output power.
Based on the above shortcomings, it can be seen from Scheme 1 that, based on the SSHC circuit of a single capacitor, this paper introduces a sampling resistor R1, and the zero–crossing signals PN and NP are output. After receiving two zero–crossing signals, the pulse generation circuit generates switch control signals K1, K2, and K3 to accelerate the voltage flip. In addition, a passive power factor correction circuit is added between the rectifier circuit and the load, which quickly stores power by series connection of capacitors during charging and releases more power by parallel connection of capacitors during discharging to increase the active power of the circuit.

4.2. Operational Principle

4.2.1. Double–Limit Zero–Crossing Detection Circuit

The double–limit zero–crossing detection circuit is to collect the zero–crossing signal of the current source. By extracting the voltage waveform, the two zero–crossing signals of the current source are obtained, namely from positive to negative and from negative to positive. As shown in Figure 4, this circuit is a double–limit zero–crossing detection circuit. The characteristic of the circuit is that the pulse width of the zero–crossing signal can be controlled by adjusting V2 and V3, and then the accuracy of the circuit control can be adjusted.
The circuit’s working principle is as follows: in a cycle, when the input signal Vin > V2, the 1–pin and 2–pin of the comparator output high level and low level, respectively, and through the AND gate output low level. When V3 < Vin < V2, the comparator’s 1–pin output remains unchanged, the 2–pin becomes high, and the high level is output through the AND gate. When Vin < V3, the comparator 1–pin output low level, 2–pin output unchanged, and through the AND gate output low level. When V3 < Vin < V2 occurs again, the comparator’s 1–pin output high level, the 2–pin output unchanged, and through the AND gate output high level. The above output signal through the AND gate is a zero–crossing signal V0, which is not distinguished. Input the V0 signal into the JK flip–flop whose J and K terminals are both high, pass the signal at the output of the JK flip–flop through the NOT gate, and then pass the output signal of the NOT gate and the V0 signal through the AND gate to obtain the PN signal. The signal at the output of the JK flip–flop and the V0 are passed through the AND gate to obtain the NP signal. The PN signal and the NP signal in the above represent the zero crossing signals of voltage from positive to negative and from negative to positive at the ends of the piezoelectric element, respectively. The double–limit zero–crossing detection circuit can adjust the reference voltage according to the required accuracy in order to meet the design requirements.

4.2.2. Pulse Signal Generation Circuit

As shown in Figure 5, the pulse signal generation circuit is driven by the zero–crossing signal in order to control the switches accurately in the SSHC circuit.
When VPT first flips from positive to negative, the working principle of the pulse signal generation circuit is as follows:
In the first stage, P1 is low level initially, then P1 and zero–crossing signal PN pass through the AND gate to make K1 high level, resulting in the switch S2 becoming closed, and Cp begins to charge C1. In the process of charging, the current flows through R1, and the voltage difference between the two ends of R1 is generated. The output signal amplified by the amplifier is reversed to obtain the A1 signal. The A1 signal is connected to the pulse extraction module, and the P1 signal will copy the rising edge signal of A1 and keep the high level to the PN signal clearing. At this time, the reverse P1 and PN pass through the AND gate, which leads to the K1 signal becoming low level, and the control switch S2 is disconnected. At the same time, since P2 is low level and K2 becomes high level, therefore, the switch S1 is closed.
In the second stage, after the A1 signal and the P1 signal after delay pass through the AND gate, the pulse of A1 in the first stage is filtered out. Then the rising edge of the A1 signal is extracted, and the P2 becomes and remains at a high level until the zero–crossing signal is cleared. At this time, P2 becomes low level and the switch S1 is disconnected. At the same time, since P3 is low level and K3 becomes high level, the switch S3 is closed.
In the third stage, the A1 signal and P2 after delay pass through the AND gate, filter out the pulses in the first two stages of A1, and then extract the rising edge, and P3 becomes and remains high level until the zero–crossing signal is cleared. At this time, K3 becomes low level, and the switch S3 is disconnected.
The above three stages are the description of the positive to negative flip process of voltage VPT, and the process of negative to positive flip is similar and no longer described.

4.2.3. Passive Power Factor Correction Circuit

The entire piezoelectric energy harvesting system uses a large number of nonlinear components, increasing the reactive power of the system, and, at the same time, leading to a lower power factor and a lower active power provided to the load. By correcting the power factor, the power factor angle of the entire system is increased, thereby improving the recovery efficiency.
As shown in Figure 6, the third–order Valley–fill circuit is charged and discharged by a capacitor paralleled behind the rectifier diode, so that the current flowing through the load RL is no longer a pulsating peak pulse. The working principle is as follows: when the voltage at both ends of the load RL begins to rise, the diodes D5 and D6 are turned on, and the diodes D7, D8, D9, and D10 are cut off. The steady–state sinusoidal excitation begins to charge the capacitors C2, C3, and C4 in the valley–fill circuit. At this time, C2, C3, and C4 are in series. According to the capacitance series formula, the total capacitance after the series is reduced, the capacitance will be filled quickly, and the capacitance filling time is reduced. When the voltage at both ends of the load RL begins to decrease after the peak, the diodes D7, D8, D9, and D10 are turned on, and the diodes D5 and D6 are cut off. The voltage generated by the steady–state sinusoidal excitation is smaller than the voltage across the capacitors C2, C3, and C4. The rectifier diode is turned off, and the capacitors C2, C3, and C4 are connected in parallel to supply power to the load RL until the next rectifier voltage peak arrives.
Compared to the second–order valley–fill circuit, the third–order valley–fill circuit has a faster capacitor charging and discharging speed, so that in a cycle of the piezoelectric vibrator displacement, the rectifier diode has more conduction time, and the harmonic content of the current waveform is less, thereby increasing more power factor angles and higher energy harvesting efficiency.

5. Results

5.1. Simulation Results

The circuit designed in this paper is simulated and analyzed by Multisim software. Due to the similar working process of voltage flipping from positive to negative and from negative to positive, this paper just simulates and analyzes the voltage flipping process from positive to negative. Because the ammunition system is small in size and thick in the wall, its natural frequency is high (generally kHz level). In this paper, 1 kHz is selected as the frequency of the current source.
In this paper, the piezoelectric ceramic is selected as the piezoelectric sheet, the diameter of the piezoelectric sheet is 30 mm, the thickness is 0.2 mm, at the same time,  ε 33 S = 2.08 × 10 8   F / m e 31 = 1.48   N / V m , and then the piezoelectric element is equivalent to the parallel connection of the current source and capacitance. After calculating and analyzing, the parameters of the main components are shown in Table 1.
From Figure 7a, the voltage V1 at both ends of the capacitor C1 always flips at the time of zero crossing, which is in line with expectations. From Figure 7b,c, it can be seen that NP and PN act as zero–crossing signals from positive to negative and from negative to positive in the zero–crossing waveform, respectively, realizing the distinction between the two zero–crossing signals. From Figure 7b,c, it can be seen that V2 and V3 are ±0.05 V and ±0.5 V respectively, and the width of the zero–crossing signal varies greatly, which also verifies the effectiveness of the double–limit zero–crossing.
Figure 7d,e shows the whole process of signal P1 generation. From the diagram, it can be seen that when the zero–crossing signal PN is high level, the A1 signal becomes the signal A2 after delay. When signal A2 is the rising edge, the signal P1 is triggered from low level to high level and maintained until the zero–crossing signal PN becomes low level. It can be seen that the signal P1 remains high level throughout the zero–crossing period after being triggered, which provides the condition for the subsequent AND operation to filter the signal.
Through the above description, it can be inferred that the generation process of signals P1, P2, and P3 is similar, and the difference is that the time and order are different. As shown in Figure 7f, all three signals are triggered after the delay of the signal A1 and remain until the zero–crossing signal PN becomes low level.
Figure 7g–i shows the generation process of switching signals K1, K2, and K3 in the main circuit, that is, when VPT flips from positive to negative or from negative to positive, the closing sequence of switching signals is different. From the diagram, when VPT flips from positive to negative, the closing sequence is K1–K2–K3. When VPT flips from negative to positive, the closing sequence is K3–K2–K1. The closing time of the three switching signals is also different, the reason is that the voltage at both ends of the flip capacitor and the time of charge transfer are different in the three stages of voltage flip.
The observation depicted in Figure 8a reveals a positive correlation between the load and the output voltage, with the rate of increase gradually diminishing. Additionally, Figure 8b demonstrates that higher Cr values enhance the stability of the output voltage, albeit at the cost of increased response time. Stability is mainly characterized by the fluctuation of the voltage value within a certain range, the smaller the range the better the stability. Response time is mainly the time it takes for the voltage value to reach a stabilized value. Due to the circuit’s application in a fuse, it becomes imperative to ascertain the value of Cr. In this study, a value of 1 μF has been chosen. As depicted in Figure 8c, it is evident that the load’s output voltage and output power exhibit an inverse relationship as the load intensifies, eventually reaching a state of gradual stabilization. Based on the data presented in Figure 8d, when the current source is 5 mA and the load is 10 kΩ, the voltage at both ends of the load remains constant at 3.75 V in the absence of the power factor correction circuit. Furthermore, the output power is measured to be 1.41 mW. Conversely, when the power factor correction circuit is employed, the voltage across the load stabilizes at 4 V, resulting in an output power of 1.6 mW. Consequently, it can be deduced that the implementation of the power factor correction circuit leads to a relative increase in output power of 13.5%.

5.2. Experimental Tests

In order to test the actual effect of the designed circuit, the proposed circuit is tested at the board level. Due to the limited laboratory conditions, the AC current source cannot be provided, so the piezoelectric element part is replaced by the output voltage source of the signal generator. The power supply of the active device is provided by the regulated power supply. The circuit part is welded as a PCB board. According to the data, the open circuit voltage of the piezoelectric element is 5~8 V. It is known through simulation that the voltage at the two ends of the equivalent circuit of the piezoelectric element is a sinusoidal waveform with a peak value of 5 V. Therefore, in this paper, a voltage source with a peak value of 5 V is used to replace the piezoelectric element. Figure 9 is the experimental picture, including the regulated power supply, signal generator, oscilloscope, and circuit board. The model of the regulated power supply is MT–152D, three–digit display, and display accuracy is plus or minus 0.5%. The display range of voltage is 0.00–9.99–16.0 V, and the display range of current is 000.–999. mA–2.1 A and the rated power is 30 W. The model of the signal generator is AFG–2225, which has a dual–channel output; the frequency range of its sine wave is 1 μHz~25 MHz, and the resolution is 1 μHz. The model of oscilloscope Tektronix DPO 4102B has a resolution of 8 bit, and the minimum measurement accuracy is 1 mV/div.
Figure 10 is the experimental waveform of the double–limit zero–crossing detection circuit. Figure 10a,d are PN, indicating that IP is zero–crossing from positive to negative, and Figure 10b,d are NP, indicating that IP is zero–crossing from negative to positive. By adjusting the size of the two reference voltages, the width of the zero–crossing signal can be changed to achieve a double–limit function.
Figure 11a shows the on–off of switches K1, K2, and K3 when the voltage VPT flips from positive to negative. Since the oscilloscope used in the experiment shows at most two channel waveforms at the same time, the following figures compare the waveforms of PN and K1, K1, and K2, and K2 and K3, respectively. It can be seen that the timing of the switch closure is K1–K2–K3, which is consistent with the simulation data. Figure 11b is the on–off condition of the switch K1, K2, and K3 when the voltage VPT flips from negative to positive. It can be inferred that the pulse generation circuit accelerates the voltage flip by controlling the on–off of the switch.
Figure 12 provides the curve of the theoretical prediction, simulation results, and experimental results of the output voltage variation with the load RL, which shows that although there is a certain gap between the simulation results and the experimental results compared to the theoretical prediction, the variation trend is the same and in line with the expectation.
When the generator outputs a sinusoidal voltage with a peak value of 5 V, the voltage at both ends of the uncorrected load is 3.7 V, and the load power is 1.369 mW, with a power factor of 0.75. The voltage at the piezoelectric element and the capacitor in the third–order valley–fill circuit is 4.3 V and 1.2 V, respectively. The voltage at both ends of the load with the power correction circuit is 3.9 V, and the output power is 1.52 mW, and the power factor of 0.93. The voltage at the piezoelectric element is 4.7 V, and the voltage of three capacitors in the third–order valley–fill circuit are all 1.3 V, The output power has increased by 11.1%, and the power factor has increased by 24%. Table 2 demonstrates the performance comparison of synchronous switch harvesting on a capacitor circuit, and it can be seen that the circuit proposed in this paper can not only operate at high frequencies for fusing environments but also that the output voltage and output power are improved with the addition of the power factor correction circuit. According to the information obtained, the minimum ignition voltage for a detonator is 2.7 V, indicating that the voltage generated by the energy harvesting circuit designed in this article is sufficient to reliably ignite the detonator.

6. Conclusions

The primary purpose of the circuit described in this paper is to convert the mechanical energy produced during the flight of the projectile into detonation electric energy through the utilization of a piezoelectric element. The circuit possesses the capability to not only regulate the pulse width of the zero–crossing signal, but also effectively govern the synchronous switch, and incorporate a power factor correction circuit to fulfill the voltage and power requirements during detonator detonation. Through the implementation of simulation analysis, it was observed that when the current source is 5 mA and the connected load is 10 kΩ, the voltage at both ends of the load in the absence of a power factor correction circuit measures 3.75 V, resulting in an output power of 1.41 mW. The voltage at both ends of the load with the power factor correction circuit is 4 V, and the output power is 1.6 mW, which relatively increases by 13.5%. The experimental results show that when the open circuit voltage of the piezoelectric element is 5 V, the frequency is 1 kHz, the load resistance is 10 kΩ, the voltage across the load without power factor correction is 3.7 V, and the power is 1.369 mW, with a power factor of 0.75. The voltage across the load with the power correction circuit is 3.9 V, and the calculated output power is 1.52 mW, and the power factor of 0.93. The output power is promoted by 11.1%, and the power factor has increased by 24%. Based on the current results, the future research direction of this project is the miniaturization and high efficiency of circuits.

Author Contributions

This paper was a collaborative work of all the authors. Conceptualization, S.L. and F.Z.; methodology, S.L. and F.Z.; software, F.Z.; validation, F.Z.; resources, S.L. and Y.H.; data curation, F.Z.; writing—original draft preparation, F.Z.; writing—review and editing, S.L.; visualization, F.Z.; supervision, S.L.; project administration, Y.H.; funding acquisition, S.L. and Y.H. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the Guangxuan Program Funding Project of Shenyang Ligong University (LJKMZ20220601).

Data Availability Statement

Not applicable.

Acknowledgments

This research was supported by the Guangxuan Program Funding Project of Shenyang Ligong University (LJKMZ20220601), we would like to express our appreciation to them.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Diagrams related to airflow generating sound waves. (a) Structure of airflow generating sound waves; (b) Diagram of the mechanism of the piezoelectric material bending under the influence of the projectile.
Figure 1. Diagrams related to airflow generating sound waves. (a) Structure of airflow generating sound waves; (b) Diagram of the mechanism of the piezoelectric material bending under the influence of the projectile.
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Figure 2. Theoretical model. (a) Traditional piezoelectric cantilever structure. (b) Equivalent model of piezoelectric energy harvesting. (c) Equivalent circuit model of the piezoelectric element.
Figure 2. Theoretical model. (a) Traditional piezoelectric cantilever structure. (b) Equivalent model of piezoelectric energy harvesting. (c) Equivalent circuit model of the piezoelectric element.
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Figure 3. The process of VPT flipping from positive to negative in the SSHC circuit of a single capacitor. (a) Operation of the SSHC circuit before the flip of VPT. (b) Timing diagram. (c) Phase 1. (d) Phase 2. (e) Phase 3.
Figure 3. The process of VPT flipping from positive to negative in the SSHC circuit of a single capacitor. (a) Operation of the SSHC circuit before the flip of VPT. (b) Timing diagram. (c) Phase 1. (d) Phase 2. (e) Phase 3.
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Scheme 1. Circuit design scheme.
Scheme 1. Circuit design scheme.
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Figure 4. Double–limit zero–crossing detection circuit.
Figure 4. Double–limit zero–crossing detection circuit.
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Figure 5. Pulse signal generation circuit.
Figure 5. Pulse signal generation circuit.
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Figure 6. Third–order valley–fill circuit.
Figure 6. Third–order valley–fill circuit.
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Figure 7. Waveform of simulation. (a) Comparison the waveform of V1 and VPT; (b) Waveform of double–crossing detection circuit when V2 and V3 are ±0.05 V; (c) Waveform of double–crossing detection circuit when V2 and V3 are ±0.5 V; (d) The generation process of P1 signal global graph; (e) The generation process of P1 signal local graph; (f) Signal generation process of P1, P2 and P3. (g) The generation process of switching signals K1, K2, and K3 global graph; (h) The generation process of switching signals K1, K2, and K3 from positive to negative; (i) The generation process of switching signals K1, K2, and K3 from negative to positive.
Figure 7. Waveform of simulation. (a) Comparison the waveform of V1 and VPT; (b) Waveform of double–crossing detection circuit when V2 and V3 are ±0.05 V; (c) Waveform of double–crossing detection circuit when V2 and V3 are ±0.5 V; (d) The generation process of P1 signal global graph; (e) The generation process of P1 signal local graph; (f) Signal generation process of P1, P2 and P3. (g) The generation process of switching signals K1, K2, and K3 global graph; (h) The generation process of switching signals K1, K2, and K3 from positive to negative; (i) The generation process of switching signals K1, K2, and K3 from negative to positive.
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Figure 8. Waveform of load output. (a) The waveform of output voltage changing with RL; (b) The waveform of output changing with Cr; (c) The waveform of output voltage and output power changing with RL; (d) The waveform of output voltage with RL =10 kΩ and Cr =1 μF.
Figure 8. Waveform of load output. (a) The waveform of output voltage changing with RL; (b) The waveform of output changing with Cr; (c) The waveform of output voltage and output power changing with RL; (d) The waveform of output voltage with RL =10 kΩ and Cr =1 μF.
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Figure 9. Pictures of the experiment.
Figure 9. Pictures of the experiment.
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Figure 10. Experimental waveform of double–limit zero–crossing detection circuit. (a) The waveform of IP and PN (upper and lower limit difference 0.05 V); (b) The waveform of IP and NP (upper and lower limit difference 0.05 V); (c) The waveform of IP and PN (upper and lower limit difference 0.5 V); (d) The waveform of IP and NP (upper and lower limit difference 0.5 V).
Figure 10. Experimental waveform of double–limit zero–crossing detection circuit. (a) The waveform of IP and PN (upper and lower limit difference 0.05 V); (b) The waveform of IP and NP (upper and lower limit difference 0.05 V); (c) The waveform of IP and PN (upper and lower limit difference 0.5 V); (d) The waveform of IP and NP (upper and lower limit difference 0.5 V).
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Figure 11. Waveform of pulse generating circuit: (a) The generation of PN, K1, K2 and K3 when VPT is from positive to negative zero crossing; (b) The generation of PN, K1, K2 and K3 when VPT is from negative to positive zero crossing.
Figure 11. Waveform of pulse generating circuit: (a) The generation of PN, K1, K2 and K3 when VPT is from positive to negative zero crossing; (b) The generation of PN, K1, K2 and K3 when VPT is from negative to positive zero crossing.
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Figure 12. Curve of output voltage with RL.
Figure 12. Curve of output voltage with RL.
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Table 1. Parameters of the main components.
Table 1. Parameters of the main components.
ParametersNotationValue
Current sourceIP5 mA,1 kHz
equivalent capacitance of the piezoelectric elementCP147 nF
stress intensity factorα0.93 mN/V
Flip–flop capacitorC1147 nF
Capacitance in valley–filling circuitsC2= C3= C4= Cr1 μF
Table 2. Performance comparison of synchronous switch harvesting on capacitor circuit.
Table 2. Performance comparison of synchronous switch harvesting on capacitor circuit.
Reference[13][15][17][18,19][27]This Work
Rectifier typeSSHCP–S3BFSSHIE–DICHSSHCSSHC
CP45 nF28.42 nF14 nF51 nF33 nF147 nF
Open–circuit voltage2.5 V15 V2 V10 V6.5 V5 V
Frequency92 Hz2π × 24.9 Hz441 Hz23.2 Hz140 Hz1 kHz
Output voltage5 V3 V1.8 V5.9 V4.24 V3.9 V
Output power0.45 mW24 μW24 μW348.1 μW1.80 mW1.52 mW
  P S P F B R 9.72.8764.485.444.2
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Liu, S.; Zheng, F.; Hao, Y. Research on the Optimization of Synchronous Switch Energy Harvesting Circuit Based on Capacitor. Electronics 2023, 12, 4070. https://doi.org/10.3390/electronics12194070

AMA Style

Liu S, Zheng F, Hao Y. Research on the Optimization of Synchronous Switch Energy Harvesting Circuit Based on Capacitor. Electronics. 2023; 12(19):4070. https://doi.org/10.3390/electronics12194070

Chicago/Turabian Style

Liu, Shuangjie, Fei Zheng, and Yongping Hao. 2023. "Research on the Optimization of Synchronous Switch Energy Harvesting Circuit Based on Capacitor" Electronics 12, no. 19: 4070. https://doi.org/10.3390/electronics12194070

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