A Wideband Power Amplifier in 65 nm CMOS Covering 25.8 GHz–36.9 GHz by Staggering Tuned MCRs

Abstract

Broadband millimeter-wave power amplifiers have attracted much attention and have wide applications for 5G communication, satellite communication, radar, sensing, etc. Yet, it is challenging to design a power amplifier with broadband small-signal gain and power performance simultaneously. In this study, a transformer-based symmetrical magnetically coupled resonator (MCR) matching network for broadband output matching and stagger-tuned MCRs are used to achieve both broadband small- and large-signal performance. Also, to enhance the gain for the power amplifier, a three-stage common-source pseudo-differential structure is adopted to mitigate the low-gain issue due to stagger tuning, and the shunt resistors aimed to decrease the Q factor of the MCRs. We used the in-phase two-way current combined with microstrip transmission lines to increase the output power. Designed in 65 nm bulky CMOS technology, the power amplifier presents a 3 dB small-signal gain bandwidth from 25.8 GHz to 36.9 GHz, indicating a peak gain of 25.87 dB at 30.5 GHz. The power amplifier demonstrates a 17.84 dBm saturated output power ($P_{sat}$) at 31 GHz and a 24.37% peak power added efficiency ($PA{E}_{max}$) at 28 GHz. The power amplifier achieves a flat $P_{sat}$ of 17.44 ± 0.4 dBm, a $PA{E}_{max}$ of 22.59 ± 1.78%, and an $O{P}_{1dB}$ of 13.78 ± 0.31 dBm from 26 GHz to 36 GHz.

1. Introduction

The development of 5G communication, satellite communication, and radar has attracted much interest and acquired great demands in high-rate wireless communication. There are mainly two ways to increase the data transmission rate: (1) improve the spectrum efficiency; (2) increase the bandwidth of the spectrum. With the same spectrum efficiency, the data transmission rate increases twice with the doubled bandwidth [1]. In the wideband millimeter-wave band region, an extreme data rate is delivered even under low-order modulation [2]. Also, the higher frequency decreases the antenna size, which is important for phase-array design [1]. The frequency regions n257 (26.5–29.5 GHz), n258 (24.25–27.5 GHz), and n260 (37–40 GHz) are specified as 5G FR2 frequency ranges by the 3 GPP 5G New Radio (NR) Standard [3,4]. Countries have adopted different frequency bands for 5G or other applications. If a single transmitter possesses the bandwidth to cover multiple or all of the regional frequency bands, it can roam internationally [1,5,6], which reduces the system cost and design difficulty. Also, for an FMCW radar, wideband is necessary for improving the range resolution ($▵R$) [7,8], which is estimated using

$$▵R=\frac{c}{(2\ast BW)}$$

(1)

in which BW is the bandwidth of the radiated chirp [8]. Power amplifiers (PA), one of the most important blocks in millimeter-wave transmitters, have attracted more and more attention, with their output power and bandwidth having important effects on the whole system. The output power of the PA determines the signal distance, and the bandwidth greatly influences the data transmission rate. The challenge of designing a broadband PA is to sustain the wideband small-signal frequency response and broadband power performance simultaneously [9]. There are mainly four ways to achieve wideband millimeter-wave silicon-based power amplifiers: (1) distributed amplifiers; (2) stagger tuning; (3) high-order matching networks; and (4) feedback networks. Distributed amplifiers usually occupy a large area of chip size [10], and achieving a wideband optimal load impedance is difficult in this way [11]. Also, at each stage of the distributed amplifiers, the load impedance is not the optimal value for power matching, leading to a decreased efficiency of the power amplifiers [12,13]. The stagger-tuning technique makes the multiple amplification stages cascade and resonate at different frequencies to flatten the total gain response [1], which is usually effective to achieve small-signal broadband [14,15]. In addition, the stagger tuning method sacrifices the gain of the amplifier [16]. High-order matching networks, like Chebyshev filters or high-order LC filters, often consist of several passive components, resulting in a high insertion loss. The feedback technique, i.e., resistance–capacitance feedback network, suffers from deteriorated output power and efficiency [7,17]. Transformers or transformer-based magnetically coupled resonators (MCR) are high-order LC networks with only one inductor area that are widely used for wideband power amplifiers and low-noise amplifiers [7,16,18]. Jia et al. designed a wideband power amplifier with a symmetrical transformer-based MCR providing wideband optimal load impedance [16]. Wang et al. demonstrated a compact wideband high-linear-power amplifier covering 24–42 GHz using a custom-designed distributed balun with wideband optimum load impedance [5]. Chou et al. presented a V-Band wideband power amplifier with the help of a transformer-based radial power combiner and the stagger tuning technique [19]. All these power amplifiers use transformer-based or distributed-balun-based MCRs to realize wideband optimal load impedance by carefully selecting the MCR parameters. Wang et al. indicated that a wideband (46–101 GHz) power amplifier with a high-k interstage transformer can be compensated via a single-peak output-matching network [7]. To further decrease the gain ripple, a Gm compensator-based negative feedback chain is also applied. Wei et al. presented a wideband LNA by adding the peaks and valleys of the different resonators [18]. Xue et al. [20] proposed two W-Band wideband power amplifiers by staggering the transformers’ resonating frequency using an in situ transformer-coupled resonating peak control simulation methodology to realize 9/16 GHz 3 dB small-signal bandwidth. In reference [21], the transformer-based resonating peak tuning and staggering method was also used to achieve two wideband power amplifiers covering the 16/14 GHz 3 dB small-signal bandwidth. Several studies [18,20,21] have adopted the transformer-based staggering method and only small-signal wideband performance was achieved. Meanwhile, the design of the transformer-based staggering method lacks detailed elaboration. For example, reference [20] used a staggering method to flatten the bandwidth but without detailed method processes and particulars. In our work, we give not only the detailed design process but also the detailed whole logical thinking perspectives and design method for a wideband power amplifier. In this work, a symmetrical transformer-based output MCR4 is used to provide wideband optimal load impedance for the power stage. At the interstage between the power stage and driver stage 2, an asymmetrical MCR3 is used to realize wideband matching by making it satisfy both the conditions of ${\mathsf{\omega }}_1$ = ${\mathsf{\omega }}_2$ and a good matching at 35 GHz. At the interstage between driver stage 1 and driver stage 2, an asymmetrical MCR2 to form a high-pass form Z21 for stagger tuning is realized by selecting the transformer parameters under the condition of matching at 33 GHz. The input asymmetrical MCR1 is used to achieve wideband response and to compensate for the gain decline at the band edge ($f_L$ and $f_H$). The symmetrical output MCR4 for wideband optimal $Z_{opt}$ (leading to wideband large-signal performance) and stagger-tuned interstage and input MCRs for flattened small-signal bandwidth are combined for a better performance. The framework of the paper is organized as follows: A detailed analysis of the design of the four MCRs for input, output, and interstage matching is introduced in Section 2. Section 3 presents the whole circuit design consideration of the power amplifier. Section 4 shows the simulation results, and Section 5 concludes the entire work.

2. Analysis and Design

Figure 1a is the schematic of the designed broadband power amplifier. To increase the output power, two-way current-combining is used with stronger symmetry than voltage-combining [22]. Figure 1b is the cell stage of the power amplifier. In this work, we aim to design the output matching network for realizing a wideband $Z_{opt}$ for the power stage. The interstage matching network between power stage and driver stage 2 is used to achieve wideband impedance matching. We also design the interstage matching between driver stage 2 and driver stage 1 to realize a high-pass form filter for the staggering. The input-matching network is used to tune the gain shape of its stage by adopting a $\mathsf{\omega }/Q$-compensated asymmetrical MCR to enhance the gain at the band edge ($f_L$ and $f_H$), so that a flattened wideband performance of the whole circuit is achieved.

2.1. Wideband Output Matching Network Design

Wideband output matching network, which transfers the load impedance to $Z_{opt}$ for the power stage in a wideband frequency range, is the key factor for large power characteristics of a PA [23]. A symmetrical MCR could be used to achieve the broadband $Z_{opt}$ [16]. In a symmetrical MCR, as shown in Figure 2,

$$Q_1=Q_2=Q_0$$

(2)

$${\mathsf{\omega }}_1={\mathsf{\omega }}_2={\mathsf{\omega }}_0$$

(3)

in which

$$Q_0=Q_1=Q_2={\mathsf{\omega }}_1{R}_1{C}_1={\mathsf{\omega }}_2{R}_2{C}_2$$

(4)

$${\mathsf{\omega }}_0={\mathsf{\omega }}_{1,2}=\frac{1}{\sqrt{L_1{C}_1}}=\frac{1}{\sqrt{L_2{C}_2}}$$

(5)

K is the coupling coefficient between the two inductors, as shown in Figure 2. In this work, the interest frequency band is from 26 GHz to 36 GHz. As the output power and power gain at low frequency is larger than that at high frequency, we choose 32 GHz rather than 31 GHz as the center operation frequency to calculate the parameters of the output-matching MCR. Based on the loadpull simulation, we choose $Zopt$ = (26 + j*26) $\mathsf{\Omega }$ for the power stage at 32 GHz. The conjugate of Zopt is $Zop{t}^{\ast }$ = (26 − j*26) $\mathsf{\Omega }$, which is equivalent to a resistor of $R_1$ = 52 $\mathsf{\Omega }$ parallel with a capacitor of $C_{11}$ = 95.65 fF, as shown in the lumped model of the output symmetrical MCR in Figure 3. The symmetrical MCR transfers the input impedance of the power combiner to $Zopt$ for the power stage. The power combiner at the output, as shown in the dashed line on the top of Figure 1a, is designed to reactively transfer the load impedance to $Z_T$ = (27.86 − j*25.96) $\mathsf{\Omega }$ for the output transformer by using microstrip transmission-line segments. In the output symmetrical MCR shown in Figure 3, $C_1=C_{11}+C_{12}$, $C_2=C_{21}+C_{22}$. $C_{12}$ represents the extra added capacitor on the primary side if needed. $C_{21}$ represents the equivalent paralleled output capacitance of the power combiner input impedance ($Z_T$), which is 89 fF in this work. $C_{22}$ represents the extra added capacitor on the right side if needed. $R_2$ represents the equivalent paralleled output resistor of the power combiner input impedance ($Z_T$), which is also 52 $\mathsf{\Omega }$ in this work. For a symmetrical MCR, the coupling factor k and Q factor satisfy the equations below under the no in-band ripple condition [16]:

$$Q=\sqrt{\frac{-1+\sqrt{1+4\ast {\left({\mathsf{\omega }}_c{R}_1{C}_1\right)}^4}}{2}}$$

(6)

$$k=\frac{1}{\sqrt{1+Q^2}}$$

(7)

$$L_1=\frac{{R_1}^2{C}_1}{Q^2}$$

(8)

$$\frac{L_1}{L_2}=\frac{R_1}{R_2}$$

(9)

$$C_2=\frac{R_1}{R_2}\ast C_1$$

(10)

in which ${\mathsf{\omega }}_c$ is the center operation frequency with 32 GHz, as mentioned above.

Assuming $C_{12}$ is 19 fF (could be changed in a later design stage if needed), then the total left capacitance $C_1=C_{11}+C_{12}$ is calculated to be 114.69 fF. An initial assumption of $C_{12}$ of 19 fF is based on the fact that there is usually parasitic capacitance of the transformer [16], and extra added capacitor $C_{12}$ can be used as an additional degree of freedom to facilitate the design of MCR. $C_{12}$ should be as small as possible because a larger $C_{12}$ (leading to a larger $C_1$) results in decreased GBW of the MCR [16]. According to Equations (6) and (7), Q = 1.0116, and k = 0.703 are obtained. According to Equations (8)–(10), we obtain that $L_2$ = $L_1$ = 303.26 pH, $C_2$ = $C_1$ = 114.69 fF, and $C_{22}$ = 25.69 fF at 32 GHz, respectively. Some iterations of the calculation and design tuning of the values of Q, k, $L_1$, $L_2$, and $C_{12}$ are necessary to make these parameters satisfy the no in-band ripple condition equations. Figure 4 presents (a) the 3D view of the output transformer (TF4 in Figure 1) in the symmetrical MCR and (b) its layer structure. To achieve a coupling factor k as high as 0.7, a combination of interleaved and stacked structures is employed [24,25,26], as shown in Figure 4b. The primary inductor of the stacked part is metal 8 paralleled with metal 7. The secondary inductor consists of metals 8 and 9 and the AP layer in parallel. These paralleled metals increase the Q factor of the windings. Also with a high k factor, according to Formula (11), the insertion loss of the transformer is decreased, in which $\eta$, $Q_p$, $Q_s$, and k represent the passive efficiency, the Q factor of primary/secondary windings, and the coupling coefficient of the two windings, respectively [5]. The distance between AP layer and metal 8 is as far as 4.94 $\mathsf{\mu }$m, so the parasitic capacitance between $L_1$ and $L_2$ is not high enough to affect the SRF of the output transformer seriously. Figure 5a,b show the finally realized inductance and Q factor of $L_1$ and $L_2$. Figure 6a shows the k between $L_1$ and $L_2$, and Figure 6b shows the 3D view of the whole output matching network, respectively.

$$\eta =\frac{1}{1+2\ast \sqrt{\frac{1}{k^2{Q}_p{Q}_s}(1+\frac{1}{k^2{Q}_p{Q}_s}})+\frac{2}{k^2{Q}_p{Q}_s}}$$

(11)

The power gain of the whole output matching network is presented in Figure 7a. The power gain is defined as [27]:

$$G_p=\frac{P_L}{P_{in}}$$

(12)

in which $P_L$ represents the power delivered to the load, and $P_{in}$ represents the power fed into the network. This factor takes into account the situation that the load impedance is not always matching [27]. The minimum loss is −1.376 dB at 28.1 GHz. In general, from 25 GHz to 40 GHz, the loss at high frequency is larger than that at low frequency. Figure 7b presents the trans-impedance (Z21) of the MCR4 with Z21 being defined as [28]:

$$Z21\left(dB\mathsf{\Omega }\right)=20log(\frac{v_2}{i_1}){|}_{i_2=0}$$

(13)

in which $v_2$, $i_1$, and $i_2$ are defined in Figure 2. Compared with an ideal lossless symmetrical MCR, the finite Q parameter of the lossy transformer makes the two amplitude peaks of Z21 not equal anymore [29]. Also, the practical coupling factor k of a lossy transformer is not a constant value compared with an ideal transformer. The test schematic for the Z21 of MCR4 with a 50 $\mathsf{\Omega }$ resistor at the input is shown in Figure 8. Although the input-matching condition of the power stage affects the test results, the power stage has good isolation due to the neutralization capacitors. Therefore, directly connecting a 50 $\mathsf{\Omega }$ resistor at the power stage input does not have a significant impact on the test results of the Z21. Also, the test iteration for Z21 is needed when the matching passives are designed. As a result, the initial Z21 test result is used to provide an intuitive perception of the gain shape. With the matching network being placed in the circuit, the “in-situation” Z21 test method takes the circuit parasitics into account [20].

Figure 9a shows the power gain (Gp) of the power stage with the whole output matching network. From Figure 9a, we can see that the peak power gain at low frequency is much higher than that at high frequency, which has a similar trend as the Z21 shown in Figure 7b. Figure 9b presents a flattened input impedance of the output symmetrical MCR4 (including $C_{11}+C_{12}$ of the power stage) over a wide frequency band, especially a wide band near zero imaginary part, which means that the capacitor ($C_{11}+C_{12}$) resonates with the right side impedance $Z_{right}$ shown in Figure 3, so that the drain of the output stage transistors can see a nearly pure real Ropt. The test circuit for the power stage with the whole output matching network is shown in Figure 10. With ideal LC input-matching networks at every single-frequency point, the large-signal performance of the power stage is tested from 26 GHz to 36 GHz and the results are shown in Figure 11a,b. For the large-signal performance, the power stage achieves a $P_{sat}$ of 17.87 dBm at 31 GHz, a $PA{E}_{max}$ of 33.55% at 26 GHz, and a 14.4 dBm $O{P}_{1dB}$ at 31 GHz and 32 GHz. From Figure 11b, the simulated results reveal over a 17.3 dBm $P_{sat}$, over a 25% $PA{E}_{max}$, and over a 13.8 dBm $O{P}_{1dB}$ from 26 to 36 GHz, which explains the wideband load–pull matching achieved by the whole output matching network.

2.2. Interstage Matching Network Design

For the interstage matching network between the power stage and driver stage 2, the target is to achieve broadband matching between driver stage 2 output impedance and power stage input impedance. In transformer matching, we uses a simplified lumped T-model, shown in Figure 12, to estimate the size/parameters of the transformers [30]. For a transformer-based MCR, both the bandwidth and in-band ripple increase with higher coupling factor k, which has been investigated previously in references [16,31,32,33]. Meanwhile, the higher k results in lower insertion loss of the transformer. Considering that the TF1 and TF2 in MCR1 and MCR2 (shown in Figure 1) are used to adjust the small-signal bandwidth performance of the power amplifier, a higher k is preferred for TF3 (transformer 3 in MCR3 shown in Figure 1) regardless of the higher in-band ripple. Usually, the gate impedance has a higher Q factor than the output impedance of the transistor, and the higher Q results in increased gain ripple [16]. Adding paralleled resistors at the gate is an alternative way to reduce the Q factor and to extend the bandwidth [16,34]. Two 150 $\mathsf{\Omega }$ resistors (Rg at the power stage) are added at the gate of the power stage. Then, the input impedance of the power stage after adding resistors at the gate is ZM1 = 16 − j*43.6. The output impedance of driver stage 2 is ZM2 = 33.56 − j*62.78. The equivalent T matching of TF3 and the specific structure of MCR3 are shown in Figure 13a,b, respectively. In the MCR3, the output impedance of diver stage 2 (ZM2) is equivalent to a paralleled tank including a resistor $R_1$ and a capacitor $C_1$. The input impedance of the power stage (ZM1) is equivalent to a paralleled tank including a resistor $R_2$ and a capacitor $C_2$. The ZM2 is affected by the input-matching condition of driver stage 2 due to the non-zero S12 of the transistors. Considering that the neutralization technique is used for all three stages to cancel out the effect of Cgd of the transistors, the S12 for all three stages is small enough so that the ZM2 of driver stage 2 is not severely affected by the previous matching condition. Also, simulation iterations can be set to reset the value of ZM2. The TF3 is used to match ZM1 and ZM2. According to reference [35], when the two resonators of an MCR satisfy the condition of ${\mathsf{\omega }}_1$ = ${\mathsf{\omega }}_2$, the peak Z21 of an asymmetrical MCR is almost the same as that of a symmetrical MCR, and the mismatch of ${\mathsf{\omega }}_1$ and ${\mathsf{\omega }}_2$ will deteriorate the insertion loss, especially at a higher frequency. In MCR3, $Q_1$ = 1.87 and $Q_2$ = 2.725 are obtained at 35 GHz. With a lower $Q_1$ and ${\mathsf{\omega }}_1$ = ${\mathsf{\omega }}_2$, the MCR3 achieve a better flat response and the mismatch of $Q_1$ and $Q_2$ could be accepted [35]. With the help of TF3, the matching between ZM1 and ZM2 has lots of matching trajectories, only including the T-model or T-model with extra capacitors, as shown in Figure 14a. Considering that the gain and output power of the transistors decrease as the operating frequency increases, the matching trajectory of TF3 is designed to achieve a good match at 35 GHz, and also ${\mathsf{\omega }}_1$ = ${\mathsf{\omega }}_2$ is set at 35 GHz, as shown in Figure 14b. Thus, a good match between ZM1 and ZM2 at 35 GHz and ${\mathsf{\omega }}_1$ = ${\mathsf{\omega }}_2$ for a better flat response are both satisfied for MCR3. Figure 15 presents the 3D view of the practical designed TF3. For the finally realized TF3, L1 is 561.46 pH and L2 is 348.62 pH with k being 0.525 at 35 GHz. Figure 16a presents the matching situation between power stage input impedance (ZM1) and $Z_{left}$ (shown in Figure 13b) from 26 GHz to 36 GHz. A good match (S11 below −11 dB) between ZM1 and $Z_{left}$ is achieved from 26 GHz to 36 GHz. Figure 16b shows the Z21 of MCR3 (TF3 is included) with the similar test method of MCR4 mentioned above. In Figure 16b, the Z21 magnitude at low frequency (25–30 GHz) is higher than that at higher frequency (35–40 GHz).

For the interstage matching network between driver stage 1 and driver stage 2, which is part of MCR2, it aims to achieve a high-pass form Z21 to compensate for the gain drop in MCR3 and MCR4 at high frequency. To achieve the high-pass form Z21, 33 GHz is selected as the initial matching frequency point between the input impedance of driver stage 2 (Zin-diver2) and the output impedance of driver stage 1 (Zout-driver1). At 33 GHz, Zin-driver2 = 30.62 − j*72.94 and Zout-driver1 = 50.48 − j*130.14, which is equivalent to parallel R and C of (204.37 $\mathsf{\Omega }$||56.21 fF) and (385.99 $\mathsf{\Omega }$||32.21 fF), respectively, as shown in Figure 17. Actually, there are lots of alternative transformers with different parameter combinations to match Zin-driver2 and Zout-driver1 at 33 GHz. The frequency points of the two peaks of Z21 for an MCR are affected by $\frac{1}{\sqrt{L_1{C}_1}}$, $\frac{1}{\sqrt{L_2{C}_2}}$, and the coupling coefficient k [36]. Thus, the peak Z21 positions for MCR2 is adjusted by tuning these parameters. Figure 18 presents a group of Z21 lines with different $L_1$, $L_2$, and k. In all four cases, Zin-driver2 and Zout-driver1 are conjugate-matched at 33 GHz. In Figure 18, different parameter combinations of the transformers have different peak Z21 positions and different in-band ripples, resulting in different Z21 gain shapes with matching networks inserted in the amplifier. A combination of $L_1$ = 585 pH,$L_2$ = 320 pH, and k = 0.462 (red line in Figure 18) is selected for TF2 to achieve the high-pass Z21 shape of MCR2. The two Z21 peaks are located at 32.5 GHz and 47.5 GHz, respectively, as shown in Figure 18. Figure 19a presents the 3D view of transformer 2 (TF2) in MCR2. Figure 19b shows the Z21 of MCR2 with a similar test method to those of MCR3 and MCR4, as mentioned above, by using the EM simulation result of TF2. Like the cases in MCR4 and MCR3, a finite Q of the inductors makes the Z21 line of MCR2 different from that using an ideal transformer (red line in Figure 18). However, the average magnitude of the Z21 from 32.5 GHz to 40 GHz is relatively higher than that from 25 GHz to 32.5 GHz. Therefore, it indicates that a high-pass form Z21 is achieved.

2.3. Input-Matching Network Design

For the input-matching network, an asymmetrical MCR1 satisfying ${\mathsf{\omega }}_1/{\mathsf{\omega }}_2$ = $Q_1/Q_2$ and resulting in two equal Z21 peaks, is used to extend the bandwidth [16]. Figure 20a presents the lumped model of MCR1 based on TF1 for matching. The input impedance of the input stage (ZM1 = 42.94 − j*119 at 36 GHz) is equivalent to a paralleled tank including a resistor $R_2$ and a capacitor $C_2$. The output impedance of the power splitter (ZM2 = 82.16 − j*22.12 at 26 GHz) is equivalent to a paralleled tank including a resistor $R_1$ and a capacitor $C_{11}$. The power splitter is designed by using microstrip transmission-line segments to reactively match the impedance and split the input power to the two-way driver stage 1 in-phase, as shown in Figure 20b. $C_{12}$ on the left side is the extra added capacitor to satisfy the condition of ${\mathsf{\omega }}_1/{\mathsf{\omega }}_2$ = $Q_1/Q_2$ for the asymmetrical MCR1. In MCR1, we set ${\mathsf{\omega }}_1$ = 26 GHz, ${\mathsf{\omega }}_2$ = 36 GHz. For the input stage, as shown in Figure 1, a pair of paralleled Rg of 500 $\mathsf{\Omega }$, and a pair of series Rs of 10 $\mathsf{\Omega }$ are added at the gate of the input transistors. All these resistors decrease the Q factor of the input impedance of the transistors. Also, Rs improves the common mode stability of the circuit. After adding these resistors, the input impedance of the input stage ZM1 is 42.94 − j*119 at 36 GHz. Its equivalent paralleled resistance and capacitance are $R_2$ = 372.7 $\mathsf{\Omega }$ and $C_2$ = 32.87 fF, respectively. As $L_2$ resonates with $C_2$ at 36 GHz, we obtain $L_2$ = $\frac{1}{{\mathsf{\omega }}_2^{2}C2}$ = 594.6 pH and $Q_2$ = ${\mathsf{\omega }}_2$*$R_2\ast C_2$ = 2.771. Based on ${\mathsf{\omega }}_1/{\mathsf{\omega }}_2$ = $Q_1/Q_2$, we obtain $Q_1$ = 2 and $C_1$ = 139 fF. As $L_1$ resonates with $C_1$ at 26 GHz, we acquire $L_1$ = $\frac{1}{{\mathsf{\omega }}_1^2{C}_1}$ = 269.5 pH. As mentioned above, $C_{11}$ is the equivalent output paralleled capacitor of the power splitter, which is 18.7 fF at 26 GHz in this work; thus, the added extra capacitor $C_{12}$ is 120.33 fF (equals to ($C_1-C_{11}$)). So far, the coupling factor k between $L_1$ and $L_2$ has not been determined. Usually, a higher k makes the two Z21 magnitude peaks of an MCR be apart from each other [16,31,32,33]. Figure 21 shows the Z21 of the MCR1 with a k increasing from 0.3 to 0.7, when the inductors and capacitors are all ideal components. With an increasing k, both the bandwidth and in-band ripple are increased. Considering the target frequency, in-band ripple, and the difficulties of an actual transformer implementation, a k of 0.573 at 32 GHz is selected and achieved for this MCR1. The 3D view of the input transformer (TF1) is shown in Figure 20b. The primary inductance ($L_1$) at 26 GHz is 266.65 pH, and the secondary inductance ($L_2$) is 596.4 pH at 36 GHz for the finally achieved practical transformer.

Figure 22a presents the Z21 of MCR1 with the whole input-matching network shown in Figure 20b. Compared with the initial desire with the condition of ${\mathsf{\omega }}_1/{\mathsf{\omega }}_2$ = $Q_1/Q_2$, the two Z21 peaks are not equal anymore. The loss of the transformer affects the Z21 response [29]. Meanwhile, the equivalent $R_1$, $R_2$, $L_1$, $L_2$, and k being non-constant with frequency also affects the Z21 response. In Figure 22a, the Z21 magnitude of MCR1 at the frequency edge (from 25 GHz to 40 GHz) is much higher than that at the frequency center (from 30 GHz to 35 GHz). Therefore, the Z21 drop at the band edge is compensated, like the case in reference [7]. Figure 22b presents the Z21 of each MCR and the Z21 of the total circuit. It indicates that the Z21 amplitudes of the first and second MCRs compensate for that of the third and the fourth. Therefore, a wideband total Z21 of the whole circuit from input to output is achieved.

3. The PA Circuit Implementation

Figure 1 shows the architecture of the implemented wideband power amplifier. Three common-source stages are used to improve power gain and to stagger the Z21 of each MCR stage conveniently. Output power is increased by two-way current-combining. The matching networks mainly consist of transformer-based MCRs between each stage and transmission lines for the input and output. The gate biases of the transistors are supplied through the center tap of the transformers (TF1, TF2, and TF3) by series resistors (R1) of 250 $\mathsf{\Omega }$ to improve common mode stability [37]. Especially for the input stage, series resistors Rs of 10 $\mathsf{\Omega }$ are inserted between gate and the input transformer (TF1) to further suppress the common-mode oscillation. Pseudo-differential NMOS pair with neutralization capacitors has been employed to all the stages. The neutralization capacitors implemented via metal–oxide–metal are used to tackle the negative feedback and to improve reverse isolation [37]. Then, both the power gain and stability are improved. Shunt resistors are added at the gate of each stage to reduce the Q factor of the impedance, to help implement matching, and also to improve the stability of the circuit. Figure 23a presents the Gmax and stability of the 128 $\mathsf{\mu }$m transistor used in the output differential pair versus the values of neutralization capacitance (Cneu) at 32 GHz. Gmax1 and Kf1 present the condition without gate paralleled resistors, and Gmax2 and Kf2 present the condition that two 150 $\mathsf{\Omega }$ gate paralleled resistors (Rg for output stage) are added. It indicates that the Cneu range sustaining Kf > 1 is extended from about 23.9% to 51.7%. Also, the Gmax decreases by about 3 dB when Cneu is 37 fF. Considering that the whole circuit is composed of three cascaded circuit stages, the gain reduction induced by these shunt resistors at each stage is acceptable. Figure 23b shows the Gmax and Kf at different frequencies with shunt resistors added. It demonstrates that the Cneu ranges sustaining Kf > 1 at different frequencies are almost the same. Even at 40 GHz, the Gmax is bigger than 11.75 dB. The neutralization capacitance (Cneu) selected for the three stages are 37 fF/17 fF/9.5 fF, respectively. All the neutralization capacitors are implemented with parallel-plate metals. In this work, 2*32/1*32/1*16 fingers with a finger width of 2 µm (128 $\mathsf{\mu }$m*2 for the output stage differential pair) for the output stage, driver stage 2, and driver stage 1 are used for better performance. The metal lines on transistors are simulated using a 3D EM simulator. The 1.1 V VDD supply is fed through the center tap of the transformers. The 0.6 V VGS for the power stage and driver stage 2 and 0.55 V for driver stage 1 are selected for the consideration of output power and PAE.

4. Results and Discussion

A wideband power amplifier is designed in 65 nm CMOS technology and the layout is shown in Figure 24a. The area of the chip core is about 0.686 mm*1.933 mm. Figure 24b presents the simulated S-parameters of the designed power amplifier. The peak small-signal gain is 25.87 dB at 35.5 GHz, with a 3 dB bandwidth of 11.1 GHz from 25.8 GHz to 36.9 GHz. The output reflection coefficient is lower than −10 dB from 22 GHz to 43.5 GHz while the worst input reflection coefficient is only lower than −3 dB as the design goal is to broaden the bandwidth of the gain rather than wideband input matching at the input. Benefiting from the multiple-neutralization-stage design, the reverse isolation is better than −100 dB from 20 GHz to 40 GHz, as shown in Figure 25a. The stability factor Kf is greater than 1000 for all the frequencies. The large-signal performance versus input power (Pin) at 28/31/32 GHz is shown in Figure 25b. Biased at 1.1 V supply voltages for all the three stages, the power amplifier achieves a $P_{sat}$ of 17.57 dBm/17.84 dBm/17.81 dBm, a $PA{E}_{max}$ of 24.37%/23.59%/23.12%, a $O{P}_{1dB}$ of 13.92 dBm/14.09 dBm/14.04 dBm, and a $PA{E}_{P1dB}$ of 10.24%/10.53%/10.38% at 28/31/32 GHz, respectively. Also, as shown in Figure 26a, at the frequency edge of interest, i.e., 26 GHz and 36 GHz, a $P_{sat}$ of 17.04 dBm/17.04 dBm, an $O{P}_{1dB}$ of 13.54 dBm/13.47 dBm, a $PA{E}_{max}$ of 23%/20.81%, and a $PA{E}_{P1dB}$ of 9.45%/9.27% are achieved, respectively. To check the wideband large-signal performance of the designed power amplifier, Figure 26b presents the $P_{sat}$, $O{P}_{1dB}$, $PA{E}_{max}$, and $PA{E}_{P1dB}$ from 26 GHz to 36 GHz. The designed power amplifier achieves a $P_{sat}$ of 17.44 ± 0.4 dBm with a $PA{E}_{max}$ of 22.59 ± 1.78%, and an $O{P}_{1dB}$ of 13.78 ± 0.31 dBm under the 1.1 V supply voltage. Compared with the results of the only power stage with ideal LC input matching in Figure 11b, the average $P_{sat}$ and $O{P}_{1dB}$ deteriorate from 17.66 dBm and 14.21 dBm to 17.52 dBm and 13.85 dBm from 26 GHz to 36 GHz, respectively. The average $PA{E}_{max}$ decreases from 29.46% to 23.04%. The results prove that the designed power amplifier achieves wideband performances in both small- and large-signal performance using the wideband output symmetrical MCR and the staggered MCRs between stages.

Table 1. Performance comparison with the state of the art.

	TCAS-II 2021 [38]	TCAS-II 2021 [23]	MWCL 2022 [29]	ISSCC2017 [39]	This Work
Technology	130 nm SiGe	28 nm CMOS	28 nm FD-SOI	40 nm CMOS	65 nm CMOS
Frequency (GHz)	35	24/26/28/30	30	27	31/32
Peak gain (dB)	25.3	21.2	19	22.4	25.87 dB@35.5 GHz
3 dB S21 BW (GHz)	11	21.8–30	26–39.8	26–32	25.8-36.9
$P_{sat}$ (dBm)	22.8	19.7/20.3/20/20	17.1	15.1	17.84/17.81
1 dB $P_{sat}$ BW (GHz)	7	N/A	12	N/A	10
$O{P}_{1dB}$ (dBm)	22.6	18.2/18.2/17.8/17.2	16.1	13.7	14.09/14.04
1 dB $O{P}_{1dB}$ BW (GHz)	N/A	N/A	13	7	10
$PA{E}_{max}$ (%)	27	34.5/33.1/30/30.3	25.3	33.7	24.37%
VDD (V)	3.3	2.2	N/A	1.1	1.1
Area (${\mathrm{mm}}^2$)	0.48	0.189	0.162	0.225	1.326

summarizes the performance of the designed wideband power amplifier and compares it with other state-of-the-art PAs in the Ka-band. Our power amplifier demonstrates the highest gain compared with the previous work in Table 1 despite the use of staggering. Both the small- and large-signal bandwidths are competitive among the references in Table 1 besides the FD-SOI power amplifier in reference [29]. With a 1.1 V VDD supply and the power combining method, the $P_{sat}$ and $O{P}_{1dB}$ of our power amplifier are impressive besides the work with a 3.3 V/2.2 V supply in references [23,38], respectively. Figure 27 and Figure 28 present the S-parameters and large-signal performance at the ff corner and ss corner, respectively. At both the ff corner and ss corner, the DC bias current of all the stages is adjusted by changing the gate bias voltage to make it nearly the same as that at the tt corner. At the ff corner, the 3 dB small-signal bandwidth is 12.13 GHz, with a peak gain of 23.9 dB, as shown in Figure 27a. It achieves a flat $P_{sat}$ of 16.91–17.74 dBm, a flat $O{P}_{1dB}$ of 13.51–14.17 dBm, and a $PA{E}_{max}$ of 20.57–23.76%, between 26 GHz and 36 GHz, at the ff corner. At the ss corner, the 3 dB small-signal bandwidth is 10.29 GHz, with a peak gain of 27.57 dB, as shown in Figure 28a. In Figure 28b, the power amplifier achieves a flat $P_{sat}$ of 17.08–17.87 dBm, a flat $O{P}_{1dB}$ of 13.22–13.88 dBm, and a $PA{E}_{max}$ of 20.72–24.7%, between 26 GHz and 36 GHz. These results indicate that the broadband characteristics of the designed power amplifier are relatively stable.

5. Conclusions

This article presents a wideband power amplifier in 65nm CMOS covering the bandwidth from 25.8 GHz to 36.9 GHz. A symmetrical output MCR is designed to achieve wideband optimum load impedance for the power amplifier. To flatten the small-signal bandwidth of the power amplifier, staggered interstage and input MCRs are custom-designed. A high-pass form MCR2 and an asymmetrical MCR1 satisfying ${\mathsf{\omega }}_1/{\mathsf{\omega }}_2$ = $Q_1/Q_2$ are used to successfully compensate and stagger the Z21 shape of MCR3 and MCR4. To increase the output power, the two-way current combining method is used via a microstrip transmission line power combiner and splitter. Three common-source stages with neutralization capacitors are used to improve power gain and stability and to stagger the Z21 of each MCR conveniently. Benefiting from the above-mentioned design considerations, the power amplifier achieves both wideband small- and large-signal performance. A peak small-signal gain of 25.87 dB with 3 dB bandwidth from 25.8 GHz to 36.9 GHz is achieved. From 26 GH to 36 GHz, a $P_{sat}$ of 17.44 ± 0.4 dBm with a 22.59 ± 1.78% $PA{E}_{max}$ and an $O{P}_{1dB}$ of 13.78 ± 0.31 dBm under the 1.1 V supply voltage are realized. These results indicate that this power amplifier is competitive on the applications of wideband millimeter-wave communication.