Thirteen-Level Switching Capacitor Inverter with Six Times Boost and Self-Balancing Capability

Abstract

A thirteen-level inverter based on switching capacitor is proposed in order to improve the boost capacity and output power quality of inverter in renewable energy power generation system. The proposed topology is composed of one DC input power supply, three capacitors and 14 switching devices, and achieves thirteen-level output with six times voltage boost. It has smaller volume, lower cost and output harmonic content. Moreover, it can realize inverter without H bridge and reduce the voltage stress of switching tube. In addition, the proposed inverter can achieve self-balancing capacitor voltage without any auxiliary method, simplifying the complexity of control. The superiority of the proposed topology is verified by comparing with other traditional multilevel inverters. The simulation and experimental verification on the simulation and prototype platform show that the inverter has good performance in both steady and dynamic conditions.

1. Introduction

Nowadays, multi-level inverters (MLI) play an important role in modern power systems and have many advantages, such as avoiding high-voltage stress under high switching frequency operation and producing output voltage with low total harmonic distortion [1,2,3,4]. Therefore, the research and application of multilevel inverters are continuing [5,6,7,8].

In recent years, the dominant multilevel inverters include neutral clamped (NC), flying capacitor (FC) and cascaded H-bridge (CHB) [9,10]. Among them, the NC circuit and FC circuit are limited by capacitor voltage imbalance and the number of switching devices. In contrast, the CHB circuit has a simple structure, but multiple independent DC power supplies are required for cascading [11]. In addition, most traditional multilevel inverters need to add an additional boost circuit at low-voltage input, which increases the volume of the inverter and reduces the economy. In order to alleviate the above problems, researchers proposed a switched capacitor multilevel inverter (SC-MLI) [12,13,14]. SC-MLI not only has the characteristics of self-balancing, but also can achieve more level output with fewer devices and it also has the ability to boost independently [15]. Therefore, domestic and foreign researchers continue to innovate and improve it [16,17,18].

The topology proposed in Reference [19] can achieve the effect of increasing the voltage gain and the number of output levels, but the number of devices used is large, and the terminal H-bridge needs to withstand large voltage stress and cannot be applied in high-voltage output occasions. In order to reduce the number of devices, Reference [20] proposed a nine-level SC-MLI, greatly reducing the number of switching devices, but its topology is not conducive to the expansion of the inverter bridge, the output level is limited. References [21,22,23,24] proposed an extensible SC-MLI, which achieves more levels and higher gain output by cascading multiple modules with capacitors in the topology. However, the number of output levels of the inverter in Reference [21] is linked to the number of DC power supplies, which limits the number of output levels. The inverter proposed in [22] not only needs multiple DC power supplies, but also needs to set the voltage ratio between multiple power supplies. The MLI in Reference [23] requires a large number of devices and a relatively complex structure, so the volume and cost of the system are relatively high. The topology proposed in [24] only requires a single DC source, which is simple in structure and easy to expand. However, when there are too many expansion modules, the number of levels does not increase any more, and the economy is low.

In order to solve the above problems, this paper proposes a thirteen-level SC-MLI with expansion capability. The capacitor is periodically charged and discharged so that the voltage inside the capacitor can be self-balanced. Through the series-parallel combination of the dual-capacitor basic module of the front stage and the expansion module of the rear stage, the post-stage capacitor is charged and discharged at the same time as the post-stage capacitor to supply energy to the load. The inverter can achieve more level output with fewer devices, and has the ability of independent boost, which greatly reduces the cost of the system and greatly expands the application range.

2. Proposed Topology

2.1. Description of the Proposed MLI

The main circuit topology of the proposed thirteen-level inverter is shown in Figure 1, including double capacitance base module, extended module and half-bridge module.

In the proposed topology, the output voltage is superimposed by a power supply and a capacitor. In the dual-capacitor basic module, the DC power supply V_dc charges the capacitors C₁ and C₂; the switch tubes S₂ and S₄ are jointly switched on and off, and are complementary to S₃ to change the series and parallel connection of capacitors C₁ and C₂. The switch tube S₁ and S₅ are complementary conduction, switching the series and parallel connection between DC power supply V_dc and capacitor C₁ and C₂. During the charging and discharging process, the states of C₁ and C₂ capacitors are completely consistent, thus solving the problem of capacitor voltage balance. In addition, the dual capacitor module and the capacitor C₃ are connected by an expansion module composed of five switches S₆~S₁₀; finally, the half-bridge structure composed of two sets of switch tubes replaces the H-bridge to change the polarity of its output.

The inverter uses a DC input power supply, three capacitors and fourteen switching devices (such as MOSFETE) to achieve a step wave output of up to thirteen levels, with six times the voltage gain. The maximum blocking voltage (MBV) of all switches in the dual-capacitor module is equal to V_dc. The maximum blocking voltage of the expansion module and the switches in the two half-bridges is 3V_dc, so the total standing voltage (TSV) of the fourteen switches is 32V_dc.

2.2. Steady-State Switching Analysis of the Proposed MLI

Figure 2 shows the inverter in the positive half cycle different output level working state, black solid line for the circuit discharge circuit.

In order to simplify the analysis, the on-resistance of the switch tube and the voltage drop of the capacitor voltage in the circuit are ignored. The working principle of the inverter in the positive half cycle is analyzed as follows.

(1)

Working mode 1 (V_o = 0), as shown in Figure 2a. In the dual-capacitor module, the switch tubes S₂, S₄ and S₅ are turned on, the capacitors C₁ and C₂ are connected in parallel, and the DC power supply is connected in parallel with the capacitors C₁ and C₂ and charged to V_dc. In the expansion module, the switches S₆ and S₉ are turned on, and the dual-capacitor module discharges separately. In the half-bridge circuit structure, the switch tubes S₁₁ and S₁₃ are conductive. Similarly, the case of obtaining zero level in the negative half cycle is shown in Figure 2b.

(2)

Working mode 2 (V_o = +V_dc), as shown in Figure 2c. The state of each element in the dual capacitor module is the same as in Mode 1. In the expansion module, the switches S₇ and S₁₀ are turned on, and the dual-capacitor module discharges separately. In the half-bridge circuit structure, the switch tubes S₁₂ and S₁₄ are conductive.

(3)

Working mode 3 (V_o = +2V_dc), as shown in Figure 2d. In the dual-capacitor module, the capacitor C₁ and C₂ are connected in parallel and connected in series with the DC power supply to provide energy to the load. The switches S₇ and S₁₀ in the expansion module are conductive, and the double capacitor module discharges separately. In the half-bridge circuit structure, the switch tubes S₁₂ and S₁₃ are conductive.

(4)

Working mode 4 (V_o = +3V_dc), as shown in Figure 2e. In the double capacitor module, the switch tubes S1 and S3 are turned on, and the capacitor C₁ and C₂ are connected in series to provide energy to the load together with the DC power supply. The four switches S₆, S₇, S₉ and S₁₀ in the expansion module are switched on together, and the dual capacitor module charges the capacitor C₃ to 3V_dc. In the half-bridge circuit structure, the switch tubes S₁₁ and S₁₄ are conductive.

(5)

Operating Mode 5 (V_o = +4V_dc), as shown in Figure 2f. In the dual-capacitor module, the switch tubes S₂, S₄ and S₅ are turned on together. At this time, the capacitors C₁ and C₂ are connected in parallel, and then charged in parallel with the DC power supply to V_dc. The switches S₇, S₈ and S₉ in the expansion module are turned on, and the dual-capacitor module discharges in series with the capacitor C₃. In the half-bridge circuit structure, the switch tubes S₁₁ and S₁₄ are conductive.

(6)

Working mode 6 (V_o = +5V_dc), as shown in Figure 2g. In the dual-capacitor module, the switch tubes S₁, S₂ and S₄ are turned on. After the capacitors C₁ and C₂ are connected in parallel, they are connected in series with the DC power supply to provide energy to the load. In the expansion module, the switch tubes S₇, S₈ and S₉ are switched on, and the double capacitor module discharges in series with the capacitor C₃. In the half-bridge circuit structure, the switch tubes S₁₁ and S₁₄ are conductive.

(7)

Working mode 7 (V_o = +6V_dc), as shown in Figure 2h. In the double capacitor module, the switch tubes S₁ and S₃ are connected, the capacitors C₁ and C₂ are connected in series, and the DC power supply is connected in series to provide energy to the load, and the diode D is cut off in reverse. In the expansion module, the switch tubes S₇, S₈ and S₉ are turned on together, and the double capacitor module is discharged in series with the capacitor C₃. In the half-bridge circuit structure, the switch tubes S₁₁ and S₁₄ are conductive. The working principle of the inverter working in the negative half cycle is consistent with that in the positive half cycle.

Table 1. Charging and discharging state of capacitor in different switching modes (▲: Charge ▼: Discharge —: Lie Idle).

Output Voltage	On-Off Switch Tube	C1	C2	C3
6Vdc	S1, S3, S7, S8, S9, S11, S14	▼	▼	▼
5Vdc	S1, S2, S4, S7, S8, S9, S11, S14	▼	▼	▼
4Vdc	S2, S4, S5, S7, S8, S9, S11, S14	▲	▲	▼
3Vdc	S1, S3, S6, S7, S9, S10, S11, S14	▼	▼	▲
2Vdc	S1, S2, S4, S7, S10, S11, S14	▼	▼	—
Vdc	S2, S4, S5, S7, S10, S11, S14	▲	▲	—
0+	S2, S4, S5, S6, S9, S11, S13	▲	▲	—
0−	S2, S4, S5, S7, S10, S12, S14	▲	▲	—
−Vdc	S, S4, S5, S6, S9, S12, S13	▲	▲	—
−2Vdc	S1, S2, S4, S6, S9, S12, S13	▼	▼	—
−3Vdc	S1, S3, S6, S7, S9, S10, S12, S13	▼	▼	▲
−4Vdc	S2, S4, S5, S6, S8, S10, S12, S13	▲	▲	▼
−5Vdc	S1, S2, S4, S6, S8, S10, S12, S13	▼	▼	▼
−6Vdc	S1, S3, S6, S8, S10, S12, S13	▼	▼	▼

shows the charging, discharging and idle state of the capacitor under different switching modes.

2.3. Proposed N-Level Topology

In order to increase the number of output levels of the proposed topology and improve the gain of its output voltage, multiple expansion modules are added to expand the circuit on the basis of the original inverter, as shown in Figure 3. In the dotted box is the expandable capacitor module. After adding the expandable module, the working principle of the inverter is similar to the structure of the only expandable module.

For each single capacitor module added to the extended structure, the voltage gain of the inverter circuit will increase by 3V_dc and the number of levels will increase by six. So, when the module is m, the inverter circuit voltage gain will increase 3mV_dc, the output level is:

$$N=6m+7$$

(1)

In the expansion module, the capacitors in the adjacent modules can discharge in parallel, so the voltage ripple of the capacitor is further improved.

3. Modulation and Characteristic Strategy

3.1. Modulation Strategy

According to the analysis of the working principle of the thirteen-level inverter mentioned above, this paper adopts the carrier phase stacking control method with better harmonic elimination effect, and its principle is shown in Figure 4.

In Figure 4, twelve groups of triangular carriers with an amplitude of A_c and a frequency of f_c are compared sine waves with amplitude A and frequency f, as shown in Figure 4a. The original PWM pulses of u₁~u₁₂ are obtained, as shown in Figure 4b. Modulation ratio M is:

$$M=\frac{A_c}{6A}$$

(2)

This paper sets the modulation ratio to 0.9. Twelve original pulses are combined into a control signal of fourteen switching tubes according to a specific logical relationship, as shown in Figure 4c. In one cycle, the logical relationship between each switch and the twelve original pulses is:

$$S_1=u_2+{\overline{u}}_3{u}_4+{\overline{u}}_4{u}_5+{\overline{u}}_8{u}_9+{\overline{u}}_9{u}_{10}+{\overline{u}}_{11}$$

(3)

$$S_2=u_1{\overline{u}}_2+{\overline{u}}_2{u}_3+{\overline{u}}_4{u}_9+{\overline{u}}_{10}{u}_{11}+{\overline{u}}_{11}{u}_{12}$$

(4)

$$S_3={\overline{S}}_2$$

(5)

$$S_4=S_2$$

(6)

$$S_5={\overline{u}}_2{u}_3+{\overline{u}}_5{u}_8+{\overline{u}}_{10}{u}_{11}$$

(7)

$$S_6={\overline{u}}_3{u}_4+{\overline{u}}_6$$

(8)

$$S_7=u_6+{\overline{u}}_9{u}_{10}$$

(9)

$$S_8=u_3+{\overline{u}}_{10}$$

(10)

$$S_9=u_4+{\overline{u}}_6{u}_{10}$$

(11)

$$S_{10}={\overline{u}}_3{u}_6+{\overline{u}}_9$$

(12)

$$S_{11}={\overline{u}}_6$$

(13)

$$S_{12}=u_6$$

(14)

$$S_{13}=u_7$$

(15)

$$S_{14}={\overline{u}}_7$$

(16)

Figure 4e shows the logic circuit of grid pulse generated by carrier in-phase cascade control method. After the logical combination of the original pulses generated by the comparison between the sine wave and the twelve groups of carriers, fourteen groups of pulses are generated to drive the opening and closing of each switching tube of the inverter.

3.2. Analysis of Capacitor Balancing

Capacitance voltage self-balance is a prerequisite for normal operation of SC-MLI. If the capacitor voltage cannot achieve self-balancing, it will cause the voltage offset to fail to achieve the expected experimental results, and even damage the device.

According to Table 1, capacitors C₁ and C₂ operate in the same state, thus satisfying the condition that their capacitor voltages can be self-balanced. When the output voltage is 0, ±V_dc and ±4V_dc, the DC power supply charges the capacitors C₁ and C₂; when the output voltage becomes ±2V_dc and ±5V_dc, capacitors C₁ and C₂ discharge together in parallel; when the output voltage is ±3V_dc and ±6V_dc, the capacitor C₁ and C₂ discharge together in series. Therefore, capacitors C₁ and C₂ are always in a running state. Capacitor C₃ charges and discharges alone, so there is no need to consider its capacitor voltage self-balancing. When the output voltage is 0, ±V_dc and ±2V_dc, the capacitor C₃ is in an idle state; when the output voltage is ±3V_dc, C₃ is charged in parallel with the capacitor basic module; when the output voltage is ±4V_dc, ±5V_dc and ±6V_dc, C₃ discharges in series with the capacitor base module.

3.3. Analysis of the Capacitors

The output voltage of MLI is essentially a combination of power supply voltage and capacitor voltage in series and parallel, so the ripple of capacitor voltage plays a vital role in the quality of output power. Usually, the ripple is expressed as the amount of continuous discharge of the capacitor:

$$\Delta Q_c={\displaystyle {\int }_{t_a}^{t_b}{I}_o\sin (2\pi ft-\phi )\mathrm{dt}}$$

(17)

where, △Q_c is the change value of the capacitance charge in the time period t_a~t_b, I_o is the amplitude of the circuit output current, f is the load frequency and φ is the phase difference between the output voltage of the inverter with inductive load and the load current.

The capacitance voltage ripple △U_c is calculated from the capacitance discharge:

$$\Delta U_c=\frac{\Delta Q_c}{C}$$

(18)

Under normal circumstances, the constraint voltage ripple is less than 10% of the rated voltage of the capacitor to avoid the adverse effects of the voltage ripple on the inverter. The conditions that the capacitor and the rated voltage U_c should meet are:

$$U_{c}C\ge 10\Delta Q_c$$

(19)

The amplitude of the carrier wave obtained from Equation (2) is:

$$A_c=\frac{A}{6M}$$

(20)

As shown in Figure 4a, the instantaneous value of the output voltage of the inverter, the time period from 0 to V_dc is 0~t₁, then:

$$t_1=\frac{\arcsin \frac{1}{6M}}{2\pi f}$$

(21)

Similarly, when n = 1, 2, …, 6.

$$t_n=\frac{\arcsin \frac{n}{6M}}{2\pi f}$$

(22)

It can be seen from Table 1 and Figure 4 that when the continuous discharge of capacitors C₁ and C₂ is in the t₂~t₃ and t₅~t₆ time periods, the discharge amounts can be obtained as follows:

$$\Delta Q_c={\displaystyle {\int }_{t_2}^{t_3}{I}_o\sin (2\pi f-\phi )}\mathrm{dt}$$

(23)

$$\Delta Q_c^{\prime }={\displaystyle {\int }_{t_5}^{t_6}{I}_o\sin (2\pi f-\phi )}\mathrm{dt}$$

(24)

During a power frequency cycle, the amount of discharge from the capacitor C₁ and the capacitor C₂ is equal. Capacitor C₃ in the t₄~t₆ period of continuous discharge, discharge capacity:

$$\Delta Q_c^{\prime }={\displaystyle {\int }_{t_4}^{t_6}{I}_o\sin (2\pi f-\phi )}\mathrm{dt}$$

(25)

According to the expressions (18)–(20), the variation of the charge of the capacitors C₁ and C₂ is less than that of C₃ within half a cycle, so the voltage ripple of the two capacitors is less than that of C₃.

3.4. Power Loss Calculation

The main losses of SC-MLI are capacitor ripple loss (P_rip), conduction loss (P_com) and switching loss (P_sw). P_rip is caused by the voltage fluctuation of the capacitor. According to Formula (18):

$$P_{\mathrm{rip}}=f_o\frac{\Delta Q_c^2}{C}$$

(26)

The conduction loss of the inverter is caused by the parasitic parameters of the device, such as the on-resistance (r_s) of the switch and the equivalent series resistance (ESR) of the capacitor. The equivalent parameters of the six working modes are shown in

Table 2. Equivalent Parameters in Six Working Modes.

j	Uo	req
0	0	$4r_s$
1	Vdc	$ESR+6r_s$
2	2Vdc	$ESR+6r_s$
3	3Vdc	$2ESR+6r_s$
4	4Vdc	$2ESR+7r_s$
5	5Vdc	$2ESR+7r_s$
6	6Vdc	$3ESR+7r_s$

. The value of j in the table indicates that the output V_o is j times the V_dc.

According to Figure 4, in the interval [0, t₁], the power loss of the output level between 0 and V_dc can be calculated by the following formula:

$$P_0{}_{\&V_{\mathrm{dc}}}={{\displaystyle {\int }_0^{t_1}\left[I_o\sin \left(2\pi f_{o}t\right)\right]}}^2\times \left[\left(ER{S}_c+6r_s\right)\frac{A\sin \left(2\pi f_{o}t\right)}{A_c}\right]+4r_s\left(1-\frac{A\sin \left(2\pi f_{o}t\right)}{A_c}\right)\mathrm{dt}$$

(27)

Similarly, the power loss of the other five operating modes can also be obtained in the same way. Thus, P_com can be obtained by:

$$P_{\mathrm{con}}=4(P_{0\&V_{\mathrm{dc}}}+P_{V_{\mathrm{dc}}\&2V_{\mathrm{dc}}}+P_{2V_{\mathrm{dc}}\&3V_{\mathrm{dc}}}+P_{3V_{\mathrm{dc}}\&4V_{\mathrm{dc}}}+P_{4V_{\mathrm{dc}}\&5V_{\mathrm{dc}}}+P_{5V_{\mathrm{dc}}\&6V_{\mathrm{dc}}})$$

(28)

Based on the charge and discharge process of the parasitic capacitor in the switching tube, assuming that the capacitance of the parasitic capacitor is linear, the voltage is gradually charged to vs. when the switch is turned off, where vs. is the MBV of the switch. Therefore, P_sw is:

$$P_{\mathrm{sw}}=C_s{V}_s^2{f}_s$$

(29)

where, f_s is the switching frequency of the switch, and is:

$$f_s=N_s{f}_o$$

(30)

where, N_s is the switch transition in one cycle of the reference waveform. As you can see from Figure 4, the switch is repeatedly switched on and off at corresponding intervals. If the switch operates throughout the cycle, the N_s of each switch can be roughly calculated as the ratio of fs to f_o. Therefore, N_s of each switch is:

$$N_s=\frac{t_s{f}_c}{T_s{f}_o}$$

(31)

where: t_s is the working time of the switch; T_s is the time of a cycle.

Therefore, the efficiency of the inverter proposed is:

$$\eta =\frac{P_o}{P_o+P_{\mathrm{rip}}+P_{\mathrm{com}}+P_{\mathrm{sw}}}$$

(32)

where, η and P_o are respectively the efficiency and output power of the proposed inverter.

4. Comparison Outcomes

In order to highlight the overall advantages of the thirteen-level inverter, the proposed topology is compared with the existing typical topology. The topology of the contrast does not increase the expansion structure to ensure that the contrast is more distinct. The detailed comparison parameters are shown in

Table 3. Comparison of Seven Thirteen-Level Switched Capacitor.

Topology	NCapacitor	NSwitch	NSource	MBV	TSV
[25]	4	14	2	6	32
[26]	5	19	1	5	48
[27]	5	34	1	1	34
[28]	0	8	3	3	24
[29]	4	18	2	3	32
[30]	4	16	2	3	35
Proposed	3	14	1	3	32

, including the number of capacitors, switches, DC power supplies, MBV and TSV of each inverter.

It can be seen from Table 2 that although the number of switching tubes and TSV used in Reference [25] are comparable to those in this paper, its MBV is relatively high and two power supplies are used. Reference [26] reduced the number of power supplies and MBV, but the number of capacitors and switches is too large, TSV is too large. Reference [27] the MBV of the switch tube is less than this article, but the corresponding number of devices also increased, especially the use of five capacitors, which will increase the volume and cost of the inverter. In reference [28], the number of switching devices and the total voltage stress are relatively lower without using capacitors, but the number of power supplies increases linearly with the output voltage level. The MBV and TSV in References [29,30] are comparable to those in this paper, but the number of capacitors, switches and power supplies are slightly higher than those in this paper.

In summary, the topology proposed in this paper has obvious advantages in comprehensive performance, and also has the ability to expand, so it has good economy and practical application ability.

5. Simulation Verification and Experimental Verification

5.1. Simulation Verification

In order to verify the correctness of the thirteen-level switching capacitor inverter and the theory in this paper, the topology simulation circuit model is built on the Matlab/Simulink platform. The steady-state output voltage and current output waveform are shown in Figure 5.

The values of capacitors C₁~C₂ and C₃ are 2200 uF and 4700 uF, V_in is 10 V, and pure resistance load R is 100 Ω. As can be seen in the figure, the output voltage is 60 V, and a level thirteen-step wave with six times gain is achieved.

For further analysis, the performance of the proposed topology under group load is analyzed. When the load is R = 100 Ω, L = 40 mH resistive load, the voltage and current output waveform is shown in Figure 6.

As can be seen from the figure, the output voltage is a standard thirteen-level step wave. According to the filter effect of inductance, the load current waveform is similar to sinusoidal waveform, and the load current lags behind the output voltage waveform, which proves the capability of the topology to carry inductive load. The FFT analysis of the output voltage of the proposed topology is shown in Figure 7, which is 11.71%, which can be further reduced by increasing the number of levels in the output voltage.

5.2. Experimental Validation

In order to further verify the correctness of the topology and its performance under steady-state and dynamic conditions, an experimental prototype was built, as shown in Figure 8.

To further verify the correctness of the topology, an experimental prototype is built. The main circuit is driven by the control signal generated by the K60 series microcontroller to control the turn-on and turn-off of each switch tube, so as to realize the output of the thirteen-level. The parameters are shown in

Table 4. Component Parameters of Experimental Prototype.

Components	Specifications (Parameters)
Controller	MK60FX512
Switching Tube	IRF3205
Diode	FR104, 1N5819
Capacitance	2200 uF, 4700 uF
Resistance	100 Ω
Inductance	40 mH
Switching frequency	2 kHz
Output frequency	50 Hz

.

According to the modulation method in Figure 4, the K60 single chip microcomputer drives the on–off of fourteen switching tubes in the main circuit with the generated logic signal, and obtains the driving signal waveform of each switching tube of the inverter, as shown in Figure 9. It can be seen from the figure that the switching frequency of each switch tube is consistent with the theoretical analysis and simulation of the modulation strategy, which verifies the correctness of the conduction sequence of the switch tube.

The voltage of the fourteen switch tubes S₁–S₁₄ is shown in Figure 10. It can be seen that the MBV of S₁–S₄ in the dual-capacitor base module is 20 V, 16 V, 18 V and 16 V, respectively. The MBV of S₅–S₉ in the expansion module is 20 V, 52 V, 52 V and 44 V, respectively. In the half-bridge module, the S₁₁, S₁₂ and S₁₃, S₁₄ are 40 V and 44 V, respectively.

The current of fourteen switching tubes S₁–S₁₄ is shown in Figure 11. It can be seen that the maximum current of all switching tubes is within 5 A.

When the DC input voltage is 20 V, the output voltage and current waveform of the system with a pure resistive load are shown in Figure 12. As can be seen from the figure, the load current waveform is a stepped wave, consistent with the output voltage waveform. The peak output voltage is 120 V, which achieves a voltage gain of six times. Moreover, after stabilization, the standard thirteen-level step wave can be output, which further verifies the feasibility of the topology.

When the system power supply voltage V_in changes from 10 V to 20 V, the waveform diagram is shown in Figure 13. It can be seen that the inverter can react quickly and stabilize in the new state.

Under the group inductive load R = 100 Ω and L = 40 mH, the reactive power capacity of the proposed SC-MLI was evaluated with an inductive resistance load of 161 VA according to IEEE standard 1547 [31]. The power factor (PF) was 0.89, and the topological output voltage and current were shown in Figure 14. As can be seen in the figure, the output voltage is a standard thirteen-level step wave, and the load current waveform is a smooth sine wave, which lags behind the output voltage waveform, proving the capability of the topology to provide reactive power.

When the load changes from no-load to group load with R = 100 Ω and L = 40 mH, the experimental output waveform is shown in Figure 15.

It can be seen that the output voltage remains unchanged, and the load current changes with the load, indicating that the output voltage can remain stable when the load changes, and it has a good ability to adapt to load mutations. When the power supply voltage Vin changes from 10 V to 20 V, the waveform diagram is shown in Figure 16.

Under different output power, the efficiency of the proposed topology is shown in Figure 17. When the output power changes from 100 W to 500 W, the efficiency is always above 93%, and the highest is 95.7%. When the output power is less than 300 W, the efficiency is higher than 95%. When the input voltage of the inverter is 20 V and the output power is 200 W, the efficiency is 95.3%, higher than 94% and 92.3% in reference [27,29].

6. Conclusions

In this paper, an extensible thirteen-level SC-MLI is proposed to achieve higher output step wave and voltage gain with fewer devices. It has the advantages of fewer devices and automatic capacitor voltage balance, and can expand the topology by adding expansion modules as required. Compared with the existing topology, the proposed inverter has certain advantages in the number of components, MBV and TSV. Finally, an experimental prototype is used to verify the inverter. According to the experimental results, the proposed topology can output thirteen-level stepped waves stably, with self-balancing capacitor voltage and six-times voltage gain effect. Additionally, it can still work normally when the load changes, with excellent dynamic stability to meet the needs of inverter applications, at the same time, it has a high power conversion efficiency, the maximum value is more than 95%.