New Heuristic Algorithm for Low Energy Mapping for 2.5-D Integration

Abstract

A chiplet placement algorithm for 2.5-D IC integration on an interposer is discussed in this paper. Inspired by the NoC (network-on-chip) mapping problem, we propose a novel chiplet placement algorithm called the CCEOA (chiplet communication energy optimization algorithm), which takes into account the actual size of the chiplet. The CCEOA can map chiplets to mesh topology, resulting in a layout with a low CEC (communication energy consumption). The algorithm considers the spacing of the chiplets while selecting the initial nodes and the nodes to map the next chiplet. Furthermore, because there exist nodes resulting in the same CEC increment during the mapping process, the algorithm adopts a secondary local exploration strategy to further select nodes. Meanwhile, the lateral and vertical placements of chiplets are also considered. The algorithm is implemented and evaluated with a 2.5-D IC integration with 22 chiplets to demonstrate its efficiency and the accuracy.

1. Introduction

Traditional monolithic 2D integrated chip (IC) designs are increasingly having difficulty following Moore’s law, as semiconductor technology advances and the design complexity of system-on-chip (SoC) increases [1]. Printed circuit boards (PCBs) have traditionally been utilized as integration platforms. PCBs are mature and cost-effective, but their lengthy and wide traces cause a high inductance and capacitance, restricted bandwidth and substantial power losses [2,3]. As a result, interposer-based 2.5-D IC integration has received a lot of interest as a way to overcome the constraints of 2-D IC integrations [4,5]. Based on an interposer, 2.5-D IC integration separates a single SoC into numerous functional blocks known as chiplets, which are placed side-by-side on the interposer and coupled with high speed and bandwidth through the interposer. This approach significantly reduces the design cycle, complexity and cost. It enables the heterogeneity of blocks in multiple technologies and permits the reuse of off-the-shelf intellectual properties (IPs) [6,7]. Instead of redesigning the entire system, SoC designers can replace only the necessary chiplets. Because the known good dies (KGDs) are picked as chiplets, the development risk of SoC in 2.5-D integration is reduced much more than that of a traditional 2-D IC design [8]. Furthermore, Intel’s FOVEROS technology and AMD’s Zen 2 microarchitecture show that 2.5-D IC technology is no longer an option but rather a new trend in the system-on-chip (SoC) design.

The speed of the semiconductor development is increasing as a result of fifth-generation (5G technology standard for broadband cellular networks) and artificial intelligence (AI) [9]. While 2.5-D IC integration provides a higher level of integration, the smaller physical size and spacing of the interconnects lead to increased coupling effects and interference between the interconnects, which pose a challenge to chiplet communication issues. A reasonable layout would improve the chiplet communication.

The advancement of chip technology has resulted in ongoing advancements in packaging technologies. Kim et al. presented an effective methodology for the co-design, co-analysis and the system-level optimization of the chiplet/interposer power network (PDN) in 2.5-D IC integration [10]. Kabir et al. proposed a chip-package co-design flow for 2.5-D IC integration. Their flow included 2.5-D-aware partitioning suitable for SoC design, chip-package floor planning, post-design analysis and the verification of the entire 2.5-D IC integration [11]. Park et al. presented a complete EDA flow and design strategies targeting active interposer-based 2.5-D IC integration. They concentrated on the co-analysis of power, performance, signal and power integrity, the related co-optimization of chiplets and the active interposer [12].

Various chiplet placements result in different CECs. It is crucial to figure out how the chiplets should be arranged. Various heuristic techniques have been used to handle similar problems in NoC. Murali, S. et al. presented NMAP, which was a fast algorithm that mapped the cores onto a mesh NoC architecture under bandwidth constraints, thus, minimizing the average communication delay [13]. Wang et al. proposed a new effective optimization method based on the discrete particle swarm optimization framework, including the novel principles for representation, velocity computing and position-updating of the particles [14]. Liu et al. proposed a multi-objective ant colony algorithm (MOACA) that mapped IP cores onto mesh-based NoC architectures, which showed to be an efficient way of finding the pareto-optimal front-optimizing energy consumption and hotspot temperature of an NoC [15].

In this article, we propose a heuristic algorithm, the CCEOA (chiplet communication energy optimization algorithm), based on the 2D NoC mapping algorithm SYMMAP (symmetry mapping) [16] to discover a feasible layout of 2.5-D IC integration for a low CEC, considering the peculiarities (actual size, chiplet space, etc.) of 2.5-D IC integration.

2. Model Establishment

Mesh topology is used in mapping. Standard NoC mapping only considers that one IP core occupies one node in topology, but this is not the case in 2.5-D IC integration. Because the chiplets are different sizes, we should take the area factor into account. At the same time, the distance between the chiplets would be different if the chiplets were placed horizontally or vertically. To solve these problems, we needed the following novel models.

2.1. The 2.5-D IC Integration Mapping Model

In this study, a 2.5-D IC integration with 22 chiplets was used as an example. The model consisted of an FPGA, Memory, AD, DA, etc.

In this algorithm, mesh topology was used. In order to take into account the area factor, it could be assumed that a chiplet mapping with a certain area would occupy multiple nodes in the topology. Meanwhile, there should be a certain spacing between the chiplets, which also needed to be considered. In Figure 1, chiplet numbers are used to represent the chiplets. The chiplet sizes in the algorithm were regarded as the theoretical value based on the actual size containing the spacing, which was slightly larger than the actual size. The theoretical sizes of all chiplets and their numbers are shown in

Table 1. The actual sizes and the theoretical sizes of chiplets.

Number	Chiplet Name	Actual Size (mm2)	Theoretical Size (mm2)
0	Memory	6.9 × 6.8	9 × 9
1	AD	4.7 × 4.6	6 × 6
2	D51	2.3 × 2.3	3 × 3
3	D52	2.3 × 2.3	3 × 3
4	FPGA	10.6 × 10.0	12 × 12
5	D10	4.8 × 1.7	6 × 3
6	D11	4.8 × 1.7	6 × 3
7	D19	4.8 × 1.7	6 × 3
8	D18	4.8 × 1.7	6 × 3
9	DA	4.9 × 4.9	6 × 6
10	D8	1.9 × 1.7	3 × 3
11	D9	1.9 × 1.7	3 × 3
12	D12	1.9 × 1.7	3 × 3
13	D13	1.9 × 1.7	3 × 3
14	D16	1.9 × 1.7	3 × 3
15	D17	1.9 × 1.7	3 × 3
16	D20	1.9 × 1.7	3 × 3
17	D21	1.9 × 1.7	3 × 3
18	D27	1.9 × 1.7	3 × 3
19	D26	1.9 × 1.7	3 × 3
20	D25	1.9 × 1.7	3 × 3
21	D24	1.9 × 1.7	3 × 3

.

The chiplet communication volume is depicted as a directed graph in Figure 2. Each chiplet (number of chiplets) is represented by a vertex in the graph, and each directed edge represents the communication volume (Mbit/s) between two chiplets.

2.2. Communication Energy Consumption Model

Energy minimization is one of the most important aspects of IC design. In a 2D mesh NoC, the energy consumption of transferring 1 bit of data between node i and j could be described as [17]:

$$E_{bit}^{i,j}=d_{i,j}\times E_{router}+(d_{i,j} - 1)\times E_{Lbit},$$

(1)

where $E_{i,j}^{bit}$ represents the energy consumption of transferring 1 bit of data from node i to node j. d_i,j is the Manhattan distance between node i and j. E_router and E_Lbit are the energy consumed in routers and links, respectively.

In 2.5-D IC integration, chiplets are directly connected through the interposer. Therefore, the energy consumption can be simplified as:

$$E_{bit}^{i,j}=d_{i,j}\times E_{Lbit},$$

(2)

where $E_{i,j}^{bit}$ is the energy consumption of transferring 1 bit of data from chiplet i to chiplet j. d_i,j is the Manhattan distance between chiplet i and chiplet j. E_Lbit is the energy consumed per unit distance.

The computing method of distances between chiplets also needed to be examined. In Figure 3, the distances between the chiplet midpoints (dotted line) were used to calculate the average distances. Mapped nodes were given the chiplet number of the corresponding region in the topology, while unmapped nodes were given the initial value “−1”. The node in the top left corner (dashed circle) was used to record the location of the chiplet.

The initial layout of the system is shown in Figure 4, and the CEC was 1209.56 μJ, which was calculated by Equation (2).

3. Mapping Algorithm Description

This mapping algorithm maps chiplets one after the other by selecting chiplets according to the CPL. Because of the symmetry of the topology, several nodes had the same mapping effect and the number of final schemes was equal to the number of asymmetric initial nodes.

In this algorithm, there were two key phases: Step 1, choose an initial chiplet and map it onto the initial nodes. Step 2, choose the next chiplet and filter the remaining nodes to map it. At the beginning, the function priority_generate generated a CPL. The first chiplet in the CPL, which always has the highest communication volumes with other chiplets, would be mapped first. Following the mapping of the first chiplet, the locations of initial nodes were determined by the function initialnode_generate. The first chiplet in the CPL would be mapped onto the initial nodes. After the first chiplet was mapped, the function next_chiplet selected which chiplet would be mapped next. The location of the next chiplet in the topology was decided by the function next_node for the minimal CEC increment. The CEC increment E_add could be calculated by Equation (3):

$$E_{add}={\displaystyle \sum _{i=0}^n{E}_{Lbit}\cdot d_{i,j}\cdot s_0\cdot s_1}$$

(3)

where E_Lbit is the energy consumed per unit distance. n denotes the number of mapped chiplets. Chiplet j is the chiplet that needs to be mapped, while chiplet i represents the chiplet that has already been mapped. d_i,j is the distance between chiplet j and chiplet i. If chiplet j communicated with chiplet i, s0 would be “1”. If chiplet i was mapped, s1 would be “1”. Aside from that, s0 and s1 would be “0”.

The next selected chiplets and nodes were checked continually by the function of next_chiplet and next_node, until all chiplets were mapped. In this algorithm, different initial nodes generated different mapping schemes, and the total CEC of each scheme was calculated. The mapping scheme with the minimal CEC would be the algorithm result. Algorithm 1 gives the pseudo-code of our algorithm.

The following sections went over the specifics of the above functions.

Algorithm 1 The pseudo-code of chiplet communication energy consumption optimal algorithm

Input: a chiplet size table.      a chiplet communication graph.      a topology graph.  Output: a mapping result mapbest with best energy consumption.

1. Obtain CPL by priority_generate(G); 2. Initial chiplet i = first chiplet in CPL; 3. Initial node set ITS = initialnode_generate(M); 4. Communication energy consumption CECmin = +∞; 5. For (k = 1; k ≤ |ITS|; k++) { 6.   Gmapped = ∅; Gummaped = G; Tunmapped = T; 7.   mapk(ci) = tk; Tunmapped = Tunmapped − {tk};//tk ∈ITS 8.   Gmapped = Gmapped +{ci}; Gunmapped = Gunmapped − {ci}; 9.   While (Gunmapped ≠ ∅) { 10.  Next selection chiplet cj = next_priority (Gunmapped,Gmapped); 11.  Next selection node tn = next_node (Tunmapped); 12.  mapk(cj) = tn; Tunmapped = Tunmapped − {tn}; 13.  Gmapped = Gmapped +{cj}; Gunmapped = Gunmapped − {cj};} 14.  CECk = calculate_cec (mapk ( )); 15.  If (CECk < CECmin) { 16.  CECmin = CECk; mapbest = mapk ( );}} 17. Return mapbest ( );

3.1. The Priority_Generate Function

The priority_generate function was used to generate the CPL, and the mapping order was based on the CPL. The chiplet that had the largest communication volume with other chiplets would be the first in the CPL. In addition, the chiplet that had the largest communication volume with the already mapped chiplets would be chosen as the next chiplet in the CPL. If chiplets had the same communication volumes with others, the mapping order would be considered to have no differences.

Table 2. CPL of the 2.5-D IC integration with 22 chiplets.

Priority	Number	Chiplet Name	Communication Volume (Mbit/s)
1	4	FPGA	900
2	0	Memory	625
3	1	AD/DA	325
4	2	D5_1	133
	3	D5_2	133
5	5	D10	80
	6	D11	80
	7	D19	80
	8	D18	80
6	9	D4	15
7	10	D8	10
	11	D9	10
	12	D12	10
	13	D13	10
	14	D16	10
	15	D17	10
	16	D20	10
	17	D21	10
	18	D27	10
	19	D26	10
	20	D25	10
	21	D24	10

shows the CPL for this example.

3.2. The Initialnode_Generate Function

The mapping schemes generated by the CCEOA correspond to initial nodes. Different initial nodes resulted in different layouts. The initialnode_generate function determined these initial nodes. In mesh topology, some nodes had the same mapping effect due to symmetry. Only the CECs of these asymmetric nodes needed to be considered during the algorithm search. Figure 5a shows an example of the initial layout, and Figure 5b shows the symmetrical layout with the same mapping effect.

The number of initial nodes was also related to the size of the initial chiplet. It could be obtained from Equation (4):

$$M=ceil(\frac{(N_1-L_0+1)}{2})\cdot ceil(\frac{(N_2-W_0+1)}{2})$$

(4)

where ceil is the upward rounding function; N₁ is the length of the topology; N₂ is the width of the topology; L₀ is the length of the first mapped chiplet; W₀ is the width of the first mapped chiplet; and M is the number of initial nodes.

3.3. The Next_Chiplet Function

The next_chiplet function determines the next chiplet once the initial chiplet is mapped. In this function, chiplets were searched by the Algorithm 2. “N” is the number of the chiplets. The chiplet that was not mapped would be marked “−2” in the chiplet-mapping flag matrix G(k). The communication between chiplets was recorded by the matrix cost(k1) (k2).

Algorithm 2 The next_chiplet function

Input: chiplet priority list, CPL. a chiplet mapping flag matrix, G(k). a chiplet communication matrix, cost(k1) (k2). Output: the next chiplet tk.

1. For (k1 = 0; k1 < N; k1++) { 2.  tcost = 0, tmax = 0; 3.  If (G[k1] != −2){ 4.   For (k2 = 0; k2 < N; k2++){ 5.   If (G[k2] == −2 && cost[k1] [k2] > 0) 6.    tcost = tcost + cost[k1] [k2];} 7.   If (tcost > tmax){ 8.    tmax = tcost; 9.    tk = k1;}}} 10. Return tk;

3.4. The Next_Node Function

The location of the next chiplet can be determined by the next_node function. During the mapping process, only unmapped regions larger than the size of the chiplets could map it. For example, the size of the initial chiplet (chiplet 4) was 4 × 4 (L × W), while the second chiplet (chiplet 0) was 3 × 3 (L × W). In Figure 6, if the nodes in a region of length L and width W are all “−1” and do not exceed the topology boundary, the node in the upper left corner of the area (dashed circle) can be used as a mapping node.

Usually, there may be multiple nodes making the CEC increment E_add equal. At this time, the secondary local exploration algorithm can be applied. Algorithm 3 gives the main part of the secondary local exploration algorithm.

Algorithm 3 Secondary local exploration algorithm

Input: the CEC of the chiplet to be mapped, tcost. a chiplet mapping flag matrix, G(k). a chiplet communication matrix, cost(k1) (k2). Output: The next chiplet tk.

1. tmin = 0, tmax = 0, tp = 0; 2. If (tcost < tmin) { 3.  tmin = tcost 4.  tp = k1;} 5. Else if (tcost = tmin){ 6.  For (k1 = 0; k1 < N; k1++) { 7.    tcost = 0; 8.   If (G[k1] != −2) { 9.     For (k2 = 0; k2 < N; k2++) { 10.    If (G[k2] == −2 && cost[k1] [k2] > 0) 11.      tcost = tcost + cost[k1] [k2]; } 12.    If (tcost > tmax || (tcost == tmax && 13.      DG[k3] > DG[tk2])) { 14.      tmax = tcost; 15.      tk2 = k1; 16.      tcost = 0;}}} 17. Return tk2;

As shown in Figure 7, assuming that the chiplet to be mapped is chiplet 0, the CECs for the cases in Figure 7a,b are the same. At this point, the mapping position of chiplet 0 would be determined by the next chiplet (chiplet 1). In Figure 7a, the unmapped nodes were filtered and mapped for chiplet 1 (dashed box), and the minimum CEC increment was ∆E₁. Similarly, in the case shown in Figure 7b, the unmapped nodes were filtered and mapped for chiplet 1 (dashed box) and the minimum CEC increment was ∆E₂. If ∆E₂ was greater than ∆E₁, Figure 7a would be chosen as the mapping scheme for chiplet 0. Conversely, if ∆E1 was greater than ∆E₂, Figure 7b would be selected as the mapping scheme for chiplet 0.

Then, the optimal CEC increment E_add could be expressed by Equation (5):

$$E_{add}=\min (\min (E_{add{s}_1}),\min (E_{add{s}_2}))$$

(5)

where $E_{add{s}_1}$ is the CEC increment of Figure 7a, and $E_{add{s}_2}$ is the CEC increment of Figure 7b.

In addition, when considering the distances of the chiplets with different shapes, the distances (dotted line) between the midpoints of chiplets could be taken as the average distances, as shown in Figure 8. When calculating the distances between chiplets in this way, the distances between chiplets placed horizontally and vertically would also be different. In Figure 8, the dotted line is the Manhattan distance between the chiplets. When the chiplets were placed vertically, the distance between chiplet 0 and chiplet 2 was 3.5 units, while when the chiplets were placed horizontally, the distance between the two chiplets was 2.5 units. Therefore, the horizontal and vertical placements should have been calculated separately, and we could obtain the minimum E_add by the following Equation (6):

$$E_{add}=\min (\min (E_{addhor}),\min (E_{addver})),$$

(6)

where E_addhor is the CEC increment of the chiplet placed horizontally and E_addver is the CEC increment of the chiplet placed vertically.

According to these steps, the next_node function would decide which node was selected.

4. Experiment Results

This study used the C++ language to implement the CCEOA in order to verify its performance and efficiency. To examine the mapping process and algorithm performance, we used a 2.5-D IC integration with 22 chiplets as an example. The entire algorithm took only 0.101 s to produce all the results. The layout of the chiplets could be derived very efficiently. According to initialnode_generate function, the initial nodes had five different distributions, and the algorithm could obtain five alternative final mapping schemes, as illustrated in Figure 9. In Figure 9d, the optimal CEC was 943.95 μJ. The chiplet with the highest communication volume was in the middle, and the other chips with which it communicated were distributed around it, minimizing the distance and CEC between them.

In Figure 10a, compared with the original layout placement, all CECs of these schemes obtained by our algorithm were lower than the initial layout. The CEC of the optimal scheme was 943.95 μJ (Figure 10a), which was 22.0% lower than the initial layout. Figure 10b shows the 3D schematic diagram of the optimal result.

5. Conclusions

A proper layout of chiplets in 2.5-D integration could improve the communication energy consumption of the whole system. In this paper, we proposed an algorithm considering the area factor of the chiplet using multiple nodes to map them based on the SYMMAP algorithm. At the same time, due to the area factor, we examined the selection of unmapped nodes, including secondary local exploration methods. The CECs of the horizontal placement and vertical placement were also calculated, respectively, and the smaller value was taken as the result. Through the above steps, we could complete the mapping of chiplets and obtain a chiplet layout placement with a low CEC. Based on a 2.5-D IC integration with 22 chiplets, the CEC of the optimal scheme of our algorithm was 22% lower than the initial layout. Furthermore, based on our heuristic algorithm, the inputs, including the numbers and sizes of chiplets and the size of the topology, could be modified to suit the needs of different systems.