A Simplified Hard-Switching Loss Model for Fast-Switching Three-Level T-Type SiC Bridge-Legs

Abstract

Hard-switching losses in three-level T-type (3LTT) bridge-legs cannot be directly estimated from datasheet energy loss curves, which are given for symmetric two-level half-bridge configurations only. The commutations in a 3LTT bridge-leg occur between semiconductors with different blocking voltages and/or current ratings, and involve a third semiconductor device in the switching transition, which contributes additional capacitive losses. This paper, therefore, describes a simplifed approach to estimate a lower bound for the hard-switching losses of 3LTT bridge-legs (note that the approach is applicable to other three-level topolgies as well). In view of the very fast switching speeds of wide-bandgap semiconductors, the model neglects voltage/current overlap losses and considers only the dominating charge-related loss contributions (semiconductor output capacitances, body diode reverse-recovery charge), thus requiring minimal information from datasheets. A direct experimental verification with an 800 V DC-link 3LTT bridge-leg (1200 V and 650 V SiC MOSFETs) operating with output currents up to 25 A confirms the good accuracy of the simplified switching-loss model.

1. Introduction

Three-level converter topologies, especially in combination with wide-bandgap (WBG) power semiconductors such as SiC MOSFETs, are enabling ever more compact and more efficient power electronic converter systems [1,2,3,4], and are therefore of key importance to next-generation PFC rectifiers for battery charging, datacenter power supply modules, and inverter systems for variable-speed drives used in industry automation and electrified transport. In particular, the three-level T-type (3LTT) converter (cf., Figure 1), originally proposed in the 1970s [5], achieves very promising performance for 800 V DC-link applications, especially if modern WBG power semiconductors are employed [3,6]. Essentially, a two-level bridge-leg (with 1200 V SiC MOSFETs) is extended by a four-quadrant switch that allows the connection of the AC output terminal to the DC-link midpoint, i.e., enables three output voltage levels. The four-quadrant midpoint switch can advantageously be realized with two 650 V SiC MOSFETs connected in anti-series. Compared to other three-level topologies, such as the neutral-point-clamped (NPC) converter [7,8], or its sibling with active switches instead of clamping diodes (active NPC, ANPC) [9], the 3LTT requires, thus, fewer power semiconductors and, especially, fewer gate-drive power supplies (if the midpoint switch employs a common-source configuration); i.e., the 3LTT shows a favorable trade-off between functionality and complexity [10].

To perform a first-step comparative evaluation of different power semiconductors for a given application, there is a need to quickly estimate switching losses. Whereas datasheets usually directly provide turn-on and turn-off energy losses as a function of voltage and current for symmetric two-level bridge-legs, the situation is more complicated for 3LTT bridge-legs [6,11]. First, any commutation between two semiconductor devices also changes the blocking voltage across a third device connected to the common switching node, causing additional capacitive losses. Second, the commutations occur between semiconductors with different blocking voltage and/or current ratings (i.e., for the example mentioned above, between a 1200 V SiC MOSFET and a 650 V SiC MOSFET used as the midpoint switch). For these reasons, it is not possible to use the switching loss data available in typical semiconductor datasheets directly for estimating the switching losses of a certain device combination in a 3LTT bridge-leg.

Therefore, this paper provides a simplified approach to estimate the minimum hard-switching losses of SiC-MOSFET-based 3LTT bridge-legs by considering only charge-related losses (i.e., capacitive and reverse-recovery losses), which effectively dominate the hard-switching energy loss for fast-switching power semiconductors [12]. This paper consolidates existing contributions to semiconductor output capacitance charge/discharge loss modeling for three-level bridge-legs [6,11,13], as well as to the simplified estimation of diode reverse-recovery losses [6,11], into a compact, straightforward loss modeling approach.

In contrast to the interesting switching loss estimation method developed in [13], which requires double-pulse test loss measurement results, the loss model proposed herein can be parametrized with datasheet information on the devices’ output capacitances, C_oss, and reverse-recovery charge, Q_rr, only. Additionally, targeting GaN devices, the modeling approach outlined in [13] does not account for reverse-recovery losses, i.e., it is not directly applicable to 3LTT bridge-legs with SiC MOSFETs. The switching-loss model in [13] has only been verified indirectly at the converter level by measuring the total converter losses of a 3LTT undiriectional rectifier adopting 650 V GaN HEMTs and 1200 V SiC Schottky diodes.

In this paper, a dedicated experimental verification of the proposed loss model is performed on an 800 V DC-link 3LTT bridge-leg prototype (using 1200 V and 650 V SiC MOSFETs) through accurate calorimetric loss measurements. The experimental results confirm an almost perfect prediction of capacitive charge/discharge losses and show that the proposed model, including diode reverse-recovery, achieves a maximum hard-switching loss underestimation error of 18% (i.e., due to neglecting overlap losses [12]). It is worth highlighting that even though this work focuses on the 3LTT converter topology (for reasons of clarity and conciseness), the proposed hard-switching-loss model can be applied to arbitrary three-level bridge-legs (e.g., NPC, ANPC, etc.), as explained in [6].

The paper is organized as follows. First, Section 2 discusses the modeling of capacitive losses in a 3LTT bridge-leg, clarifying also the impact of the third device connected to the switching node but not actively involved in the commutation. In Section 3, a simplified model for the estimation of the bridge-leg losses in hard-switching operation is described, taking into account both capacitive and reverse-recovery loss contributions. Section 4 provides a direct experimental verification of the proposed models, using highly accurate calorimetric measurements of the semiconductor losses. Finally, Section 5 concludes the paper and gives an outlook on future developments, highlighting the importance of comprehensive reverse-recovery information in device datasheets.

2. Three-Level T-Type Capacitive Loss Analysis

This section provides a detailed analysis of the losses related to the charging/discharging of the semiconductor output capacitances in a 3LTT bridge-leg, as shown in Figure 1. In particular, this analysis focuses only on the upper half of the bridge-leg (i.e., ${\mathrm{T}}_1\leftrightarrow {\mathrm{T}}_2$ switching transitions, cf., Figure 1), since all results can be extended directly to the other bridge-leg half for reasons of symmetry. According to Figure 1, four different switching events can occur, depending on the commutation sequence (i.e., ${\mathrm{T}}_1\to {\mathrm{T}}_2$ or ${\mathrm{T}}_2\to {\mathrm{T}}_1$) and the direction of the bridge-leg output current $I_{\mathrm{sw}}$. For each situation, the respective figure shows the steady state before the transition or the dead time interval, the transition interval (only for hard-switching events), and the steady state after the transition.

For example, Figure 1a shows a transition from ${\mathrm{T}}_2$ to ${\mathrm{T}}_1$ (${\mathrm{T}}_1\leftarrow {\mathrm{T}}_2$) with $I_{\mathrm{sw}}>0$. In the initial steady state (not shown), the switching node is connected to the DC-link midpoint via ${\mathrm{T}}_2$ and ${\mathrm{T}}_3$. The dead time interval starts when ${\mathrm{T}}_2$ turns off. During this interval, the switching node voltage does not change, as the load current flows in ${\mathrm{T}}_2$’s body diode until ${\mathrm{T}}_1$ turns on. This turn-on process dissipates the energy $E_{\mathrm{oss},\mathrm{T}1}$ stored in the output capacitance of ${\mathrm{T}}_1$, and causes the indicated current flows to charge the output capacitance of ${\mathrm{T}}_2$ to $V_{\mathrm{dc}}/2$ and to charge ${\mathrm{T}}_4$’s output capacitance from $V_{\mathrm{dc}}/2$ to $V_{\mathrm{dc}}$. The turn-on process of ${\mathrm{T}}_1$ also initiates the reverse-recovery process of ${\mathrm{T}}_2$’s body diode, which is discussed in Section 3. Finally, in the new steady state, the switching node is connected to the positive DC-link rail via ${\mathrm{T}}_1$. Since a certain amount of energy is always dissipated during the switching transition (e.g., $E_{\mathrm{oss},\mathrm{T}1}$), this is considered a hard-switching event. Similarly, Figure 1b shows the transition in the opposite direction, i.e., from ${\mathrm{T}}_1$ to ${\mathrm{T}}_2$ (${\mathrm{T}}_1\to {\mathrm{T}}_2$) with $I_{\mathrm{sw}}>0$. Once ${\mathrm{T}}_1$ turns off, the load current charges/discharges the involved output capacitances until the switching node is finally connected to the DC-link midpoint via ${\mathrm{T}}_3$ and ${\mathrm{T}}_2$’s body diode. The turn-on of ${\mathrm{T}}_2$ at the end of the dead time interval is, thus, lossless, and accordingly, this transition is a soft-switching event. The transitions in Figure 1c,d follow analogous steps.

The indicated charging/discharging currents give rise to losses. To quantify these capacitive switching losses, all four switching events shown in Figure 1 are analyzed using the method reported in [14], which is based on the energy balance expression

$$E_{\mathrm{loss},\mathrm{cap}}=E_{\mathrm{initial}}+E_{\mathrm{source}}-E_{\mathrm{final}}-E_{\mathrm{load}},$$

(1)

where $E_{\mathrm{initial}}$ and $E_{\mathrm{final}}$ are the total stored energies in all device capacitances before and after the commutation, respectively, while $E_{\mathrm{source}}$ and $E_{\mathrm{load}}$ are the energies provided by the DC-link and absorbed by the output load during the transition, respectively. Note that instantaneous switching transitions are assumed (i.e., no V-I overlap across the MOSFET channel); hence, no energy is transferred to the load during the hard-switching events (a) and (c) (i.e., $E_{\mathrm{load}}=0$), whereas no loss is generated during the soft-switching events (b) and (d) (i.e., $E_{\mathrm{loss},\mathrm{cap}}=0$, assuming a sufficient dead time to complete the voltage transition [14]). Therefore, the energy balance terms for the two hard-switching events (a) and (c) are derived as

$$\begin{array}{cc}\hfill I_{\mathrm{sw}}>0:& \left\{\begin{array}{c}{\displaystyle E_{\mathrm{initial}}=E_{\mathrm{oss},\mathrm{T}1}(V_{\mathrm{dc}}/2)+E_{\mathrm{oss},\mathrm{T}4}(V_{\mathrm{dc}}/2)}\hfill \\ {\displaystyle E_{\mathrm{final}}=E_{\mathrm{oss},\mathrm{T}2}(V_{\mathrm{dc}}/2)+E_{\mathrm{oss},\mathrm{T}4}\left(V_{\mathrm{dc}}\right)}\hfill \\ {\displaystyle E_{\mathrm{source}}=Q_{\mathrm{oss},\mathrm{T}2}(V_{\mathrm{dc}}/2)\frac{V_{\mathrm{dc}}}{2}+\left[Q_{\mathrm{oss},\mathrm{T}4}\left(V_{\mathrm{dc}}\right)-Q_{\mathrm{oss},\mathrm{T}4}(V_{\mathrm{dc}}/2)\right]V_{\mathrm{dc}}}\hfill \end{array}\right.\hfill \end{array}$$

(2)

$$\begin{array}{cc}\hfill I_{\mathrm{sw}}<0:& \left\{\begin{array}{c}{\displaystyle E_{\mathrm{initial}}=E_{\mathrm{oss},\mathrm{T}2}(V_{\mathrm{dc}}/2)+E_{\mathrm{oss},\mathrm{T}4}\left(V_{\mathrm{dc}}\right)}\hfill \\ {\displaystyle E_{\mathrm{final}}=E_{\mathrm{oss},\mathrm{T}1}(V_{\mathrm{dc}}/2)+E_{\mathrm{oss},\mathrm{T}4}(V_{\mathrm{dc}}/2)}\hfill \\ {\displaystyle E_{\mathrm{source}}=Q_{\mathrm{oss},\mathrm{T}1}(V_{\mathrm{dc}}/2)\frac{V_{\mathrm{dc}}}{2}-\left[Q_{\mathrm{oss},\mathrm{T}4}\left(V_{\mathrm{dc}}\right)-Q_{\mathrm{oss},\mathrm{T}4}(V_{\mathrm{dc}}/2)\right]\frac{V_{\mathrm{dc}}}{2}}\hfill \end{array}\right.\hfill \end{array}$$

(3)

where $Q_{\mathrm{oss}}$ and $E_{\mathrm{oss}}$ refer to the charge and the energy stored in the semiconductor output capacitance $C_{\mathrm{oss}}$, respectively:

$$Q_{\mathrm{oss}}={\int }_0^{V_{\mathrm{DS}}}{C}_{\mathrm{oss}}\left(v\right)\mathrm{d}v,E_{\mathrm{oss}}={\int }_0^{V_{\mathrm{DS}}}{C}_{\mathrm{oss}}\left(v\right)v\mathrm{d}v.$$

(4)

For reasons of clarity and compactness, we define the energy terms

$$E_{\mathrm{a}}=E_{\mathrm{oss}}(V_{\mathrm{dc}}/2),$$

(5)

$$E_{\mathrm{b}}=Q_{\mathrm{oss}}(V_{\mathrm{dc}}/2)\frac{V_{\mathrm{dc}}}{2}-E_{\mathrm{oss}}(V_{\mathrm{dc}}/2),$$

(6)

$$E_{\mathrm{c}}=[E_{\mathrm{oss}}\left(V_{\mathrm{dc}}\right)-E_{\mathrm{oss}}(V_{\mathrm{dc}}/2)]-[Q_{\mathrm{oss}}\left(V_{\mathrm{dc}}\right)-Q_{\mathrm{oss}}(V_{\mathrm{dc}}/2)]\frac{V_{\mathrm{dc}}}{2},$$

(7)

$$E_{\mathrm{d}}=[Q_{\mathrm{oss}}\left(V_{\mathrm{dc}}\right)-Q_{\mathrm{oss}}(V_{\mathrm{dc}}/2)]V_{\mathrm{dc}}-[E_{\mathrm{oss}}\left(V_{\mathrm{dc}}\right)-E_{\mathrm{oss}}(V_{\mathrm{dc}}/2)],$$

(8)

which are graphically illustrated in Figure 2 for a Wolfspeed 1200 V 32 mΩ SiC MOSFET and V_dc = 800 V. By inserting Equations (2) and (3) in Equation (1) and leveraging Equations (5)–(8), straightforward capacitive loss expressions are obtained:

$$E_{\mathrm{loss},\mathrm{cap}}(I_{\mathrm{sw}}>0)=E_{\mathrm{a},{\mathrm{T}}_1}+E_{\mathrm{b},{\mathrm{T}}_2}+E_{\mathrm{d},{\mathrm{T}}_4},$$

(9)

$$E_{\mathrm{loss},\mathrm{cap}}(I_{\mathrm{sw}}<0)=E_{\mathrm{a},{\mathrm{T}}_2}+E_{\mathrm{b},{\mathrm{T}}_1}+E_{\mathrm{c},{\mathrm{T}}_4}.$$

(10)

Note that different expressions are obtained for $I_{\mathrm{sw}}>0$ and $I_{\mathrm{sw}}<0$, as the power semiconductors involved in the respective commutations are different (i.e., $T_1\ne T_2$; for example, in a bridge-leg with 800 V DC-link voltage, ${\mathrm{T}}_1$ is typically a 1200 V MOSFET, whereas ${\mathrm{T}}_2$ is typically a 650 V MOSFET) and the charging/discharging of $C_{\mathrm{oss},\mathrm{T}4}$ (i.e., the output capacitance of the third power semiconductor not actively involved in the commutation) is affected by the current direction, as it is charged from $V_{\mathrm{dc}}/2$ to $V_{\mathrm{dc}}$ in the hard-switching transition with $I_{\mathrm{sw}}>0$, shown in Figure 1a, but discharged from $V_{\mathrm{dc}}$ to $V_{\mathrm{dc}}/2$ in the hard-switching transition with $I_{\mathrm{sw}}<0$, shown in Figure 1c.

3. Simplified Hard-Switching Loss Model

The total losses generated by a hard-switching commutation in an arbitrary SiC MOSFET bridge-leg can be expressed as [12]

$$E_{\mathrm{sw}}=E_{\mathrm{loss},\mathrm{cap}}(V_{\mathrm{sw}},I_{\mathrm{sw}})+Q_{\mathrm{rr}}\left(I_{\mathrm{sw}}\right)V_{\mathrm{sw}}+\frac{1}{2}\frac{V_{\mathrm{sw}}^2}{\raisebox{1ex}{$\mathrm{d}v$}\!\left/ \!\raisebox{-1ex}{$\mathrm{d}t$}\right.}{I}_{\mathrm{sw}}+\frac{1}{2}\frac{I_{\mathrm{sw}}^2}{\raisebox{1ex}{$\mathrm{d}i$}\!\left/ \!\raisebox{-1ex}{$\mathrm{d}t$}\right.}{V}_{\mathrm{sw}},$$

(11)

where $V_{\mathrm{sw}}$ and $I_{\mathrm{sw}}$ are the switched voltage and current, respectively, $E_{\mathrm{loss},\mathrm{cap}}$ is the capacitive loss contribution (depending on the switched voltage and the direction of the switched current, cf., Equations (9) and (10) in Section 2, and $Q_{\mathrm{rr}}$ is the reverse-recovery charge of the MOSFET body diode involved in the commutation process (e.g., the body diode of ${\mathrm{T}}_2$ in Figure 1a and the body diode of ${\mathrm{T}}_1$ in Figure 1c). The last two terms of Equation (11) represent the V-I overlap losses and depend on the voltage and current time derivatives during the overlap time. It is worth noting that Equation (11) only represents turn-on losses, as the switching losses during the turn-off transition can typically be neglected if the MOSFET is assumed to be turned off fast enough [12].

A simplified switching-loss model, only accounting for the unavoidable charge-related losses [6,11], can be obtained by assuming infinitely fast transitions, such that the V-I overlap loss contributions in Equation (11) can be neglected. This assumption also allows to express the diode reverse-recovery charge as a linear function of the switched current [15]: infinitely fast current transitions force the complete diode forward bias injected charge (which is proportional to the conducted current) to be swept away as $Q_{\mathrm{rr}}$, because no time is left for charge recombination to take place. Thus, we obtain

$$Q_{\mathrm{rr}}\approx \tau \left|I_{\mathrm{sw}}\right|,$$

(12)

where $\tau$ is the charge carrier recombination lifetime. Therefore, a simplified linear switching-loss model with respect to the switched current is obtained from Equation (11) as

$$E_{\mathrm{sw}}\approx E_{\mathrm{loss},\mathrm{cap}}(V_{\mathrm{sw}},I_{\mathrm{sw}})+\tau \left|I_{\mathrm{sw}}\right|V_{\mathrm{sw}},$$

(13)

which represents a theoretical lower limit (as overlap losses are neglected) for hard-switching losses in arbitrary SiC MOSFET bridge-legs.

Remarkably, Equation (13) solely depends on typically available manufacturer datasheet information, since $E_{\mathrm{loss},\mathrm{cap}}$ can be extracted from the $C_{\mathrm{oss}}\left(v\right)$ curve (cf., Section 2), and $\tau$ can be obtained from the reverse-recovery charge data (i.e., $Q_{\mathrm{rr}}$, $I_{\mathrm{sw}}$) by inverting Equation (12). In particular, with $\tau$ being approximately linearly dependent on the semiconductor junction temperature $T_{\mathrm{j}}$ [16], two $Q_{\mathrm{rr}}$ values at different temperatures are sufficient to roughly estimate the reverse-recovery losses for an arbitrary $T_{\mathrm{j}}$. It is worth noting that datasheet values for $Q_{\mathrm{rr}}$ typically include the semiconductor’s $Q_{\mathrm{oss}}\left(V_{\mathrm{sw}}\right)$, as the bipolar and capacitive charge components are indistinguishable during reverse-recovery charge measurements [17]. Therefore, $Q_{\mathrm{oss}}$ must be first subtracted from datasheet $Q_{\mathrm{rr}}$ values before using them in Equation (12).

4. Experimental Validation

This section aims to validate and assess the accuracy first of the capacitive loss analysis described in Section 2, and then its combination with the simplified hard-switching-loss model proposed in Section 3. We use the 3LTT bridge-leg prototype shown in Figure 3, which employs third-generation 1200 V 32 mΩ (for ${\mathrm{T}}_1,{\mathrm{T}}_4$) and 650 V 25 mΩ (for ${\mathrm{T}}_2,{\mathrm{T}}_3$) SiC MOSFETs from Wolfspeed in four-pin TO-247-4 packages (i.e., featuring a Kelvin source pin for faster switching). To obtain accurate switching loss results, we employ a transient calorimetric measurement method [18], specifically, the variant presented and validated in [19]. With this approach, the semiconductor devices are mechanically connected and thermally coupled to a brass block acting as a heat sink. By measuring the time required for the brass block temperature to increase by a defined amount (i.e., by 10 °C in the present case), and by subtracting the estimated conduction losses (the on-state resistance of the devices under test is measured for different temperatures during the calibration phase of the calorimetric measurement setup), the semiconductor switching losses can be extracted.

4.1. No-Load Operation ($I_{\mathrm{sw}}=0$)

To verify the capacitive loss model described in Section 2, loss measurements at zero output current (i.e., no-load) are performed for different switched voltages (i.e., different DC-link voltages). The no-load operation allows to avoid all current-dependent terms in Equation (11), and thus, to accurately determine the 3LTT bridge-leg capacitive losses, which are defined by the sum of Equations (9) and (10) as

$$E_{\mathrm{sw}}(I_{\mathrm{sw}}=0)=Q_{\mathrm{oss},\mathrm{T}1}(V_{\mathrm{dc}}/2)\frac{V_{\mathrm{dc}}}{2}+Q_{\mathrm{oss},\mathrm{T}2}(V_{\mathrm{dc}}/2)\frac{V_{\mathrm{dc}}}{2}+E_{\mathrm{c},{\mathrm{T}}_4}+E_{\mathrm{d},{\mathrm{T}}_4}.$$

(14)

Figure 4 compares the calorimetrically measured no-load losses and the datasheet-based estimations using the proposed capacitive switching-loss model. To quantify the additional capacitive energy contribution $E_{\mathrm{c},\mathrm{T}4}+E_{\mathrm{d},\mathrm{T}4}$ coming from the presence of a third switch that is not actively involved in the commutation (i.e., ${\mathrm{T}}_4$ for the case at hand), two sets of measurements are performed, with ${\mathrm{T}}_4$ electrically connected or disconnected to the circuit. The results show excellent correspondence between measurements and estimations, supporting the validity of the described capacitive loss model.

4.2. Operation under Load ($I_{\mathrm{sw}}>0$, $I_{\mathrm{sw}}<0$)

To assess the accuracy of the simplified hard-switching-loss model proposed in Section 3, loss measurements for positive and negative bridge-leg output currents ($I_{\mathrm{sw}}$, cf., Figure 1) are performed. Due to the temperature dependency of the reverse-recovery time constant $\tau$, the bridge-leg duty cycle and switching frequency are adjusted to always achieve an estimated semiconductor junction temperature of around 125 °C (±10 °C). The switching losses are estimated according to the simplified loss model in Equation (13), i.e.,

$$E_{\mathrm{sw}}(I_{\mathrm{sw}}>0)=E_{\mathrm{a},{\mathrm{T}}_1}+E_{\mathrm{b},{\mathrm{T}}_2}+E_{\mathrm{d},{\mathrm{T}}_4}+{\tau }_{{\mathrm{T}}_2}\left|I_{\mathrm{sw}}\right|\frac{V_{\mathrm{dc}}}{2},$$

(15)

$$E_{\mathrm{sw}}(I_{\mathrm{sw}}<0)=E_{\mathrm{a},{\mathrm{T}}_2}+E_{\mathrm{b},{\mathrm{T}}_1}+E_{\mathrm{c},{\mathrm{T}}_4}+{\tau }_{{\mathrm{T}}_1}\left|I_{\mathrm{sw}}\right|\frac{V_{\mathrm{dc}}}{2}.$$

(16)

As the $Q_{\mathrm{rr}}$ information of both the 1200 V and 650 V MOSFETs is only provided at T_j = 175 °C; the datasheets belonging to the same semiconductor devices in a different, surface-mount TO-263-7L package are used to extract $\tau$ at T_j = 25 °C, enabling a linear interpolation between the $\tau \left(T_{\mathrm{j}}\right)$ values.

Figure 5 and

Table 1. Comparison between estimated and measured hard-switching losses in the 3LTT bridge-leg as a function of the switched current $I_{\mathrm{sw}}$ at $V_{\mathrm{dc}}$ = 800 V and $T_{\mathrm{j}}$ ≈ 125 °C. The losses are estimated with (15) for $I_{\mathrm{sw}}>0$ and with (16) for $I_{\mathrm{sw}}<0$.

Switched Current	Measured Loss	Estimated Loss	Error
−25 A	155.4 μJ	128.3 μJ	−17.5%
−20 A	140.3 μJ	116.9 μJ	−16.7%
−15 A	123.0 μJ	105.5 μJ	−14.2%
−10 A	107.9 μJ	94.1 μJ	−12.7%
−5 A	90.6 μJ	82.7 μJ	−8.6%
+5 A	96.3 μJ	85.8 μJ	−10.9%
+10 A	116.6 μJ	100.2 μJ	−14.0%
+15 A	137.3 μJ	114.7 μJ	−16.5%
+20 A	154.5 μJ	129.2 μJ	−16.4%
+25 A	174.3 μJ	143.6 μJ	−17.6%

compare the experimental results and the estimations obtained with the proposed datasheet-based switching-loss model for the 3LTTC, whereby Figure 5 also provides a breakdown of the the capacitive loss contributions from Equations (9) or (10), respectively, and of the reverse-recovery losses. Considering its simplicity, the model predicts the measured hard-switching losses well, achieving a maximum underestimation error of 18% in the considered load current range. The model accuracy reduces with increasing $\left|I_{\mathrm{sw}}\right|$, as the unaccounted-for V-I overlap (caused by the finite $\raisebox{1ex}{$\mathrm{d}v$}\!\left/ \!\raisebox{-1ex}{$\mathrm{d}t$}\right.$ and $\raisebox{1ex}{$\mathrm{d}i$}\!\left/ \!\raisebox{-1ex}{$\mathrm{d}t$}\right.$ values) increasingly affects the overall losses. The deviation between the measured and estimated losses is, in fact, well reflected by the approximate evaluation of the V-I overlap losses with Equation (11), assuming reasonable values of $\raisebox{1ex}{$\mathrm{d}v$}\!\left/ \!\raisebox{-1ex}{$\mathrm{d}t$}\right.$ ≈ 100 $\raisebox{1ex}{$\mathrm{V}$}\!\left/ \!\raisebox{-1ex}{$\mathrm{ns}$}\right.$ and $\raisebox{1ex}{$\mathrm{d}i$}\!\left/ \!\raisebox{-1ex}{$\mathrm{d}t$}\right.$ ≈ 10 $\raisebox{1ex}{$\mathrm{A}$}\!\left/ \!\raisebox{-1ex}{$\mathrm{ns}$}\right.$ (i.e., according to measurements and datasheet information). As the switching speeds of next-generation WBG power transistors are expected to show an increasing tendency, driven by the trend towards further integration of power electronic converters and, especially, by integrated gate-drive circuits [20], the accuracy of the proposed loss model is expected to improve further.

5. Conclusions

This paper describes a simplified method to estimate the hard-switching losses in SiC-based three-level T-type (3LTT) bridge-legs. Remarkably, the proposed method is applicable to other three-level topologies as well. Neglecting voltage/current overlap losses and considering only charge-related loss components, the proposed approach requires minimal information from datasheets. It can not only account for the capacitive charge/discharge loss caused by the third semiconductor device that is subject to the voltage transient during hard-switching events, but it is also especially applicable to commutations between semiconductor devices with different blocking voltage and/or current ratings. The proposed loss model is verified experimentally by calorimetrically measuring the switching losses of an 800 V DC-link 3LTT bridge-leg prototype employing 1200 V and 650 V SiC MOSFETs. The results show that, with the proposed model, the basic semiconductor information provided in the datasheet are sufficient to predict the switching losses of the 3LTT with reasonable accuracy, resulting in a maximum underestimation error of 18% with respect to calorimetric measurements.

Whereas a certain loss underestimation must be expected due to not considering the overlap losses (whose importance reduces with increasing switching speeds enabled by future integrated gate drivers), it is worth highlighting that the estimation accuracy strongly depends on the quality of the $Q_{\mathrm{rr}}$ information provided by the semiconductor device manufacturers in their datasheets. Unfortunately, this information is often unreliable (e.g., possibly including unwanted high-frequency ringing effects [17]) and/or is only provided for one operating point (i.e., a single combination of $I_{\mathrm{sw}}$, $T_{\mathrm{j}}$, $\raisebox{1ex}{$\mathrm{d}i$}\!\left/ \!\raisebox{-1ex}{$\mathrm{d}t$}\right.$). Therefore, better $Q_{\mathrm{rr}}$ data quality, considering, for instance, the measurement procedure proposed in [17], and the availability of more data points in datasheets could further improve the accuracy of the proposed straightforward modeling approach for hard-switching losses in 3LTT (and other three-level) bridge-legs.