Design and Analysis of Fault-Tolerant 1:2 Demultiplexer Using Quantum-Dot Cellular Automata Nano-Technology

Abstract

Quantum-dot Cellular Automata (QCA) is an innovative paradigm bringing hopeful applications in the perceptually novel computing layout in quantum electronics. The circuits manufactured by QCA technology can provide a notable decrease in size, rapid-switching velocity, and ultra-low power utilization. The demultiplexer is a beneficial component to optimize the whole process in any logical design, and therefore is very important in QCA. Moreover, fault-tolerant circuits can improve the reliability of digital circuits by redundancy. Hence, the present investigation illustrates a novel QCA-based fault-tolerant 1:2 demultiplexer construct that employs a two-input AND gate and inverter. The functionality of the suggested layout was executed and evaluated with the utilization of the QCADesigner 2.0.3 simulator. This paper utilizes cell redundancy on the wire, inverter, and AND gates for designing a fault-tolerant demultiplexer. Four components (i.e., missing cells, dislocation cells, extra cells, and misalignment) were analyzed by the QCADesigner simulator. The simulation results demonstrated that our proposed QCA-based fault-tolerant 1:2 demultiplexer acted more efficiently than prior constructs regarding delay and fault tolerance. The proposed fault-tolerant 1:2 demultiplexer could attain high fault-tolerance when single missing cell or extra cell faults exist in the QCA layout.

1. Introduction

Since 1993, nano-technology and relevant domains have attracted more attention [1]. The requests for high-velocity operation with down-energy utilization and leakage current, along with the scaling restrictions of CMOS constructs, have forced investigators to look for substitution technologies [2]. When the component size reduces, efficiency enhances; thus, a direct connection exists between efficiency and compression [3]. Quantum-dot Cellular Automata (QCA) is one of the most hopeful nano-scale technologies that has been presented as a transistor-less paradigm [4,5]. Molecular QCA encourages nanometer-scale units with ultra-high device densities at room temperature to function with tiny heat release [6,7,8]. Some investigations concerning nano-architectures and their processes are relevant to enormous information-laden issues, using various QCA devices at a higher abstraction stage [9]. They perform independently from nano-scale manufacturing technology. QCA technology has advantages such as high device density, low power consumption, fast operation, and small dimensions [10,11]. Manufacturing fault stages and operational time defect rates are the disadvantages of this technology [12]. Therefore, the QCA-based layout of devices has crucially notable benefits compared to conventional computing layouts.

In this technology the cell positions of the execution phase specify the precision of the QCA operation. This causes QCA to perform appropriately. The cells should be aligned and located accurately in their sequence. Besides the defects in the QCA execution phase, the fabrication procedure may lead to some types of failures [13]. Lately, several investigators have assessed the fault-tolerant attributes in many technologies such as QCA [14,15,16,17]. Demultiplexers and multiplexers are beneficial elements for schematizing several significant logic circuits. The demultiplexer is generally known as a data disseminator. It is a combinational circuit that holds input data and then turns them into any output lines. The defective QCA circuits’ behavior needs the fault-tolerant demultiplexer schematization [18,19,20].

In this research, a new structure for a fault-tolerant 1:2 demultiplexer based on the QCA was attained using fault-tolerant majority and redundancy in the wire and inverter. Overall, the objectives of the present article were:

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To develop a fault-tolerant 1:2 demultiplexer that outperformed existing quantum comparators in terms of ALP, cost, and delay;

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To suggest a coplanar architecture for designing a fault-tolerant 1:2 demultiplexer;

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To compare the presented design with other layouts regarding complexity, cell counts, fault tolerance, and the utilized area.

Section 2 of this article demonstrates an overview of related demultiplexer designs. Section 3 supplies the 1:2 demultiplexer schematization in the quantum cell technology and checks its performance. Section 4 presents the outcomes of the simulation and indicates the precision of the schematized circuit. Finally, Section 5 concludes the paper and suggests some possible future work.

2. Basic Concepts and Related Works

2.1. QCA Cell

A square cell with two electrons in four spots is the basic component of QCA technology. These electrons can freely tunnel between the dots, but not out of the cell. P = 1 and P = +1 are two stable states that produce two polarizations. The digital numbers “0” and “1” correspond to these two polarizations [21,22]. Figure 1a shows the polarization of the QCA cells.

2.2. QCA Majority Gate and Inverter Gate

The majority and the inverter gates are two important QCA gates. In this technology, the majority gate with three inputs is critical in the construction of digital circuits [23,24]. This gate is shown in Figure 1b. If the constant values “1” and “0” are assigned to one of the inputs, the majority gate will act as an AND gate and an OR gate, respectively. The output of the inverter will be the inverse of its input [25,26]. The inverter gate is shown in Figure 1c. QCA digital circuits were implemented using these two basic gates.

2.3. QCA Faults

In the design of QCA circuits, the following faults are common [26,27,28]:

• Missing cell (Figure 2a);
• Additional cell (Figure 2b);
• Cell displacement (Figure 2c);
• Rotation cell (Figure 2d).

2.4. Related Works

Lately, investigators have presented several demultiplexer designs. The remaining part of this section inspects these schematizations.

Iqbal and Khanday [18] proposed the new and beneficial schematizations of a modular QCA demultiplexer and MUX. Their suggested MUX-demultiplexer contrasted with recent schematizations regarding complexity, area, and velocity. Their outcomes indicated notable developments in the suggested layouts within the usual methods. Their simulation demonstrated that their suggested multiplexer–demultiplexer layouts contained less complexity than the presented layouts. They examined the simulation results by QCADesigner 2.0.3.

Furthermore, Shah and Khanday [20] proposed another optimal design of a QCA-based demultiplexer. A modular approach was developed to design a 1:2n demultiplexer using this as a building block. The employed design methodology led to a smaller area of occupation and better efficiency of circuit stability, noise, and energy utilization than the previously presented design. To confirm the functionality of the proposed structures, they used QCADesigner 2.0.3.

Ahmad [29] also proposed a new design for 1:2n demultiplexer and 2n:1 multiplexer in QCA technology. A method was offered to execute the impressive digital logic gates employing the suggested 2n:1 multiplexer, wherein two inverters and four three-input AND gates were required. This demultiplexer design was created by the rotation of two two-input AND gates. The circuit provided in the QCADesigner 2.0.3 software was implemented and simulated. Its correct operation confirmed and approved the functionality of the suggested constructs. Some Boolean proofs were conducted.

Moreover, Khan and Arya [30] suggested and inspected an optimized and simple QCA-dependent single-layered demultiplexer with the utilization of two clocks, i.e., two majority gates and one inverter. In this demultiplexer, the input signal was applied to the majority gates, which operated with the select line’s utilization to produce the outputs. The postponement of the suggested clock was 0.5. Moreover, their proposed design was coplanar and used a low number of cells. They used QCADesigner 2.0.3 to examine the complexity and accuracy of the circuit.

Finally, Ganesh and Kishore [31] proposed the QCA subtractive algorithm and combinational circuit algorithms for circuit simulation. Here, the majority voting layout procedure was utilized by improving basic QCA sequential and combinational circuits. Moreover, they generated simple T and D flip-flops with the utilization of QCA technology. The simulation outcomes of the QCADesigner 2.0.3 indicated that the suggested circuits worked well. The mentioned simulations and algorithms were beneficial in generating complex QCA circuits.

3. The Proposed Fault-Tolerant Demultiplexer

Demultiplexer circuits are regularly utilized in digital electronics, QCA technology, and communication systems. The demultiplexer circuit handles single input data and transfers it to multiple output lines. It is recognized as a data distributor. Most QCA circuits have been produced using inverter and majority gates; however, the normal majority and inverter gates do not behave well in the instance of general faults. For this reason, researchers proposed a new fault-tolerant majority and inverter gate, as seen in Figure 3 [32].

The demultiplexer converts input serial data into several output parallel lines. The block diagram of the proposed demultiplexer is demonstrated in Figure 4a. Therefore, in designing a QCA-based fault-tolerant 1:2 demultiplexer, two clock phases are necessary for producing a stable output, as illustrated in Figure 4b. The proposed demultiplexer has output lines (O1, O2), a select line (S), and an input line (IN). Generally, it transfers the inputs to one of the outputs depending on the select (S) line value. The suggested circuit was schematized using one fault-tolerant inverter and two fault-tolerant majority gates. The demultiplexer’s single input (IN) is directly linked to an input line of the majority gates. The first inputs in majority gates are S, 0, and IN, and the second majority gate inputs are S, 0, and reverse of IN. If the select line value is ‘0′ (S = 0), the IN signal is transferred to the output O2, whereas if the value of the select line is ‘0′ (S = 1), the IN signal is transmitted to the output O1. The truth table of the digital demultiplexer is demonstrated in

Table 1. The 1:2 demultiplexer truth table.

Inputs		Outputs
IN	S	O1	O2
0	0	0	0
0	1	0	0
1	0	0	1
1	1	1	0

. Our suggested design for a fault-tolerant 1:2 demultiplexer is shown in Figure 5. The inputs were inserted from one side of the scheme and the outputs were inserted from the other. The efficiency of the fault-tolerant demultiplexer was attained through inverter gates, wire, and fault-tolerant majority. We used wire redundancy to realize the fault-tolerance ability in the suggested demultiplexer. Here, the input cells fixed the polarization. Moreover, the output and middle cells were variable, and this design is provided in one layer.

4. Simulation Results

In this paper, to simulate the suggested circuits, we used QCADesigner 2.0.3. In the rest of the section, simulation parameters, comparisons, and simulation tools will be explained.

4.1. Simulation Tools

Researchers use the QCADesigner tool to simulate, verify circuit functioning, and test circuits. Circuit layout, functionality, and the check of fault-tolerant circuits in QCA technology were performed by QCADesigner. It simulates QCA circuits depending on two various simulation engines. In this experiment both engines were used, and as a result the outcomes were similar [33,34,35,36,37].

4.2. Accuracy Analysis

The simulation results for the fault-tolerant 1:2 demultiplexer are shown in Figure 6. In this circuit, the outputs were generated after two clock phases. The simulator software generated ‘0’ and ‘1’ logic in waveforms. The values marked with the black rectangle denote input values, the values marked with a red rectangle denote output values, and the values marked with a blue rectangle denote the clock. Due to the analysis of the results, it was quite visible that the function of the introduced QCA construct for fault-tolerant 1:2 demultiplexer design was accurate. In this condition, the demanded function was available. All inputs were applied to the fault-tolerant 1:2 demultiplexer circuit, which built the true outputs.

4.3. Cell Defect Analysis

Our proposed fault-tolerant 1:2 demultiplexer was tested against the missing cell, additional cell, cell displacement, and rotation cell to show the correct operation of the proposed circuit. For this reason, 10% of the cells were inspected randomly to show the fault-tolerance ability of the proposed layout. The test results for the missing cell, additional cell, cell displacement, and rotation cell defect for the proposed fault-tolerant 1:2 demultiplexer design are shown in

Table 2. Percentage of fault tolerance attained by fault-tolerant demultiplexer in the presence of (single cell) missing cell, additional cell, cell displacement, and rotation cell.

Designs	Fault Tolerance against Missing Cell (%)	Fault Tolerance against Additional Cell (%)	Fault Tolerance against Cell Displacement (%)	Fault Tolerance against Rotation Cell (%)
Shah, Khanday [20]	15%	10%	10%	25%
Iqbal, Khanday [18]	15%	20%	15%	20%
Ahmad [29]	10%	15%	20%	10%
Khan and Arya [30]	15%	10%	15%	15%
The proposed design	100%	100%	90%	95%

. As is evident from Table 2, our fault-tolerant 1:2 demultiplexer design was 100% tolerant under the missing cell and additional cell defects. This new design was above 90% fault-tolerant under cell displacement defects, and was above 95% of cell displacement faults. As the comparison illustrated, due to the correct output when the fault occurred, the performance of the fault-tolerant 1:2 demultiplexer was better than the total demultiplexer.

Ultimately,

Table 3. Comparisons among the suggested and modern layouts.

Designs	Area (µm2)	Cells	Latency	Crossover Type	Fault Tolerance on Gates	Fault Tolerance on Wire
Shah, Khanday [20]	0.08	56	1	Coplanar	No	No
Iqbal, Khanday [18]	0.04	27	0.5	Coplanar	No	No
Ahmad [29]	0.03	21	0.75	Not required	No	No
Khan and Arya [30]	0.03	21	0.5	Not required	No	No
The proposed design	0.06	64	0.5	Coplanar	Yes	Yes

compares the proposed fault-tolerant 1:2 demultiplexer with the prior layouts regarding some important metrics such as the cells, area, crossover type, latency, fault tolerance, and fault tolerance on the wire. As shown in Table 2, the suggested fault-tolerant 1:2 demultiplexer was one of the best circuits provided due to the suitable consumption space, the single layer of the circuit, the fault resistance in the gate, and the fault resistance in the wire.

4.4. QCA Cost and Average Output Polarization

Furthermore, in order to apply the suggested fault-tolerant 1:2 demultiplexer complexity, we practiced its QCA cost function. The cost function can be calculated as follows [38,39]:

$${\mathrm{Cost}}_{\mathrm{QCA}} = \left(M^k+I+C^c\right) \times T^p, 1\le k,c,p$$

(1)

where M is the number of majority gates, C is the number of crossovers, I is the number of inverters, and T is a delay. c, k, p are the weights for crossover, majority gate, and delay, respectively. The items stated are the critical components of QCA technology, and the quantum cost is calculated using them. The decreased quantum cost demonstrated the quality of the proposed design.

In this part, several values (between 1 and 4) are estimated for these weights to be better compared. As shown in

Table 4. QCA cost for the proposed fault-tolerant 1:2 demultiplexer and other layouts.

Designs	${\mathrm{Cost}}_{\mathrm{QCA}}$
	Mode 1	Mode 2	Mode 3	Mode 4
	K, L, P = 1	K, L, P = 2	K, L, P = 3	K, L, P = 4
Our Suggested Layout	6	20	72	272
Shah, Khanday [20]	6	20	72	272
Iqbal, Khanday [18]	20	144	1088	8448
Ahmad [29]	6	20	72	272
Khan and Arya [30]	6	20	72	272

, the suggested fault-tolerant 1:2 demultiplexer had better performance than its counterparts in terms of cost, due to the use of a limited number of gates, low space consumption, and convenient clocking.

The temperature effect on the output cell’s polarization of the proposed fault-tolerant 1:2 demultiplexer is also very important. To test the Average Output Polarization (AOP), QCADesigner can also be applied with a coherent vector stimulation device [40]. The AOP can be assessed by calculating the variance between the maximum and minimum polarization [41]. The AOP function is expressed as follows:

$$\mathrm{AOP}=\frac{\mathrm{Maximum}-\mathrm{Minimum}}{2}$$

(2)

AOPs for any output cells of the expected fault-tolerant 1:2 demultiplexer are shown in

Table 5. The AOP values for the proposed fault-tolerant 1:2 demultiplexer and other designs.

Designs	Outputs	Temperature (K)
		1	2	3	4	5	6	7
Our Suggested Layout	O1	9.85	9.85	9.84	9.84	9.84	9.84	9.84
	O2	9.85	9.85	9.84	9.84	9.84	9.84	9.84
Shah, Khanday [20]	O1	9.55	9.55	9.55	9.55	9.54	9.50	9.45
	O2	9.55	9.55	9.55	9.55	9.54	9.50	9.45
Iqbal, Khanday [18]	O1	9.54	9.54	9.54	9.54	9.53	9.48	9.44
	O2	9.54	9.54	9.54	9.54	9.53	9.49	9.45
Ahmad [29]	O1	9.5	9.5	9.5	9.5	9.48	9.4	9.36
	O2	9.5	9.5	9.5	9.5	9.48	9.4	9.36
Khan and Arya [30]	O1	9.22	9.22	9.22	9.18	9.16	8.1	8.95
	O2	9.5	9.5	9.5	9.48	9.48	9.40	9.34

. The suggested fault-tolerant 1:2 demultiplexer works efficiently between 1 and 7 K (a typical temperature range in this technology). The AOP for each output cell is reduced very little. These outcomes confirmed that the proposed design had decent stability in a different range of temperatures. Therefore, the layout is very stable in the case of temperature changes.

5. Conclusions and Future Work

We proposed a new design for a fault-tolerant 1:2 demultiplexer by the fault-tolerant three-input majority (AND) gates, fault-tolerant inverter gate, and fault-tolerant wire redundancy. This design, in terms of fault tolerance, is superior to previous, similar circuits; it is among the best designs for fault-tolerant demultiplexers in terms of cell number, space, and delay intolerance. We employed the coherence vector and bistable approximation engines in QCADesigner to simulate the suggested design. The suggested layout was notably more robust than the previous designs for demultiplexers, and the outcomes showed the accuracy of this design. This fault-tolerant 1:2 demultiplexer design was 100% tolerant in single missing cell and additional cell defects. Moreover, this new design was above 90% fault-tolerant in single-cell displacement defects and was above 95% fault-tolerant in single-cell displacement faults.

We can use this new design to create a 1:n demultiplexer in QCA technology and larger circuits for future works. Moreover, the proposed circuit can schematize more complex and high-performance fault-tolerant nano-scale circuits in the future.