Design of a Digital Baseband Processor for UHF Tags

Abstract

In this paper, we present a new digital baseband processor for UHF tags. It is a low-power and low-voltage digital circuit and adopts the Chinese military standard protocol GJB7377.1. The processor receives data or commands from the RF front-end and carries out various functions, such as receiving and writing data to memory, reading and sending memory data to the RF front-end and killing tags. The processor consists of thirteen main sub-modules: TPP decoding, clock management, random number generator, power management, memory controller, cyclic redundancy check, FM0 encoding, input data processing, output data processing, command detection module, initialization module, state machine module and controller. We use ModelSim for the TPP decoding simulation and communication simulation between tag and reader, and the simulation results meet the design requirements. The processor can be applied to UHF tags and has been taped out using a TSMC 0.18 um CMOS process.

1. Introduction

Radio-frequency identification is one of the short-range wireless communication technologies commonly used on the Internet of Things and will play an increasing role in short-range communication technologies. Nowadays, RFID is growing quickly in many areas such as supply chain systems, community medical [1] and transportation systems. An RF system is composed of an antenna, reader and electronic tag. There are three crucial band categories: low-frequency, high-frequency, and ultra-high frequency (UHF) [2]. UHF tags occupy a significant market for tags due to their high stability, long transmission range and data capacity. The global market for UHF tags is expanding from 2017–2019, with approximately 15 billion UHF tags sold as of 2019 and a total market value of approximately USD 1 billion. This paper focuses on research regarding the digital baseband system of the UHF RFID tag. The digital baseband processor is the tag’s core, which plays a vital role in the communication process between the tag and reader. It controls when and how the tag receives (and sends) data to the reader.

This paper designs a digital baseband processor for passive UHF electronic tags based on the Chinese Military Standard Protocol GJB7377.1. This paper carefully describes the digital tag processor (in terms of structure) and the data processing process in detail. The digital processor consists of 13 sub-modules, is responsible for receiving the data or command from the RF front-end, and controlling the communication between the tag and the reader, following the command. The rest of the paper is as follows: Section 2 introduces the protocol standard of GJB7377.1. Section 3 introduces the general structure of the UHF electronic tag. The overall design of this paper follows the digital baseband processor and implementation methods of some modules. Section 4 discusses the simulation results of the digital baseband processor. Section 5 concludes the paper.

2. GJB7377.1 Protocol

In this paper, the digital baseband circuit of the tag is designed based on the Chinese Military Standard GJB7377.1. The protocol defines the physical layer parameters and the media access control layer of the air interface for two channels of the military RFID system (840 MHz–845 MHz and 920 MHz–925 MHz), as well as the working mode protocol. The basic content of the GJB7377.1 standard protocol is shown in

Table 1. GJB7377.1 Protocol.

	R→T Link	T→R Link
Working frequency	840–845 MHZ/920–925 MHZ	840–845 MHZ/920–925 MHZ
Modulation	DSB-ASK/SSB-ASK	ASK/PSK
Coding method	TPP	FM0/Miller
Data rate	80 kbps/160 kbps	80 kbps/640 kbps
Verification method	CRC-16	CRC-5/CRC-16
Anti-collision algorithm	DDS-BT	DDS-BT

. The contents of the table are explained as follows, ASK is the amplitude-shift key; PSK is the phase-shift key; DSB-ASK is the double-sideband amplitude-shift key; SSB is the single-sideband amplitude-shift key; DDS-BT is the dynamic disperse shrink binary tree.

3. Methods

3.1. Structure of the Ultra-High Frequency Electronic Tag

The structure composition of the UHF electronic tag is shown in Figure 1, which is composed of an antenna, RF front-end, digital processor and memory [3,4,5].

The antenna transmits and receives the tuned signal. The role of the RF front-end is to demodulate the tuned signal (received by the antenna) and transmit the demodulated baseband signal to the digital processor. As shown in Figure 1, the RF front-end contains six sub-modules: demodulation circuit, modulation circuit, clock circuit, power generation circuit, voltage regulator circuit, and reset circuit [6,7].

The structure of the demodulation circuit is shown in Figure 2: the modulated signal passes through the envelope detector, then the signal passes through a detector filter to remove unnecessary frequency bands and finally the modulated signal is converted to a baseband signal by a voltage judgment.

The structure of the modulation circuit is shown in Figure 2: the baseband signal is first modulated by ASK or PSK, then spectrally shifted using the mixer, next the excess frequency is removed using the filter to keep the required frequency, and finally, the signal power is amplified by the amplifier and then sent to the reader through the antenna.

The digital processor must realize the GJB7377.1 protocol, receive the command sent by the reader and execute the command. Commands include realizing the anti-collision algorithm of DDS-BT, executing read-write commands, completing communication between reader and tag and encoding the baseband signal for the data output from the tag.

3.2. The Design of the Tag Digital Processor

3.2.1. The Overall Systematic Design of the Digital Processor

The structure of the digital baseband processor of a UHF tag is shown in Figure 3.

The processor includes the TPP decoding module, clock management module, encoding module, power management module (power), input data processing module (input), CRC verification/generation module (CRC), random number generation module (random), control module (control), output data processing module (output), command detection module (CDM), initialization module (INIT), state machine module (state machine) and memory control module (MC). When the tag is close to the reader, the analog front-end circuit generates a stable voltage to supply power to the initialization module. After the tag completes initialization, then the RF front-end demodulates the modulated signal into a baseband signal, the baseband signal will enter the TPP decoding module. In the decoding module, the pre-synchronous code/frame synchronous code of the transmitted baseband signal is first detected, and if successfully detected, the subsequent segments of data will be decoded. The decoded data go to the data input processing module, which converts serial input data into parallel input data while decoded data is also sent to the command detection module. The decoded data of TPP is composed of command header, data bits and CRC check digit. The decoded data of TPP enters the command detection module to check the command header. The command header is parsed to obtain the command type, and signals are sent to the state machine to control the state jump. If an error occurs in the command header parsing, the parsing is stopped, and the corresponding flag bit is given. Lastly, the data is no longer sent to the CRC check module. But the command is successfully parsed in the command detection module; the data is transmitted to the CRC verification module. Then the CRC module selects the CRC-16 verification according to the protocol. The protocol stipulates that the data detection method of the forward link is CRC-16, and the data detection method of the reverse link is CRC-16/CRC-5. When the CRC is successfully verified, the controller follows the reader’s command according to the Chinese Military Standard GJB7377.1 Protocol.

When several tags communicate with one reader at the same time, the random number generation module, the time slot counter and the state machine work together to complete the anti-collision algorithm according to the DDS-BT algorithm in the Chinese Military Standard GJB7377.1 Protocol.

When the tag executes the read operation command, the control module manipulates the memory control module to communicate with the memory; then, the memory data is sent to the output processing module to convert the parallel data into serial and sent to the CRC generation module to produce the cyclic verification code. After that, the produced verification code is added to the end of the serial data, which is then sent to the coding module for FM0 coding/subcarrier Miller coding to generate a baseband signal. Whether to add the leading code depends on the Query command, and the signal will be transmitted to the RF front-end to modulate. Finally, the tuned signal is sent to the reader, using the antenna, to complete the communication between reader and tag.

When the tag executes the write operation, the controller runs the memory control module writing data to the memory. If successful, the memory returns to the success symbol after completion, which means communication between the reader and tag is finished.

3.2.2. The TPP Decoding Module

According to Chinese Military Standard GJB7377.1 Protocol, the command sent by the reader is coded by the TPP coding method, and there exists the leading code of the forward link (also called the front synchronization code/frame synchronization code) in the front of the command, the TPP coding and the leading code are shown in Figure 4 and Figure 5. In the decoding module, to successfully identify the leading code, a clock at the rate of 2.56 MHz is required to meet the accuracy requirements of the protocol [8]. The specific decoding method is as follows. First, when the falling edge level is detected, counter1 starts to count and stops when the rising edge level is detected again. If the counter1 records a time of 12.5 μs, we regard it as a separator detected, and the counter2 starts immediately. When the rising edge level is detected again, counter2 stops counting, and the value in counter2 is stored in the register, then the value is erased, and counter2 starts to count again. Finally, the value in the register measures the time interval between two adjacent rising edge levels. If the time interval is 6Tc, the calibration symbol 1 is judged, and then the calibration symbol 2 is judged when the time interval is 4Tc. After that, the command data starts to decode behind the leading code. The decoding basis is as follows: the TPP code is decoded as 00 when the time interval is between 0 and Pivot1; as 01 when the time interval is between Pivot1 and Pivot2; as 11 when the time interval is between Pivot2 and Pivot3; as 10 when the time interval is greater than Pivot3. The Tcal1 is the time length of the calibration symbol 1, and the Tcal2 is the time length of the calibration symbol 2. The protocol states that the Tcal1 is 6Tc while the Tcal2 is 4Tc, and the Tc is valued at 6.25 μs or 12.5 μs in accordance with the protocol. The formulae for Pivot1, Pivot2, and Pivot3 are as follows:

$$\begin{array}{l}\mathrm{Pivot}1=\mathrm{Tcal}1/4+\mathrm{T}\mathrm{c}\mathrm{a}\mathrm{l}2/4\\ \mathrm{P}\mathrm{i}\mathrm{v}\mathrm{o}\mathrm{t}2=\mathrm{P}\mathrm{i}\mathrm{v}\mathrm{o}\mathrm{t}1+\mathrm{T}\mathrm{c}\mathrm{a}\mathrm{l}2/4\\ \mathrm{P}\mathrm{i}\mathrm{v}\mathrm{o}\mathrm{t}3=\mathrm{P}\mathrm{i}\mathrm{v}\mathrm{o}\mathrm{t}2+\mathrm{T}\mathrm{c}\mathrm{a}\mathrm{l}2/4\end{array}$$

3.2.3. The CRC Module

The CRC algorithm can efficiently and accurately verify data and minimize errors and is mainly used for information transmission on communication lines [9].

In order to ensure the integrity of the communication data between the reader and the tag, the protocol stipulates using a circular check code for verification. The forward link is checked with CRC-16, while the reverse links are verified with CRC-16 or CRC-5. When applying the cyclic redundancy check algorithm, the generated polynomials are involved in the operation, which affects the error correction effect, so we must pay attention to the selection of the generating polynomials [10]. The generating polynomial for CRC-16 is $x^{16}+x^{12}+x^5+1$. The generating polynomial for CRC-5 is $x^5+x^3+1$. The process of generating the cyclic code for CRC-16 is as follows:

• The reader firstly sets the register in the CRC module to FFFFh.
• The data to be encoded is input serially, with 8 bits of data, one at a time.
• There is an exclusive OR between the input data and the lower 8 bits of the CRC register preset value, and then the resulting value is stored in the CRC register.
• The register is shifted one bit to the right, the highest bit is filled with zero, the lowest bit is shifted out of the register to be judged.
• If the LSB data is 0, then repeat step 4. If the data is 1, then there is an exclusive OR between the value of the register and the polynomial. The polynomial is expressed in binary as 10001000000100001.
• If the 8-bit data is processed completely, repeat steps 2, 3, 4 and 5 until no data is input.
• The last remaining value in the register is the CRC-16 check code.

After generating the check code, the reader adds the check code to the end of the serial data to be sent, and the TPP coding module encodes the serial data to form the baseband signal. The baseband signal is modulated and then sent to the tag. When the tag receives the signal and starts to demodulate, the tag decodes the baseband signal and subsequently sends the decoded data to the CRC check module. The CRC check module in the tag repeats the steps of the reader to generate a new check code. The new check code is compared to the code sent by the reader to judge whether the integrity and correctness of the data transmission were corrupted in the transmission process. The process of generating a circular check code by CRC-16 is illustrated in Figure 6.

3.2.4. The FM0 Encoding Module

The data encoding format for tag reverse link transmission is either FM0 encoding or Miller encoding, depending on the M value in the query command. Figure 7 illustrates the FM0 coding.

FM0 coding works by using electrical level changes to represent binary logic within a duration window of one bit [11]. FM0 inverts the baseband phase at every symbol boundary; data-0 has an additional phase inversion in the middle of the symbol [12]. The format of the leading code of FM0 is also shown in Figure 7.

The FM0 encoding starts with the leading code, and the leading code format selection depends on the value of TRext. The FM0 encoding rule is that any two adjacent data must have their electrical levels reversed [13]. This means that the start boundary electrical level of the latter data must be reversed compared to the end boundary level of the previous data. The FM0 encoding has memory functions [14]. During data processing, the electrical level of the next bit has to be the opposite of the end electrical level of the previous bit, so registers are needed to record the end level of the previous bit and thus to determine the start electrical level of the next bit [14]. The data sending frequency of the reverse link is related to the command sent to the tag by the reader, and after the reader determines the reverse link data sending frequency, the required frequency is generated by the clock circuit inside the tag and used as the frequency of the data transmitted by the tag. Since the energy of the ultra-high frequency passive tag comes from the reader, the tag power consumption must be reduced; therefore, it is necessary to consider the method of frequency division to reduce the power consumption. A clock of 1.28 MHz is sufficient for FM0/Miller coding module [15], but in [16], they show that the minimum clock frequency in the detection of pre-synchronous code/frame synchronous code is 1.92 MHz. Therefore, the system clock can be designed as 2.56 MHz so that the clock of the coding module can be obtained by dividing the system clock. In addition, since tag decoding circuits and encoding circuits cannot be used at the same time, the power management module can be used to turn off useless modules not currently operating in the tag. All of the above methods can reduce the power consumption of the tag.

3.2.5. Initialization Module

The main function of the initialization module is to judge the state of the digital baseband and activate the random number generation module if the digital baseband is in the non-activated state. The flow chart of initialization is shown in Figure 8. When the passive tag is close to the reader, the analog RF front-end circuit of the tag generates a stable voltage for the digital baseband circuit to work normally; the power management module sends an enable signal to the initialization module so that the initialization module starts to work. The memory is first accessed by the state machine with the memory control module. The storage area in the memory is divided into the tag information area, encoding area, security area and user area. The initialization status of the tag, the inactivation status of the tag and the lock status of other areas in the memory are judged by reading the data stored in the tag information area and the status flags of the tag in the memory. First, the tag initialization information is read; if it has been successfully completed, then the initialization ends. Conversely, if initialization has not been successfully completed, the inactivation flag reading is continued. If the inactivation flag is equal to one, then the tag is in the inactivation state, the digital baseband will not respond to the command sent by the reader, and the initialization is completed. Under the condition that the tag inactivation flag is zero, the data in the tag information area is read in order to make a timely response to the reader’s command. After the data in the tag information area is read, the initialization is completed, the work completion signal is sent to the power management module, and the power management module stops supplying power to the initialization module. After the initialization of the tag is completed, the tag is marked for the reader to interact. At this time, the protocol DDS-BT anti-collision algorithm needs the state machine, the time slot calculator and the random number generation module to cooperate together.

4. Results and Discussion

In this paper, the RTL-level code simulation of the passive UHF digital baseband processor is carried out using Verilog design language. The tag-reader communication simulation was also completed. Figure 9 shows the decoding process of the tag to reader command. The data_dem is a TPP encoded signal which is the command from the reader. The data_dec is the binary data after the command has been decoded. The cmd_crc is a CRC check code sent by the reader, which is used to verify whether the error occurs during the transmission of information. Figure 10 shows the whole process of communication between reader and tag. The data_dem is the command sent from the reader to tag, which makes the tag return information to the reader. The MTP_READ enables a signal to the memory, which enables the memory to transfer data to the digital processor. Then, the MTP_READY signal is sent by the memory to the digital baseband processor to ask whether it is ready to transmit or not. If both the digital baseband processor and the memory are ready for data transfer, the digital baseband processor reads data from the memory, and the match_flag is pulled high after the transfer is completed to indicate that the data transfer between the memory and the digital baseband has been completed. The DOUT_D is the information in the memory. The dout is the baseband signal that the tag returns to the reader, which will be sent to the analog front end of the tag for modulation, and then the modulated signal will be sent to the reader through the antenna; thus, completing the communication behavior between the reader and the tag. Figure 11 shows the tag, which includes the antenna, analog front-end and digital baseband processor. Figure 12 shows the results of the write sensitivity tests performed on the tags. Figure 13 shows the test results of the activation sensitivity of the tag. The above two tests were conducted at minimum power. The write sensitivity of the tag is –16.2 dbm, and the activation sensitivity of the tag is –16.1 dbm. The test results meet the protocol requirements. After the above verification, the test results show that the tag digital baseband processor can work properly, and the tag digital baseband meets the requirements of the GJB7377.1 protocol. Finally, on the basis of meeting the protocol and function implementation, how to reduce the power consumption of the digital baseband processor will be the next research topic.

5. Conclusions

In this paper, the design of a passive UHF digital baseband processor is completed in accordance with the Chinese Military Standard GJB7377.1 Protocol, using Verilog hardware description language and related EDA design tools, which can be applied to the digital processor of UHF RFID. The structure of the tag and the structure of the digital baseband processor are analyzed and designed. The simulation in the paper verifies that the results are fully compliant with the protocol, and the logic synthesis can also get the expected results. At present, the tags have been taped out using the TSMC 0.18 um CMOS process and have achieved small-scale mass production. The actual test of the reader shows that the tag fully meets the design requirements.