1. Introduction
In the past a few decades, the downsizing of metal oxide semiconductor field effect transistors (MOSFETs) has not only increased the number of transistors in integrated circuits (ICs), but also improved their performance such as high-frequency performance [
1]. To address these scaling-down issues of MOSFETs, MOSFET structures were evolved over the years, and different types of Multi-Gate FETS (MuGFETs) have been proposed [
2]. However, the downsizing of transistors has caused an ever-increasing power density in ICs. In addition, process-induced random variation (RV) reduced yield efficiency. Therefore, the effective control on the RV has become a major issue when designing and integrating transistors in ICs. Based on previous studies, it is known that there are three root-causes in process-induced RV, namely, line edge roughness (LER) [
3], random dopant fluctuation (RDF) [
4], and work function variation (WFV) [
5].
As a promising device solution, negative capacitance FETs (NCFETs) have been proposed as one of the next-generation low-power devices. Compared to the baseline FET, the ferroelectric-gated NCFET shows an enhanced output drain current at the same supply voltage, because of the amplified internal voltage (which primarily originates from the polarization switching in ferroelectric material) [
6,
7,
8]. In addition, using NC, i.e., using ferroelectric layer in a gate stack, allows for the subthreshold slope of FET to be reduced to lower than the theoretical limit of 60 mV/decade [
4]. Various dopants that are doped in hafnium-based ferroelectric materials, such as Al (HAO), Zr (HZO), and Si (HSO), are studied for NCFETs. Particularly, HAO shows stable ferroelectricity in a wide range of thermal processes (e.g., 500–1000 °C) [
9].
Moreover, the junctionless (JL) doping profile, which is a constant doping profile along the source-channel-drain direction in MOSFET, is a promising fabrication scheme, in terms of scaling issues because of its various advantages. In recent years, the channel length has been scaled down less than 20 nm, requiring very high doping concentrations. However, by the statistical characteristics of the distribution of dopants and the law of diffusion, this has become a very difficult challenge for the semiconductor manufacturing process. The JL doping profile is not only less sensitive to the thermal budget, but it can also simplify the ion implantation process, compared to conventional MOSFETs with different doping profiles. In addition, JL-nanowire FETs (JW-NWFETs) is known to have extremely low leakage current and close-to-ideal subthreshold slope, and the degradation of mobility is less than that of nanowire with junction [
10].
In this study, the impact of negative capacitance on junctionless nanowire FETs (NC-JL-NWFETs) has been studied with various process-induced variations, such as work function variation (WFV), random dopant fluctuation (RDF), and line edge roughness (LER). The impact of each variation type on baseline JL-NWFETs and NC-JL-NWFETs are compared and discussed. The impact from all the variation sources (i.e., integrated types (WFV, RDF, and LER combined)) are also investigated. The MATLAB and Sentaurus TCAD tools were used together for the simulation in this study. This combined simulation method/approach (vs. TCAD-only simulation method) significantly saved on the simulation running time.
2. Simulation of the NC-JL-NWFET and Process-Induced Variations
Figure 1a,b show the bird’s-eye view and equivalent capacitive model of the metal-ferroelectric-insulator-silicon (MFIS)-structured NC-JL-NWFET used in this study. The device was designed according to the International Roadmap for Devices and Systems (IRDS) [
11].
Table 1 lists the device parameters.
For the simulation of ferroelectric behavior in the NC-JL-NWFET, the Landau–Khalatnikov (LK) model is adopted to determine the voltage drop across the ferroelectric layer. The ferroelectric parameters for LK model are extracted from experimentally fabricated HAO-based MFM (Metal–Ferroelectric–Metal) capacitor. The LK parameters are determined as follows from Polarization–Electric field curve, shown in
Figure 1c:
The LK parameters are calculated from the remnant polarization (P
r) and coercive field (E
c) of the Aluminum-doped Hafnium (HAO)-based ferroelectric, where α (=−1.226 × 10
11 cm/F) and β (=2.394 × 10
20 cm
5/C
2F) are defined for P
r = 16 µC/cm
2 and E
c = 1.51 MV/cm. In this study, γ is assumed to be zero because the last term in Equation (1) is negligible [
12].
The voltage drop (V
fe) in terms of the charge density (Q
g) is calculated as follows:
where T
fe is 4 nm, and Q
g is extracted from TCAD simulation of the baseline JL-NWFET. Following the derivation of V
fe, the internal voltage (V
int) is derived from MATLAB as follows:
The TCAD values of V
g and MATLAB-extracted values of V
int are simulated, and the drain current (I
d) of the NC-JL-NWFET is derived from TCAD. This simulation process is described in the flow chart shown in
Figure 2.
The process-induced variations, i.e., WFV, RDF, and LER, were simulated using the TCAD tool. The variation parameters were set in the TCAD simulation and implemented for the baseline JL-NWFET simulation. To analyze the fluctuation induced by WFV and RDF, a simulation was conducted with a function embedded in TCAD [
13]. TiN was used as the metal gate and the grain orientation was considered as the corresponding probability (i.e., orientation <100>: workfunction = 4.6 eV as probability = 60%, orientation <111>: workfunction = 4.4 eV as probability = 40%). The average metal grain size was 4 nm. To investigate the LER-induced variation, the roughness patterns on the channel were generated based on the quasi-atomistic model with the 2D autocorrelation function (ACF) method using TCAD (Sentaurus) and MATLAB [
14]. The RMS amplitude σ = 0.5 nm,
X-axis correlation length ξ
x = 20 nm,
Y-axis correlation length ξ
y = 50 nm, and roughness exponent α = 1 [
15] were the design parameters used in this study. The extent of fluctuations induced by WFV, RDF, and LER were investigated in terms of the variation parameters. The RDF values implemented and integrated were controlled by applying the NC.
3. Results and Discussion
3.1. Work Function Variation (WFV)
The overall performance of the device with WFV is improved when the NC was applied.
Figure 3 shows the I
ds−V
gs curves for the n-/p-type JL-NWFET and NC-JL-NWFET in both linear and saturation modes.
Table 2 summarizes the device performance of the JL-NWFET implemented with WFV and with/without NC in the two modes (linear and saturation).
First, in the linear mode, the mean of the log scaled-on/off ratio for the n-type is increased from 8.01 without NC to 9.05 with NC. The p-type also experienced an increase from 11.03 without NC to 12.01 with NC. The mean of SS is decreased from 63.68 without NC to 61.24 with NC and from 63.82 without NC to 61.58 with NC for the n-type and p-type, respectively. The increase in the on/off ratio and decrease in SS indicates that the device performance of the JL-NWFET is improved by the NC effect. Although the device performance is improved, not all variations were improved. Vt and the on/off ratio show the decreased CV (that is, Vt: from 0.395 to 0.179 (n-type), from 0.062 to 0.052 (p-type); on/off ratio: from 0.0335 to 0.0298 (n-type), from 0.0201 to 0.0165 (p-type)). However, the mean of SS is reduced, but the standard deviation (Std) of SS is increased, indicating that the coefficient of variation is increased.
The overall performance was improved when NC was applied in the saturation mode (that is, the mean of on/off: from 8.413 to 9.510 (n-type), from 11.234 to 12.176 (p-type); the mean of SS: from 62.983 to 61.026 (n-type), from 63.184 to 61.360 (p-type)), and the variation caused by WFV was reduced (that is, the CV of Vt: from 0.586 to 0.195 (n-type), from 0.067 to 0.053 (p-type); the CV of the on/off ratio: from 0.0305 to 0.0265 (n-type), from 0.018 to 0.015 (p-type)).
3.2. Random Dopant Fluctuation (RDF)
Figure 4 shows the n-/p-type I
ds−V
gs of the JL-NWFET and NC-JL-NWFET in both linear and saturation modes;
Table 3 shows the device performance of the RDF-implanted JL-NWFET with/without NC in the linear/saturation mode. The mean on/off ratio (log scale) is increased from 7.814 without NC to 8.852 with NC and from 10.86 without NC to 11.828 with NC for n-type and p-type, respectively. The mean of SS is decreased from 61.042 without NC to 61.668 with NC (n-type) and from 63.99 without NC to 61.84 with NC (p-type) in the linear mode. In the saturation mode, the mean on/off ratio and SS is increased when NC was applied. This change indicates that the performance of the NC-JL-NWFET was enhanced compared to that of the baseline JL-NWNFET.
In terms of variation, NC effectively controlled the fluctuation induced by the RDF in the JL-NWFET. The coefficient of Vt variation, on/off ratio, and SS is decreased with NC. In the case of n-type device, the coefficient of Vt variation, on/off ratio, and SS is decreased by approximately 69%, 28%, and 22% in linear mode and 81%, 28%, and 7% in saturation mode, respectively. For the p-type device, the coefficients of variation in the three profiles are decreased by 33%, 30%, and 24% in linear mode and by 35%, 32%, and 20% in saturation mode, respectively.
3.3. Line Edge Roughness (LER)
Figure 5 shows the n-/p-type I
ds−V
gs of the JL-NWFET and NC-JL-NWFET in both the linear and saturation modes. Notably, the average values of both V
tsat and V
tlin are increased for the NC-JL-NWFET (see
Table 4). This is because the capacitance-boost effect of NC is the strongest when the applied electric field is near 0 [
16], which acts in a way that suppresses the leakage current in the subthreshold region. The on-state current is also improved (increased) but not as much as the leakage current improvement (decreased). In other words, the on/off ratio is improved. For the linear mode operation, values 8.032 to 9.131, and from 11.108 to 12.107, were yielded for n-type and p-type, respectively; for the saturation mode, these values were from 8.456 to 9.608 and from 11.298 to 12.265 for n-type and p-type, respectively. SS is also improved from 63.553 to 61.046 and from 63.627 to 61.377 for n-type and p-type, respectively.
With respect to variation, it can be denoted that NC can successfully suppress the impact of LER-induced variation in nanowire FETs. For V
tlin, σ/μ (coefficient of variation (CV)) is decreased dramatically from 1.0304 to 0.3023 and from 0.1161 to 0.0764 for n-type and p-type nanowire FETs, respectively. A similar tendency was observed for V
tsat. The value of σ/μ is decreased from 0.5573 to 0.2058 and from 0.095 to 0.064, respectively. The improvement was more pronounced in n-type FETs than in p-type FETs. Regarding other parameters, such as the on/off ratio and SS, their improvements are summarized in
Table 4.
3.4. Integrated Process Induced Variation
We were able to confirm that the mean threshold voltage in two modes (i.e., Vtlin and Vtsat) would increase when NC was applied, which we identified in the previous process. The on/off ratio and SS are also exhibiting the improved performance when NC was applied.
Figure 6 shows the n-/p-type I
ds−V
gs curves of the JL-NWFET and NC-JL-NWFET in both the linear and saturation modes.
Table 5 shows the three performance profiles of the JL-NWFET when NC was applied and not applied in both the linear and saturation modes. The NC-applied JL-NWFET shows a more successfully controlled process-induced random variation than the baseline JL-NWFET without NC. In particular, for V
t, in n-type, the coefficient of variation (CV) is decreased by 65% (from 1.321 to 0.452) in the linear mode, and 80% (from 2.780 to 0.563) in the saturation mode. Also,
Figure 7 and
Figure 8 show how much improved the RDF-induced variation was controlled by NC, compared to the other process-induced LER/WFV. In addition, although the variation in SS was induced only by WFV, it was not properly controlled, and the variation in the on/off ratio and SS, induced by process-induced random variation, was successfully controlled by NC.
When the negative capacitance effect was applied, it was possible to reduce the process-induced variation in both the linear and saturation modes, as shown in
Table 6. Overall, the process-induced variation showed, on average, the improvements of 25.17% and 27.46% in the linear and saturation modes, respectively. The better resistance to variation is due to the larger gate capacitance of the NC-JL-NWFET, which allows the device to be more tolerant to variation, resulting in a decreased variation in the surface potential of the device. This makes the NC-JL-NWFET exhibit improved performance with respect to process-induced random variations, compared to the baseline of JL-NWFET.
4. Conclusions
In this study, we investigated the impact of process-induced variations on the JL-NWFET and NC-JL-NWFET for each n-/p-type and lin/sat mode. The results show that the voltage amplification of the NC effect enhanced the overall device performance (i.e., SS, on/off ratio, and Vt) in both the linear and saturation modes. In addition, the decreased coefficient values imply that the ferroelectric layer-made devices are more resistant to process-induced variations. This improvement in device performance is described in terms of variation parameters, such as the mean, standard deviation, and mean/deviation.