A Sub-6G SP32T Single-Chip Switch with Nanosecond Switching Speed for 5G Applications in 0.25 μm GaAs Technology

Abstract

This paper presents a single-pole 32-throw (SP32T) switch with an operating frequency of up to 6 GHz for 5G communication applications. Compared to the traditional SP32T module implemented by the waveguide package with large volume and power, the proposed switch can significantly simplify the system with a smaller size and light weight. The proposed SP32T scheme utilizing tree structure can dramatically reduce the dc power and enhance isolation between different output ports, which makes it suitable for low-power 5G communication. A design methodology of a novel transmission (ABCD) matrix is proposed to optimize the switch, which can achieve low insertion loss and high isolation simultaneously. The average insertion loss and the isolations are 1.5 and 35 dB at 6 GHz operating frequency, respectively. The switch exhibits the measured input return loss which is better than 10 dB at 6 GHz. The 1 dB input compression point of SP32T is 15 dBm. The prototype is designed in 5 V 0.25 μm GaAs technology and occupies a small area of 12 mm².

1. Introduction

To meet the increasing requirements of spectrum efficiency and energy efficiency, and break through the limitations of the cellular system, 5^th generation (5G) communication technology has been proposed and widely used all over the world. The key technologies of the 5G system include large-scale multiple-input multiple-output (MIMO) [1]. The MIMO scheme improves the system’s spectral efficiency from the perspective of space utilization. Large-scale MIMO has become the crucial technology of the 5G system due to its excellent performance advantages, such as the improved number of cell service users, system spectrum efficiency, user experience rate and energy consumption [2]. Further, MIMO can use the large-scale antenna array at the base station (including dozens or even hundreds of array elements) to significantly improve the spatial resolution, and form a narrow beam pointing accurately. It can reduce the interference between users, serve multiple users with very small power consumption at the same time, and effectively improve the spectral efficiency of the system.

Digital beamforming (DBF) is a highly flexible forming method. The transceiver realizes the beamforming and direction adjustment by changing the weight of the digital channel. Each channel has a radio frequency chain, a high-speed analog-to-digital converter (ADC), and a digital-to-analog converter (DAC), and shows high capacity and flexibility. However, there are hardware limitations as follows:

(1) It is difficult to realize the power amplifier (PA) and the low-noise amplifier (LNA) [3,4]. Power amplifiers and other modules are directly behind the antenna elements, while the spacing of high-frequency antenna elements is very small and the space limit is very limited, which makes it very difficult to configure an RF chain for each antenna element.

(2) Power consumption limit. The power amplifier, the ADC/DAC, and other front-end modules are high-energy-consuming modules. Parallel multiple RF chains can greatly increase the power consumption of the system.

For an analog beamforming system, feeding on different input ports can form different amplitude and phase distributions among antenna elements, thus generating beams with different angles [5]. The Butler matrix is the most widely used structure in analog beamforming systems [6,7]. The structure block diagram of the single-pole multi-throw (SPMT) switch used in an analog beamforming system with a Butler matrix is shown in Figure 1. This kind of system can connect multiple antennas to one RF chain at the same time, which is very suitable for a large-scale MIMO system with a large number of antennas. It can significantly reduce the hardware cost of the system and has low computational complexity. Thus, a single-pole multi-throw switch is needed. The conventional single-pole 32-throw (SP32T) switch integrates 32 single-pole throw switches into the waveguide modules which makes the system too bulky and costly for the largely-amount applications.

To develop a large-array system, it is a good choice to integrate lots of the switches into one chip with more outputs. Currently, the implementation of the switch has some generic approaches. The first approach is using Micro-Electro-Mechanical systems (MEMS) with low loss and high isolation [8,9,10,11,12,13], but it is difficult to realize mass production. There are few commercial products on the market, ADI and Menlo Micro have a few SPDT or SP4T products [14,15]. The second approach is using a phase-change materials (PCMs) switch, which demonstrates a relatively higher cut-off frequency (FCO) and surpasses state-of-the-art semiconductor RF switches [16,17,18,19,20,21].

The third approach is using switch circuits by the chip in which two states are designed. It has low ON-state resistance and small OFF-state capacitance based on the bias state of the switch. In order to meet the requirements of a high transmission rate, a 5G communication circuit has a higher working frequency. Additionally, due to the high electron mobility, high saturation drift velocity, and semi-insulating substrate, the GaAs process has better high-frequency performance in high-frequency 5G communication applications, compared with the CMOS process. Moreover, in the huge 5G market, the more mature technology of the GaAs process makes it more cost-effective than the GaN process. The development of the advanced pseudomorphic high electron mobility transistor (pHEMT) has attracted more attention for the high-speed switch design at microwave frequencies due to its low noise and high mobility [22,23].

In this paper, a wideband series-shunt-based switch is proposed for 5G applications. The previously-reported single-pole double-throw (SP2T) switch is based on the series-shunt scheme, which gives an isolation of approximately 30 dB by utilizing the GaAs transistors or GaAs PIN diodes. Yet, most of these switches have low integration with limited bandwidth and are difficult to utilize for large-array systems. These designs do not provide enough large-wideband designs. Therefore, this paper proposes a fully integrated SP32T switch with low insertion loss, high isolation, good linearity and high switching speed.

The paper is organized as follows. Section 2 reviews the GaAs process, then introduces the modeling of the transistors and passive devices. Section 3 discusses the proposed design methodology of the switch with transmission (ABCD) matrix methods. Measurement results will be presented in Section 4, and conclusions are drawn in Section 5.

2. Overview of GaAs Process and the Modeling of the Active and Passive Devices

2.1. The 250 nm Phemt Technology

The proposed S32PT switch is fabricated on the 250 nm GaAs technology, as shown in Figure 2a. This process can implement a D/E-mode transistor by different implanting. Figure 2a illustrates a cross-section layer stack. The length of the gates is defined by the electron beam lithography. The process has two metal layers to realize the basic connections. The transmission lines and power lines in this design stack, MET1 and MET2, form into a thick metal layer with a high quality factor and low resistance.

The layers stacking is shown in Figure 2a. The different metal layers are connected by the vertical VIA. The wafer is passivized with a 200 nm-thick SiN layer, which acts as the dielectric layer of the metal–insulator–metal capacitors. After finishing the front-side process, a full back-side process follows, including the wafer thinning to a thickness of 50 μm, through substrate via holes and back-side metallization.

2.2. The Model of the Active Devices

The high-frequency modeling of the pHEMT is crucial for the switch design and the advantages of the accurate modeling are important [24,25,26,27,28]. The model of pHEMT as an equivalent circuit allows the device geometrical dimensions utilized to estimate the RF performances of the switches and theoretical analysis of the switch performance. The design specifications are related to the physical parameters of the device. With the proposed modeling and several design iterations, the optimum performances can be realized finally. To accurately predict and optimize the performance of the switch, the modeling of the GaAs has been developed in Figure 2. Compared to the transistors working in the amplifying state, the transistors work in the ON and OFF state for the switch. When the transistor works in the ON state, the transistor model is resistance and inductance in series, and the inductance is generated by the VIA, while the model in the process library does not consider the inductance of VIA. The ${\mathrm{C}}_{\mathrm{off}}$ of the transistor used in the proposed switch is 11–13 fF when the transistors work in the OFF state and the ${\mathrm{R}}_{\mathrm{on}}$ of the transistor used in the proposed switch is approximately 14.9 Ω when the transistors work in the ON state, and the cut-off frequency is 154 GHz. The control voltage for the gate is well above or below the threshold voltage.

When the gate voltage is set below the threshold, the transistor is utilized by the lumped elements, such as a capacitor with a resistor for representing the GaAs device under a “cold” condition, which considers the capacitive and resistive effects. When the gate voltage is well above the threshold, the GaAs device is completely in a “hot” condition, which mainly considers the resistive effects.

2.3. The EM Simulation of the Passive Device

Passive device modeling is important for the switch design due to the use of these devices for the input/output matching network and inter-stage matching. The manufactory provides some standard modeling of the capacitor, inductors and transmission lines. However, the model cannot meet the needs of customized passive components, such as inductors and transmission lines. The connection lines between the pHEMTs contribute to the inductance and capacitance, whose patterns are determined by the layout of the chip. Thus, it is essential to custom design and model the passive devices for optimum matching among the pHEMTs.

The full-wave 3D electromagnetic High-Frequency Structure Simulator (HFSS) was used to optimize the passive modeling process of the GaAs. The simulation steps are summarized as follows. Firstly, the physical layout layers of the semi-conductance were setup including the metal layers and isolation layer, such as the SiN layer based on the manufactory process, as shown in Figure 3. Secondly, the parameters of these layers are characterized by different parameters, such as thickness and conductance for metal layers and the loss tangent for isolation SiN layers. Thirdly, the reference ground for ports was defined and a custom design pattern was drawn in the HFSS. Finally, extracting the S parameter of the devices can be converted to Z/Y parameters for circuit design.

3. The Design Methodology for the SP32T Switch

This section shows the design methodology for the proposed SP32T switch that can be utilized for a highly parallelized and sub-6 GHz communications system.

3.1. The System Design Requirement and Structure Analysis

Figure 4 describes the structure of the analog beamforming system which includes the SP32T switch. A heterodyne structure is selected with sub-6 GHz frequency. An intermediate frequency after down-mixing is around in the range of 10 MHz. The proposed communication system can share the same RF chains with the proposed switches. The total system power consumption is reduced to that of one chain without sacrificing the RF performance such as output power and noise figure of the transceiver. The strong variations in the RF amplification and time delays can significantly degrade the performance of the system. The other huge benefit of using the proposed structure is that the mismatches induced by the channels are eliminated due to one TRX channel utilized. As a result, these relaxed requirements for the system design help in optimizing the communication system to perform efficiently over a large bandwidth, minimizing the channel mismatches to improve the overall performance. The target applications for the sub-6 GHz SP32T T/R switch are 5G wireless communication and it is constructed by two asymmetric SP16T switches in a back-to-back connection, as shown in Figure 5.

3.2. Transmission (ABCD) Matrix Design Methodology to Optimize the Insertion and Isolation Loss

The SP32T is composed of 16 SP2T and the 2 symmetric SPST switches. The common node of two SPST switches is denoted as Port 1, connecting to the output of the previous stage. The SP2T is a series-shunt structure, differing from the conventional structure which consists of two 50 ohm quarter-wavelength transmission lines. Consider that the impedance transformer is required to transform the low impedance of the OFF-state SPST switch to high impedance, and the IL of the ON-state SPST switch is large. The impedance transformer consumes a large area, leading to higher fabrication costs.

The series-shunt structure occupies small areas that are suitable for the multiple-output switches. To optimize the overall SP32T switch, the SP2T switch should be carefully designed. A design methodology is developed to optimize the insertion loss and return loss of the switch. The ON-state transistor is modeled as a resistance and the OFF-state transistor is modeled as a capacitor serial with an inductor induced by the VIA [29]. The transmission (ABCD) matrix can be expressed as:

$$\left[\begin{array}{cc}{A}_{on}& B_{on}\\ C_{on}& D_{on}\end{array}\right]=\left[\begin{array}{cc}1& R_{on}\\ 0& 1\end{array}\right]$$

(1)

$$\left[\begin{array}{cc}{A}_{off}& B_{off}\\ C_{off}& D_{off}\end{array}\right]=\left[\begin{array}{cc}1& 0\\ Y_{s1}& 1\end{array}\right]$$

(2)

$$Y_{s1}=\frac{j\omega C_{off}}{1-{\omega }^2{L}_{VIA}{C}_{off}}$$

(3)

where $R_{on}$ is the resistor of the ON-state transistor, $C_{off}$ is the capacitor of the OFF-state transistor, and $L_{VIA}$ is the inductor of the VIA. The connection lines between the pHEMTs are modeled as transmission lines (TL) due to the high-frequency effect. The ABCD matrix of the transmission line is given as:

$$\left[\begin{array}{cc}{A}_{TL}& B_{TL}\\ C_{TL}& D_{TL}\end{array}\right]=\left[\begin{array}{cc}cos{\phi }_{TL}& j{Z}_0\sin {\phi }_{TL}\\ j{Y}_0\sin {\phi }_{TL}& cos{\phi }_{TL}\end{array}\right]$$

(4)

where $Y_0$ and $Z_0$ are characteristic transconductance and impedance, respectively. ${\phi }_{TL}$ is the electric length of the transmission line. Based on the ABCD matrix cascading features, the ABCD matrix of the ON-state switch can be expressed as:

$$\left[\begin{array}{cc}{A}_T& B_T\\ C_T& D_T\end{array}\right]=\left[\begin{array}{cc}cos{\phi }_{TL}& j{Z}_0\sin {\phi }_{TL}\\ j{Y}_0\sin {\phi }_{TL}& cos{\phi }_{TL}\end{array}\right]\left[\begin{array}{cc}1& R_{on}\\ 0& 1\end{array}\right]\left[\begin{array}{cc}1& 0\\ Y_{s1}& 1\end{array}\right]$$

(5)

where an element of the matrix can be written as:

$$A_T=cos\left({\phi }_{TL}\right)-\frac{j\omega c\left(R_{on}cos\left({\phi }_{TL}\right)+j{Z}_{0}sin\left({\phi }_{TL}\right)\right)}{{\omega }^2{L}_{via}{C}_{off}-1}$$

(6)

$$B_T=R_{on}cos\left({\phi }_{TL}\right)+j{Z}_{0}sin\left({\phi }_{TL}\right)$$

(7)

$$C_T=j{Y}_{0}sin\left({\phi }_{TL}\right)-\frac{j\omega c\left(cos\left({\phi }_{TL}\right)+j{R}_{on}{Y}_{0}sin\left({\phi }_{TL}\right)\right)}{L_{via}{C}_{off}{\omega }^2-1}$$

(8)

$$D_T=cos\left({\phi }_{TL}\right)+j{R}_{on}{Y}_{0}sin\left({\phi }_{TL}\right)$$

(9)

Based on Equations (6)–(9), $F_T$ can be derived as:

$$\begin{array}{c}{F}_T=A_T+B_T/Z_0+C_T{Z}_0+D_T\\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}=2cos\left({\phi }_{TL}\right)+\frac{R_{on}cos\left({\phi }_{TL}\right)+j{Z}_{0}sin\left({\phi }_{TL}\right)}{Z_0}+j{Y}_{0}sin\left({\phi }_{TL}\right)(Z_0+R_{on})\\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}-\frac{j\omega C_{off}\left[j{Z}_0(R_{on}{Y}_0+1)sin\left({\phi }_{TL}\right)+\left(R_{on}+Z_0\right)cos\left({\phi }_{TL}\right)\right]}{{\omega }^2{L}_{via}{C}_{off}-1}\end{array}$$

(10)

Referring to Equation (10), the insertion loss of the switch in the ON state can be calculated as:

$$I{L}_{21}=-20\log \left|S_{21}\right|=-20\log \left|\frac{2}{F_T}\right|$$

(11)

Equation (11) contains the resistance of the ON-state switch and the capacitor of the OFF-state switch. The electric length of the transmission line also affects its insert loss. By optimizing these parameters, insertion loss can be minimized.

In the OFF mode of the SP2T switch, the gate voltage of the transistor in the signal path is pulled down to low voltage, and the gate voltage of the shunt transistor is pulled up to high control voltage, synchronously. Therefore, the turn-OFF transistor is simply regarded as one OFF-state capacitance serving as a part of the matching network and the turn-ON transistor exhibits a small resistance. Figure 6 shows the small-signal equivalent circuit for the SPDT in the OFF mode. The ABCD matrix between Port 1 and Port 2 can be represented as:

$$\left[\begin{array}{cc}{A}_{TO}& B_{TO}\\ C_{TO}& D_{TO}\end{array}\right]=\left[\begin{array}{cc}cos{\phi }_{TL}& j{Z}_0\sin {\phi }_{TL}\\ j{Y}_{0}sin{\phi }_{TL}& cos{\phi }_{TL}\end{array}\right]\left[\begin{array}{cc}1& 1/j\omega C_{off}\\ 0& 1\end{array}\right]\left[\begin{array}{cc}1& 0\\ Y_{s2}& 1\end{array}\right]$$

(12)

$$Y_{s2}=\frac{1}{R_{on}+j\omega L_{via}}$$

(13)

where the element of the matrix can be given as

$$A_{TO}=cos\left({\phi }_{TL}\right)+\frac{R_{on}cos\left({\phi }_{TL}\right)+j{Z}_{0}sin\left({\phi }_{TL}\right)}{R_{on}+j\omega L_{via}}$$

(14)

$$B_{TO}=R_{on}cos\left({\phi }_{TL}\right)+j{Z}_{0}sin\left({\phi }_{TL}\right)$$

(15)

$$C_{TO}=j{Y}_{0}sin\left({\phi }_{TL}\right)+\frac{cos\left({\phi }_{TL}\right)+j{R}_{on}{Y}_{0}sin\left({\phi }_{TL}\right)}{R_{on}+j\omega L_{via}}$$

(16)

$$C_{TO}=cos\left({\phi }_{TL}\right)+j{R}_{on}{Y}_{0}sin\left({\phi }_{TL}\right)$$

(17)

Considering Equations (14)–(17), $F_{TO}$ can be written as:

$$\begin{array}{c}{F}_{TO}=A_{TO}+B_{TO}/Z_0+C_{TO}{Z}_0+C_{TO}\\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}=2cos\left({\phi }_{TL}\right)+j{Y}_{0}sin\left({\phi }_{TL}\right)\left(Z_0+R_{on}\right)\\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}+\frac{cos\left({\phi }_{TL}\right)\left(Z_0+R_{on}\right)+(R_{on}{Y}_0+1)sin\left({\phi }_{TL}\right)j{Z}_0}{R_{on}+j\omega L_{via}}\\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}+\frac{R_{on}cos\left({\phi }_{TL}\right)+j{Z}_{0}sin\left({\phi }_{TL}\right)}{Z_0}\end{array}$$

(18)

Hence, the isolation of the switch in the OFF state can be derived as:

$${\mathrm{ISO}}_{21}=-20\log \left|S_{21}\right|=-20\log \left|\frac{2}{F_{TO}}\right|$$

(19)

This equation contains the resistance of the ON-state switch and the capacitor of the OFF-state switch. The electric length of the transmission line affects the loss and matching. the isolation can be maximized by optimizing these parameters.

3.3. Transmission (ABCD) Matrix Optimization for the SP32T Switch

Key specifications of the SP2T switch have been conducted and optimized by the ABCD matrix for both the ON/OFF states. With the same design methodology, the total insertion loss and isolation of SP32T can be summarized as:

$$I{L}_{IL}^n={\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{T1}{\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{T2}{\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{T3}{\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{T4}$$

(20)

$$I{L}_{ISO}^n={\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{T1}{\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{T2}{\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{T3}{\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{ISO4}$$

(21)

where the subscript $T1,2,3,4$ of the matrix represents the stages of the SP2T switches in the ON state, and subscript $ISO1,2,3,4$ of the matrix represents the stages of the SP2T switches in the OFF state.

Based on Equations (20) and (21) for the insertion and isolation of SP32T, the optimizing design follows was summarized as follows. Firstly, extract the ON-state resistance and OFF-state capacitance of the pHEMT with the serial inductance of the VIA. Secondly, determine the total width of the pHEMT based on the equation according to the required insertion loss and isolation. Thirdly, optimizing the inter-stage matching based on the total insertion loss and isolation, based on the above process with several time design iterations. The size is shown in Figure 7 with the passive element values of the proposed SPDT switch optimized eventually from the post-layout simulations with ADS. The calculated and optimized active device dimensions are quite close to each other. The calculated values of the passive elements are larger than the optimized values, mainly due to the parasitic capacitor of the layout is not included in the calculation.

3.4. ESD Protection and Switch Speed Design for Control Signals

In this paper, on-chip electrostatic discharge protection (ESD) is implemented to make the chip robust during the application. The basic working principle of ESD is to provide discharging loop when the input signal voltage is a sharp voltage pulse within a short time. On-chip pads of the switch are classified into microwave-frequency pads and low-frequency pads. Since the microwave-frequency pads are more sensitive to the parasitic capacitor of the extra-protection circuit. These pads are connected to the drains of the pHEMTs, and the diodes of the drain can be used to realize the ESD protection.

Compared with the pads connected to the drains of the pHEMTs, the gate is more fragile due to its high impedance and no discharge loop [30]. The ESD protection of the switch is for control pads. Referring to the system requirement, the turn-ON/OFF speed of the switch determines the imaging speed. A large ESD protection circuit will induce large parasitic capacitance to the control pads. Thus, there is a trade-off between ESD protection and switching speed.

The two design steps for the ESD protection are listed as follows. The current protection ability of the ESD was simulated to resize the diode and predict the ESD performance [31,32]. Based on the simulation results, a geometry of diode can be selected, resulting in minimum performance degradation of the ESD-induced circuit. An anti-parallel diode-string ESD protection circuit is chosen in this design. Different ESD device sizes can be stressed by an ESD transient voltage or current generated by the equivalent ESD discharging circuit HBM ESD model for a targeted ESD protection level, as shown in Figure 8. Secondly, the speed of the switch is highly related to the capacitor of the gate. The control voltages must charge and discharge the capacitor to a certain voltage to turn on and off the transistor. The parasitic capacitor on the gate forms a low pass filter characteristic that degrades the high-frequency performance. The turn-ON/OFF speed is a 50 ns requirement for this switch and the total capacitor value of the gate can be determined.

Hence, the co-design of the ESD protection and the switch circuit is essential to optimize both the ESD protection and the operating speed of the switch. The ESD current and voltage simulation were carefully conducted to predict the ESD capability and high-speed switching needed to minimize the parasitic capacitor. After several design iterations, the ESD diode is optimized as an eight-finger diode with a width of 60 μm and the switch speed is 100 MHz.

4. Measurement Results

In this section, the specifications of the single-chip switch were assessed. To reduce the RF power reflections between the amplifiers and switches and avoid the unwanted coupling effects, the input and output impedance-matching networks for the switches are important, and the return loss is set to <10 dB over the 6 GHz frequency range of interest.

4.1. Chip and Package Design for Testing

The proposed SP32T switch was fabricated in a GaAs process for a sub-6 GHz communications system. It achieves a working frequency of up to 6 GHz. Figure 9 shows that the whole chip area including all testing pads is 12 mm² and also shows the printed circuit board (PCB).

Interconnections between the chip and PCB are a key consideration for the package operating at the mm-wave band. In this design, the wire-bonding method is utilized for the chips and PCB connection. The bonding wires perform as an ideal wire connection at low frequencies. However, as the frequency increases, the model of the wire bonds is inductors. To accurately model these inductors, the wire bonds were simulated by the HFSS tool. The switch is bonded to the chip on board (COB) in a cavity for the shortest bonding wires. The bandwidth of the wire bonds is optimized to matching the pad capacitance to 50 ohm transmission lines on PCB.

4.2. Chip and Package Design for Testing

To accurately assess the performance of our chip, a dedicated calibration pattern is designed. The calibration patterns are conducted by including the bonding wires, transmission lines and connectors. These parasitic effects were de-embedded because the same bonding wire structures utilized in the design were fabricated and measured. With several different testing patterns, as shown in Figure 10, the loss of the transmission line, connectors and the bonding wire can be predicted precisely.

Agilent E3631A DC voltage source was used as power supply equipment, and Keysight N5247B vector network analyzer was used to measure the S parameter. The measured input/output return losses are illustrated in Figure 11. The measured input is better than 10 dB from 1 GHz to 6 GHz. The output return loss is also maintaining < −10 dB from 1 GHz to 6 GHz. The measured results are worse than the simulation. The measured return losses verify the proposed SP32T switch topology that can successfully solve the issue of the impedance mismatching induced by the bonding wire.

As shown in Figure 12a, the measured average insertion loss (IL) is 1 dB over the bandwidth of 0–6 GHz. Additionally, the measured isolations between ports are plotted in Figure 12b. The switch achieves the measured average isolation of 35 dB at 5 GHz. There are discrepancies between the simulated and measured performances, which are dominantly due to the inaccuracy of the transistor models. The proposed SP32T switch consumes a much smaller die area and achieves competitive performance.

4.3. Linearity and Switching Speed Measurement

The linearity of the switch is characterized by the input power compressed by 1 dB (P_1dB). Different input powers were utilized to measure the P_1dB, which is approximately 15 dBm, as shown in Figure 13. The input of the single-chip switch is connected to the signal generator (E8257D Keysight) with a frequency of up to 67 GHz and its output is connected to the signal analyzer (N9040B Keysight) with a measurement frequency of up to 50 GHz.

To assess the operating speed of the switch, different input frequencies and switching control signals are performed. Agilent 33250A function/arbitrary waveform generator was used to generate the control signals. Additionally, Keysight E8257D signal generator was used to generate the different input frequencies. The transient measurement switching speed of the proposed SP32T is shown in Figure 14, Figure 15 and Figure 16, when inputting the 10 MHz gate control signal waveform. The period of ON/OFF time for the switch is 50 ns. The transient time transferring from the turn-ON to turn-OFF is very fast at 1 ns, including a coaxial cable propagation delay of 0.5 ns. The measurement results show the proposed switch has ultra-fast speed and is feasible for the sub-6 GHz communications system. Additionally, the spectrum measurements are also utilized to check the isolation when the switch is turn-ON and turn-OFF, as shown in Figure 17. Compared with the switches in

Table 1. Performance Summary and Comparison.

	Technology Node	Switch Type	Frequency (GHz)	Insert Loss (dB)	Isolation (dB)	P1dB (dBm)	Rise Time (ns)	Fall Time (ns)	ON Time (ns)	OFF Time (ns)	Area (mm2)
[33]	NA	SPDT	0.612–1.088	2.8–2.3	>41.4	17.3–25.4	NA	NA	NA	NA	NA
[34]	250 nm GaAs pHEMT	SPDT	0.01–6	<0.9	>35	NA	NA	NA	NA	NA	1.36 × 1.4
[35]	150 nm GaAs pHEMT	SPDT	1.9–2.6	<1	>24.7	17.5	NA	NA	NA	NA	0.9 × 1.9
[36]	InGaAs PHEMT	SPST	0–6	<1.6	>82	19@1.95 GHz	1.4	1.6	8.8	NA	1.1 × 1.0
[37]	65 nm CMOS	SPDT	2.35–2.55	0.8	28	29	NA	NA	NA	NA	0.2
This work	250 nm GaAs pHEMT	SP32T	0.5–6	<2	>30@6 GHz	15	1	1	50	50	3 × 4

, the proposed chip can achieve low loss with 32 outputs. In the future, the chip area of the proposed switch can be reduced by optimizing the channel layout and transmission line structure.

5. Conclusions

This paper reports a highly integrated SP32T switch fabricated in a 0.25 μm GaAs process. The proposed SP32T single-chip switch consumes ultra-low power and occupies a smaller core area of 12 mm² including all the testing pads. Additionally, this paper proposes a design methodology for optimizing our SP32T switch and shows good agreement with the measured results. Thus, the switch design methodology facilitates the design of the mm-wave switches and can be applied to other semiconductor technologies and switch topologies. Compared to the SP32T switch that is implemented by the waveguide module, the proposed switch shows low-power consumption, high integration, and better consistency between different channels. The measured performance at 6 GHz exhibits an average IL of 1.5 dB, an average isolation of 35 dB, an input/output return losses better than 10 dB, and a switch speed of 50 ns, respectively.