ASAD-RD: Accuracy Scalable Approximate Divider Based on Restoring Division for Energy Efficiency
Round 1
Reviewer 1 Report
The paper presents an energy quality scalable approximate divider called ASAD-RD to improve the energy efficiency of a computing system. This work improves SAADI, a scalable accuracy approximate divider for dynamic energy-quality scaling, and the restoring division algorithm.
The presented results are very important since ASAD-RD improves SAADI, reducing the error and the power consumption, even if the addition of an Adder component in the multiplicative division harware requires more power.
This work reinforces the importance of approximate computin, which is very important in various leading areas of modern research.
Author Response
Response to Reviewer 1 Comments
Thank you very much for all the helpful comments from reviewers. We have revised the manuscript according to the reviewers’ comments and the changes are highlighted in red in the revision.
The paper presents an energy quality scalable approximate divider called ASAD-RD to improve the energy efficiency of a computing system. This work improves SAADI, a scalable accuracy approximate divider for dynamic energy-quality scaling, and the restoring division algorithm.
The presented results are very important since ASAD-RD improves SAADI, reducing the error and the power consumption, even if the addition of an Adder component in the multiplicative division hardware requires more power.
This work reinforces the importance of approximate computing, which is very important in various leading areas of modern research.
Response: Thank you very much for your valuable feedback.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
This paper looks like a subset of the Author's previous work:
"SAADI-EC: A Quality-Configurable Approximate Divider for Energy Efficiency " Melchert, Jackson ; Behroozi, Setareh ; Li, Jingjie ; , IEEE transactions on very large scale integration (VLSI) systems, November 2019, Vol.27(11), pp.2680-2692
It would be great if the Authors specify, what is a new contribution to this paper in comparison to the previous one.
Author Response
Response to Reviewer 2 Comments
Thank you very much for all the helpful comments from reviewers. We have revised the manuscript according to the reviewers’ comments and the changes are highlighted in red in the revision.
This paper looks like a subset of the Author's previous work:
"SAADI-EC: A Quality-Configurable Approximate Divider for Energy Efficiency " Melchert, Jackson ; Behroozi, Setareh ; Li, Jingjie ; , IEEE transactions on very large scale integration (VLSI) systems, November 2019, Vol.27(11), pp.2680-2692
It would be great if the Authors specify, what is a new contribution to this paper in comparison to the previous one.
Response: Thank you very much for your valuable feedback. We have revised the Introduction Section to specify the main contribution of the paper. This paper is not a subset of the previous manuscript. Unlike the previous paper, this study proposes a hybrid method of SAADI and other division algorithm for improving accuracy. As a result, the proposed design provides benefit in power consumption and latency due to fewer iterations or lower error rate for the same iteration. In addition, new Related Works Section is added to compare with other designs.
We added following sentences in the Introduction Section and Comparison and Analysis Section to specify main contributions of the manuscript.
“Compared with SAADI [1], ASAD-RD is based on a novel idea. It is a hybrid method of SAADI and other division algorithms for improving the accuracy and reducing the repetition process of the approximate division.”
“In the process of approximate division, a restoring division is performed at the beginning of SAADI to reduce the occurrence of truncation errors in the multiplicative division.”
“As a result, the proposed design can meet more stringent accuracy requirements that cannot be reached by SAADI, and can benefit from power or performance.”
“As a result, with the same parameters, the maximum accuracy of the ASAD-RD is not only higher than that of the previous design, but also the number of iterations for maximum accuracy is also lower. Lower iterations save power, and the amount saved is greater than the additional power consumption due to additional hardware. Therefore, ASAD-RD has advantages over SAADI in power or performance.”
Author Response File: Author Response.pdf
Reviewer 3 Report
Considering the current technology, reduced numeric representation (such as bfloat16) can be used to reduce storage and increase the execution speed of machine learning algorithms. Approximate computing could be an interesting approach in this field.
The authors should revise the following issues in their work:
1.-Motivation and novelty of the paper should be deeply improved.
2.-Introduction is extremely synthetic and more similar to the abstract. Please introduce better the problem, the motivation and the solution presented.
3.-Related work should be included.
4.-The authors should identify the real use of the proposed divider (inside the ALU in a CPU?, or in a massive computation device?) What is the real impact in global consumption?
5.-This model should be compared with other divisors (complexity and resources needed, consumption, speed…).
6.-Current devices require high speed, so multi-cycle operations reduce the real impact of the proposed algorithm.
7.-Comparison and Analysis Section have to be articulated.
8.-Bibliography should be revised: Only 2 Journal (1958,1997). The rest are conferences, symposiums and a web page.
Consider other implementations, such as:
Chen and M. Ikeda, "Design and Implementation of Low-Power Hardware Architecture With Single-Cycle Divider for On-Line Clustering Algorithm," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 8, pp. 2165-2176, Aug. 2013, doi: 10.1109/TCSI.2013.2239098.
Author Response
Response to Reviewer 3 Comments
Thank you very much for all the helpful comments from reviewers. We have revised the manuscript according to the reviewers’ comments and the changes are highlighted in red in the revision.
Considering the current technology, reduced numeric representation (such as bfloat16) can be used to reduce storage and increase the execution speed of machine learning algorithms. Approximate computing could be an interesting approach in this field.
Response: Thank you very much for your valuable feedback.
The authors should revise the following issues in their work:
1.-Motivation and novelty of the paper should be deeply improved.
Response: Thank you very much for your valuable feedback. Following sentences are added in the Introduction Section to address the motivation and novelty of the paper. For motivation, new Related Works Section is added in the revision.
“So far, many approximate computing designs have been presented, and these designs have been proven to benefit from performance improvement and power savings by causing minor errors. Also, many approximate divider designs have been proposed [9], [10], [11], [12]. However, previously proposed approximation dividers do not meet the applications’ various accuracy requirements and are limited in that they provide only a single level of accuracy. In addition, the accuracy requirement for arithmetic operations is not constant because the impact of approximation to the final quality at the application level is highly input-dependent [13] and the application-level quality requirements may also change over time. Therefore, in order to meet the quality requirements of the application, an approximate divider is required that enables dynamic quality scaling.”
“Compared with SAADI [1], ASAD-RD is based on a novel idea. It is a hybrid method of SAADI and other division algorithms for improving the accuracy and reducing the repetition process of the approximate division.”
“In the process of approximate division, a restoring division is performed at the beginning of SAADI to reduce the occurrence of truncation errors in the multiplicative division.”
“As a result, the proposed design can meet more stringent accuracy requirements that cannot be reached by SAADI, and can benefit from power or performance.”
2.-Introduction is extremely synthetic and more similar to the abstract. Please introduce better the problem, the motivation and the solution presented.
Response: Thank you very much for your valuable feedback. Following sentences are added and modified in the Introduction to specify the problem and present the motivation and the solutions as well. New Related Works Section is added in the revision.
“However, previously proposed approximation dividers do not meet the applications’ various accuracy requirements and are limited in that they provide only a single level of accuracy.
In addition, the accuracy requirement for arithmetic operations is not constant because the impact of approximation to the final quality at the application level is highly input-dependent [13] and the application-level quality requirements may also change over time.
Therefore, in order to meet the quality requirements of the application, an approximate divider is required that enables dynamic quality scaling.”
“Energy-efficient arithmetic operations have long been a challenge for researchers to derive better performance from limited resources in computer systems.”
“Compared with SAADI [1], ASAD-RD is based on a novel idea. It is a hybrid method of SAADI and other division algorithms for improving the accuracy and reducing the repetition process of the approximate division.”
In the process of approximate division, a restoring division is performed at the beginning of SAADI to reduce the occurrence of truncation errors in the multiplicative division.
As a result, the proposed design can meet more stringent accuracy requirements that cannot be reached by SAADI, and can benefit from power or performance.”
3.-Related work should be included.
Response: Thank you very much for your valuable feedback. We have added the Related work Section after Introduction to explain the properties and limitations of the related works such as other approximate dividers and SAADI including the paper you have suggested at the bottom.
4.-The authors should identify the real use of the proposed divider (inside the ALU in a CPU?, or in a massive computation device?) What is the real impact in global consumption?
Response: Thank you very much for your valuable feedback. In this study, a new structure of approximate divider is proposed and analyzed in the accuracy and power. As you mentioned, system or application-level analysis is required to validate the real benefit or impact of the proposed divider. However, we cannot provide the real use of the proposed divider due to time limitation of the revision. We are applying the proposed divider in the image processing module (i.e., Edge detection) to quantify the benefit of the proposed idea. We believe that we can report the results in the future works.
5.-This model should be compared with other divisors (complexity and resources needed, consumption, speed…).
Response: Thank you very much for your valuable feedback. Comparison among SAADI and other dividers were well compared in the reference [1]. Therefore, we only provide the comparison of the proposed idea with original SAAD algorithm. Besides, all the previous dividers before SADDI do not have dynamic scaling of the quality of calculation.
6.-Current devices require high speed, so multi-cycle operations reduce the real impact of the proposed algorithm.
Response: Thank you very much for your valuable feedback. You are right. The benefit will be reduced for high-speed application due to the multi-cycle structure. However, conventional high-speed single cycle dividers cannot meet quality scaling dynamically. Only multi-cycle algorithm as proposed in the paper can change the requested quality (e.g., speed, accuracy, or power) adaptively in runtime. Thus, the proposed divider will be beneficial to applications requiring various conditions and quality in runtime rather than only for high-speed.
7.-Comparison and Analysis Section have to be articulated.
Response: Thank you very much for your valuable feedback. Sorry for the confusion in the Comparison and Analysis Section. For better understanding and specifying the results more clearly, we have added following sentences.
For Figure 4, we have added the following sentences.
“In both dividers, the maximum number of the effective iteration counts for improving accuracy is n-1.”
“Therefore, ASAD-RD can offset the additional latency for maximum accuracy due to the extended hardware for restoring division.”
For Table 2 and the results in Section 4.1, we have added the following sentences.
“As a result, with the same parameters, the maximum accuracy of the ASAD-RD is not only higher than that of the previous design, but also the number of iterations for maximum accuracy is lower.
Lower iterations save power, and the amount saved is greater than the additional power consumption due to additional hardware. Therefore, ASAD-RD has advantages over SAADI in power and performance.”
8.-Bibliography should be revised: Only 2 Journal (1958,1997). The rest are conferences, symposiums and a web page.
Response: Thank you very much for your valuable feedback. As you requested, we have added the following two journals in the revision.
- Consider other implementations, such as:
Chen and M. Ikeda, "Design and Implementation of Low-Power Hardware Architecture With Single-Cycle Divider for On-Line Clustering Algorithm," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 8, pp. 2165-2176, Aug. 2013, doi: 10.1109/TCSI.2013.2239098.
Response: Thank you very much for your valuable feedback. We added the above paper in the reference and analyzed in the Related Works as follows. In the future works, we will implement the design and compare with ours.
“An approximate divider design presented in [14] reduces power consumption and circuit complexity. It is designed with a simple structure consisting of three approximate subtractor cells that leads to performance improvement and power reduction. But, the accuracy is also determined at the design level. Therefore, the requirements of the application cannot be met dynamically.”
Author Response File: Author Response.pdf
Round 2
Reviewer 1 Report
I already appreciated this work.
Author Response
Response to Reviewer 1 Comments
Thank you very much for all the helpful comments from reviewers. We have revised the manuscript according to the reviewers’ comments and the changes are highlighted in red in the revision.
I already appreciated this work.
Response: Thank you very much for your valuable feedback.
Author Response File: Author Response.pdf
Reviewer 2 Report
My suggestion about the clear presentation of the new contribution was in the context of the paper:
"SAADI-EC: A Quality-Configurable Approximate Divider for Energy Efficiency " Melchert, Jackson ; Behroozi, Setareh ; Li, Jingjie ; , IEEE transactions on very large scale integration (VLSI) systems, November 2019, Vol.27(11), pp.2680-2692.
In your response you refer to another one [1] which is a smaller version of the abovementioned IEEE Trans. paper. However, the final decision belongs to you.
Author Response
Response to Reviewer 2 Comments
Thank you very much for all the helpful comments from reviewers. We have revised the manuscript according to the reviewers’ comments and the changes are highlighted in red in the revision.
My suggestion about the clear presentation of the new contribution was in the context of the paper:
"SAADI-EC: A Quality-Configurable Approximate Divider for Energy Efficiency " Melchert, Jackson ; Behroozi, Setareh ; Li, Jingjie ; , IEEE transactions on very large scale integration (VLSI) systems, November 2019, Vol.27(11), pp.2680-2692.
In your response you refer to another one [1] which is a smaller version of the abovementioned IEEE Trans. paper. However, the final decision belongs to you.
Response: Thank you very much for your valuable feedback. The VLSI Journal paper is also added in Reference [16]. Both [1] and [16] papers are analyzed in the Introduction Section to specify the main contribution of the paper.
For error compensation of SAADI, [16] proposes an idea that the approximate quotient is multiplied by a constant in a LUT indexed by the number of iterations. However, the error compensation after approximation may not be achieved properly due to the truncation caused by the limit of divider width. Therefore, in this study, we propose the idea that the compensation is conducted in the input, not at the truncated output.
Author Response File: Author Response.pdf
Reviewer 3 Report
In this revision, the authors should include a document describing for each point comments and justification of the main aspect of the modifications proposed in the document.
Also, there are some previous issues not amended in this manuscript.
The authors should revise the following elements in their work:
1.-At the end of Section 1, you should describe the structure of your paper. Please, take as example other scientific papers of your bibliography.
2.-Related Works Section is rather synthetic. You should expand it and describe other proposals in detail. You can also include some figures and comparative tables if you need. The use of paragraphs can facilitate the reading of the document.
3.- The authors should identify the real use of the proposed divider (inside the ALU in a CPU? or in a massive computation device?) What is the real impact on global consumption?
4.-This model should be compared with other divisors (complexity and resources needed, consumption, speed…).
5.-Current devices require high speed, so multi-cycle operations reduce the real impact of the proposed algorithm.
8.-Bibliography should be revised. Please, include more journals to increase the global proportion.
Author Response
Response to Reviewer 3 Comments
Thank you very much for all the helpful comments from reviewers. We have revised the manuscript according to the reviewers’ comments and the changes are highlighted in red in the revision.
In this revision, the authors should include a document describing for each point comments and justification of the main aspect of the modifications proposed in the document.
Also, there are some previous issues not amended in this manuscript.
The authors should revise the following elements in their work:
- At the end of Section 1, you should describe the structure of your paper. Please, take as example other scientific papers of your bibliography.
Response: Thank you very much for your valuable feedback. We have described the structure of our paper as follows at the end of Section 1.
The remainder of the paper is organized as follows: Section 2 presents related works and explains the motivations of our study. The proposed approximate divider is introduced in Section 3. It elaborates on the algorithm and architecture with error compensation. Section 4 presents a complete analysis of accuracy and latency and comparison with a conventional scalable accuracy approximate divider (e.g., SAADI) followed by conclusions in Section 5.
- Related Works Section is rather synthetic. You should expand it and describe other proposals in detail. You can also include some figures and comparative tables if you need. The use of paragraphs can facilitate the reading of the document.
Response: Thank you very much for your valuable feedback. Per your comment, we have added Section 4.1 Previous Approximate Dividers with a summary table (Table 2) as follows. Basic methodology and limitations of the previously proposed designs are explained in this subsection.
- The authors should identify the real use of the proposed divider (inside the ALU in a CPU? or in a massive computation device?) What is the real impact on global consumption?
Response: Thank you very much for your valuable feedback. We believe that any arithmetic units, rather than general CPU, in which approximate computation (i.e., division) are allowed can use our proposed idea for better accuracy and reduced power consumption. For example, image processing modules such as JPEG encoder, edge detector can be good candidates for our design.
In this study, a new structure of approximate divider is proposed and analyzed in the accuracy and power. As you mentioned, system or application-level analysis is required to validate the real benefit or impact of the proposed divider. However, we cannot provide the real use of the proposed divider due to time limitation of the revision. We are applying the proposed divider in the image processing module (i.e., Edge detection) to quantify the benefit of the proposed idea. We believe that we can report the results in the future works.
- This model should be compared with other divisors (complexity and resources needed, consumption, speed…).
Response: Thank you very much for your valuable feedback. Comparison with others is included in Related Works and newly added 4.1 Section. However, in this study, we only provide the comparison of the proposed idea with original SAADI algorithm in terms of accuracy and power consumption because all the previous dividers before SADDI do not have dynamic scaling of the quality of calculation.
- Current devices require high speed, so multi-cycle operations reduce the real impact of the proposed algorithm.
Response: Thank you very much for your valuable feedback. You are right. The benefit will be reduced for high-speed application due to the multi-cycle structure. However, conventional high-speed single cycle dividers cannot meet quality scaling dynamically. Only multi-cycle algorithm as proposed in the paper can change the requested quality (e.g., speed, accuracy, or power) adaptively in runtime. In the case of the conventional high-speed single-cycle divider, there is a disadvantage that the application cannot satisfy the quality requirements when the quality requirements change at run time, so quality must be abandoned. To meet these changes, the divider has to be redesigned from the design level. In the case of the multi-cycle divider presented in this paper, it may be insufficient in terms of speed, but it can meet the quality requirements that change dynamically at runtime. In addition, since the accuracy in the minimum cycle (1 cycle) has been greatly improved compared to the previous design (SAADI), it is unlikely that the speed is necessarily inferior to the single-cycle divider. Thus, the proposed divider will be beneficial to applications requiring various conditions and quality in runtime rather than only for high-speed.
- Bibliography should be revised. Please, include more journals to increase the global proportion.
Response: Thank you very much for your valuable feedback. We have added the following three journal papers in the revision ([3], [5], [16]). They are analyzed and explained in Introduction and Related Works Section.
Author Response File: Author Response.pdf
Round 3
Reviewer 3 Report
I appreciate your effort to improve the quality of your manuscript and follow the reviewers’ comments.
Author Response
Response to Reviewer 3 Comments
Thank you very much for all the helpful comments from reviewers. We have revised the manuscript according to the reviewers’ comments and the changes are highlighted in red in the revision.
I appreciate your effort to improve the quality of your manuscript and follow the reviewers’ comments.
Response: Thank you very much for your valuable feedback. Your comments significantly improve the quality of the paper.
Author Response File: Author Response.pdf
