# Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

^{1}

^{2}

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Conventional Nyquist-Rate ADC Architectures

#### 2.1. Flash ADCs

^{N}-1 parallel comparators that are all clocked simultaneously. As an example, Figure 1 shows a conventional 2-bit flash ADC. The reference voltages are generated by a ladder with 2

^{N}resistors having identical values, dividing the full-scale range (V

_{FS}) into 2

^{N}regions. All of the comparators simultaneously compare the input signal with their corresponding reference voltages. If the input voltage is larger than a reference voltage, then the corresponding comparator generates a logic output of 1 (high); otherwise, the logic output is equal to 0 (low). As a result, when monitoring the outputs of the comparators connected between the low and high reference voltages, there will be a series of 1 s transitioning to a series of 0 s. This pattern, which is often referred to as thermometer code, enables determining the quantization level that is closest to the input amplitude. A thermometer-to-binary encoder can generate the final binary output.

#### 2.2. Interpolating and Folding ADCs

_{R1}and V

_{R2}. Interpolating reduces the number of preamplifiers as well as resistors in the reference ladder to half (or less, depending on the interpolation factor) in comparison to a conventional flash ADC; this results in a reduction of the total area and power consumption. However, the number of latched comparators in an interpolating ADC is still the same as in a standard flash ADC with the same resolution. Another benefit of interpolation is its improved linearity due to the averaging and distribution of the errors [38]. In addition, further interpolation levels are possible with extra interpolation resistor ladders between the preamplifiers and latched comparators [39].

#### 2.3. Subranging and Two-Step ADCs

^{L}will relax the offset requirement for the M-bit fine ADC to only M-bit. In practice, the gain, linearity, bandwidth, and offset of the amplifier should also satisfy the N-bit accuracy of the combined ADC to avoid errors in the residue voltage. Moreover, the power consumption of such an amplifier can be significantly high due to the stringent requirements for high resolutions, especially at high conversion rates.

#### 2.4. Pipelined ADCs

#### 2.5. Successive Approximation Register ADCs

_{FS}/2, such that the comparator compares the sampled voltage with the middle reference level, resolving the first MSB. Depending on the comparator’s output after each comparison, the SAR logic sets the DAC input bits to generate the appropriate reference voltage for the next comparison. The process continues until the last bit is resolved. Using a successive approximation algorithm (e.g., binary search algorithm), one output bit is generated during each conversion cycle. Therefore, a minimum of N + 1 clock cycles is required to carry out a full N-bit conversion with a basic SAR ADC.

#### 2.6. Time-Interleaved ADCs

_{s}, a total sampling rate of M × f

_{s}is attainable in theory. Therefore, conversion speeds of several GS/s are achievable with this architecture. In each channel, a sample-and-hold captures the input signal, and the sub-ADC resolves the digital output at a conversion rate of f

_{s}. After combining the channel outputs with a digital multiplexer, the effective ADC output is generated at the rate of M × f

_{s}. Each channel has 1/(M × f

_{s}) seconds of delay compared to its neighboring channels. A time-interleaved ADC can employ several power-efficient ADCs in parallel to achieve the same performance as a flash ADC but with lower power consumption in many applications, which also depends on the characteristics of a given CMOS technology. It is possible to use different types of ADCs (such as SAR, pipelined, and flash ADCs) in a time-interleaved architecture, which has to be determined by the designer under consideration of the specific application and power-efficiency requirements.

#### 2.7. Summary

## 3. Design Considerations for Time-Interleaving and SAR ADCs within Hybrid Architectures

#### 3.1. Channel Offset Mismatch

_{OS}) of each channel in an M-channel TI-ADC. The offset mismatches between each channel cause an error signal with fixed amplitude and periodic pattern in the time domain ADC output [18]. In the frequency domain, the undesired frequency components due to the offset mismatch error of an M-channel TI-ADC occur at:

_{s}is the sampling frequency of the TI-ADC. The SNR degradation due to the offset mismatch is constant and independent of the input frequency and amplitude. The corresponding SNR degradation can to be calculated from the amount of offset mismatch (σ

_{os}). The required standard deviation of the channel offset in an M-channel N-bit TI-ADC can be calculated with the following equation [62]:

#### 3.2. Channel Gain Mismatch

_{in}is the input signal frequency. The SNR degradation due to gain mismatches is independent of the input frequency, but depends on the amplitude of the input signal. The required standard deviation of the channel gain (σ

_{Gain}) in an M-channel N-bit TI ADC can be obtained with [62]:

#### 3.3. Channel Timing Mismatch (Timing Skews)

_{ti}is the deviation of a sampling moment in channel “i” from the ideal value. In the time domain, the largest error occurs when the input signal has the highest slew rate (at the zero crossing for differential sinusoidal input), which is like phase modulation (PM) noise [18]. In the frequency domain, the undesired frequency components due to gain mismatch errors occur at:

#### 3.4. Channel Bandwidth Mismatch

_{c}= 1/(2π∙R∙C), where R and C are the total resistance of the sampling path and total sampling capacitance, respectively [58,63]. As shown in Figure 13, there are differences between the bandwidths of the TI channels, which originate from several sources [59,68]. First, the differences originate from the RC mismatch coming from the MOS switch resistance and the sampling capacitance in each sample-and-hold. Second, they originate from the systematic RC mismatch between the input signal routing among the channels on the chip. Moreover, if a buffer amplifier is used in each S/H [34], the amplifier bandwidth mismatch will also contribute to the TI bandwidth mismatch [68]. The analysis of channel bandwidth mismatches is usually performed by writing the transfer function of the sampling channel to evaluate the impact of bandwidth mismatch on both amplitude and phase [18,68]. The bandwidth mismatch impact on SNR degradation is a combination of gain and phase mismatches, where for low-input frequencies, the impact of the phase errors is dominant [63]. The bandwidth mismatch has nonlinear dependence on both input signal amplitude and frequency [61].

#### 3.5. Sub-ADC Architectures in Time-Interleaved ADCs

#### 3.6. Suitability of SAR ADCs for Low-Power Hybrid ADC Architectures

^{N}·C

_{u}, where N is the number of bits, and C

_{u}is the unit capacitor value. This limits the sampling speed of the ADC, and increases the required area on the chip as the resolution increases. However, this architecture has very good device matching characteristics, which results in high linearity. Another type of SAR ADC has a split-capacitor architecture (segmented DAC), which uses two split capacitor banks connected by an attenuation (bridge) capacitor between them [72]. A SAR ADC with a C-2C ladder DAC is an alternative technique [5]. These two latter architectures have the advantage of reducing the total capacitance in comparison to the conventional binary-weighted CDAC counterpart. However, they are more sensitive to parasitic capacitances, causing considerable nonlinearity errors. In general, they require calibration because of such errors. Most of the state-of-the-art SAR ADCs contain binary-weighted CDACs because achieving higher sampling rates with a small area is possible with these CDACs in modern short-channel technologies, which often necessitates the use of very small custom-designed capacitors (≤1fF) [4,29].

_{s}, an internal clock with a frequency of (N + 1)∙f

_{s}is required. Therefore, the comparator must operate with such a high-speed clock. For every output bit, the comparator decision and DAC settling must be completed in one clock cycle. Thus, (N + 1) clock cycles are required to perform one complete conversion, limiting the overall speed of synchronous SAR ADCs. Several techniques have been proposed to improve the speed of SAR ADCs. An asynchronous SAR algorithm has been introduced in [74], where the triggering of the internal comparisons from MSB to LSB occurs by a ripple-like procedure. Hence, the quantization time allocated to each bit is no longer limited by the slowest conversion bit, but rather is affected by the average conversion time, leading to speed enhancement in comparison to synchronous architectures. Asynchronous architectures have been used frequently in recent designs [26,27,57] to shorten the overall conversion time. While an asynchronous technique helps to achieve higher speeds, it usually requires more complicated digital blocks to generate signals with unequal pulse widths. Converting more than one bit per cycle is another effective way of increasing the conversion speed of a SAR ADC. Several SAR or TI-SAR ADCs with two bits/cycle have been introduced, such as in [3,23,24,25]. They can achieve higher sampling rates because they require a smaller number of cycles compared to a 1 bit/cycle SAR ADC. However, the disadvantages of multi-bit/cycle SAR ADCs are the larger number of comparators, and the more complex DAC structure. In addition, unlike in a 1 bit/cycle architecture, offset calibration is often required for the comparators in multi-bit/cycle SAR ADCs.

#### 3.7. Comparator-Based Asynchronous Binary Search (CABS) ADC

^{N}-1 comparators (as a flash ADC), but only N comparators are activated during a complete conversion. The first comparator is triggered by a clock, while the others are triggered asynchronously by the output of a previous comparator. The CABS architecture combines the advantages of both flash and SAR ADCs to realize high-speed operation with low-power consumption. However, due to its large number of comparators, it has a high input capacitance and occupies a relatively large chip area. A version of the CABS ADC with less comparators is presented in [27], where the total number of comparators has been reduced to 2∙N-1. Nevertheless, the required time for the reference settling and the operation of additional digital gates for each comparison can limit the speed of this reduced architecture.

## 4. Low-Power Hybrid ADC Design

#### 4.1. Power-Efficient High-Speed Medium-Resolution ADCs

#### 4.2. Architecture Case Study

_{SAMP.i}) samples the input signal, and the switch between the SHDAC and flash ADC (controlled by CLK

_{SAMPX.i}) is closed while, the ones in the other channels are opened. The clock signals CLK

_{SAMPX.1}through CLK

_{SAMPX.4}must be non-overlapping in order to avoid changing the charge that is held on the adjacent SHDACs. After the sampling phase is complete, the flash ADC resolves the first three MSBs. Based on the latched thermometer output of the flash ADC at the beginning of the third phase, the SHDAC generates the residue voltage that passes through the unity-gain buffer. Finally, the buffered residue voltage is delivered to the CABS ADC that operates with one-eighth of the full-scale range.

_{flash.comp}= 143 µW and A

_{flash.comp}= 448 µm

^{2}are the power consumption and area of each comparator in the flash ADC, and P

_{CABS.comp}= 48 µW and A

_{CABS.comp}= 504 µm

^{2}are the power consumption and area of each comparator in the CABS ADC, respectively. L designates the flash ADC resolution, and M designates the CABS ADC resolution. According to Table 1, there is a tradeoff between power efficiency and area, as also visualized through the plots in Figure 16. The L–M = 2–6 architecture is the one with the largest area occupation, and L–M = 5–3 is the one with highest power consumption, making them least suitable. Minimizing the power consumption was the main priority of this work, which is why the 3–5 configuration was chosen over the 4–4 configuration. In addition to power and area considerations, selecting a 3-bit flash instead of a 4-bit flash ADC leads to approximately half the amount of kickback noise and input capacitance.

#### 4.3. Prototype Chip Layout and Testing Considerations

^{2}, including all of the SHDACs, CABS ADCs, flash ADC, bootstrap switches, DFFs, and thermometer-to-binary encoders. The clock generation circuits occupied 0.03 mm

^{2}, including the on-chip clock buffer, which was only added for the prototype test interface. Combined, the ADC core and clock generation occupied an area of 0.72 mm

^{2}. The digital calibration occupied 0.71 mm

^{2}, which included the calibration logic, DAC, test signal generation, and extra calibration channel (SHDAC, unity-gain buffer).

_{CM}in Figure 18. For the bias voltages that were connected to high-impedance nodes on the ADC chip (gate of MOS transistors), simple voltage dividers were employed without buffering. The ADC can operate in both normal mode and calibration mode, which can be set by an on-board switch. Another switch is used to set and reset the clock generation circuitry. To also allow manual calibration, the PCB contains DIP switches for the 6-bit input data of the coarse and fine codes, 4-bit address lines, and control signals of the calibration logic.

#### 4.4. Summary of Measurement Results

_{8-bit}and INL of −3.58/+2.79 LSB

_{8-bit}after flash ADC calibration), which also caused degradation that limited the dynamic performance (SNDR and SFDR) of the ADC for 8-bit accuracy. In retrospect, the main factor for the large 8-bit DNL/INL was the variation of the fabricated CABS ADC comparators’ offsets that were caused by random device mismatches. The CABS comparator offsets were estimated under the assumption of correlations between parameters during the Monte Carlo simulations, which was based on the proximity of the devices on the chip and the matched layout configurations. However, the measurements revealed that the offsets after fabrication were higher than the estimations. As observed during measurements, removing the last two LSBs of the CABS ADC stage lead to the suitable linearity performance for the ADC when evaluated with 6-bit accuracy. For this reason, the results in this section focus mainly on tests with 6-bit resolution (i.e., not using the last two LSB outputs). The measured DNL and INL errors of the hybrid ADC with 6-bit equivalence before and after flash ADC calibration were within −0.41/+0.50 LSB and −0.77/+0.52 LSB, respectively. The results indicate that the nonlinearity errors of the hybrid ADC were significantly reduced by the calibration of the flash ADC.

_{T}) and considerably lower parasitic capacitances. Hence, a design in a newer CMOS technology would lead to lower power consumption and a significant area reduction. Overall, in comparison to the specifications of the other works in Table 2, the measurement results of the proposed ADC architecture provide a proof-of-concept for its efficiency and performance.

## 5. Conclusions

## Conflicts of Interest

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**Figure 2.**Interpolation concept. (

**a**) Diagram of part of an ADC with interpolation; (

**b**) exemplification of preamplifier output vs. input voltage characteristics.

**Figure 16.**Estimated (

**a**) power, and (

**b**) area for the hybrid ADC with L-M bits, where L = flash ADC resolution, and M = CABS ADC resolution.

**Figure 19.**Test setup configuration at the ADC’s differential inputs for low-frequency measurements.

**Figure 23.**Measured output spectra (8192-point FFT) of the 6-bit 1 GS/s hybrid ADC output for: (

**a**) f

_{in}= 10.193 MHz and (

**b**) f

_{in}= 493.958 MHz before and after flash offset calibration.

**Table 1.**Architectural power and area tradeoffs: Comparison of options for the first and second stage resolutions in the example hybrid ADC architecture.

Subranging Choice * | No. of Comp. in Flash ADC | No. of Comp. in CABS ADC | No. of Activated Comparators during Each 8-bit Conversion | Est. Power of the Flash and CABS for Each 8-bit Conversion (mW) | Est. Total Minimum Area for One Flash and Four CABS ADCs (mm^{2}) |
---|---|---|---|---|---|

L–M | 2^{L} − 1 | 2^{M} − 1 | (2^{L} − 1) + M | (2^{L} − 1) ∙ P_{flash.comp} + M ∙ P_{CABS.comp} | (2^{L} − 1) ∙ A_{flash.comp} + 4 ∙ (2^{M} − 1) ∙ A_{CABS.comp} |

2–6 | 3 | 63 | 3 + 6 | 0.717 | 0.128 |

3–5 | 7 | 31 | 7 + 5 | 1.241 | 0.066 |

4–4 | 15 | 15 | 15 + 4 | 2.337 | 0.037 |

5–3 | 31 | 7 | 31 + 3 | 4.577 | 0.028 |

Spec. | This Example | [1] | [3] | [7] | [8] | [13] | [74] | [83] | [84] | [85] | [86] | |
---|---|---|---|---|---|---|---|---|---|---|---|---|

Sampling Rate (GS/s) | 1 | 1 | 1 | 1.25 | 1 | 1.6 | 1.5 | 0.6 | 1.4 | 1 | 1.2 | 0.8 |

Resolution (bit) | 6 | 8 | 8 | 6 | 6 | 6 | 7 | 6 | 7 | 6 | 8 | 6 |

CMOS Techn. (nm) | 130 | 130 | 55 | 130 | 65 | 90 | 90 | 130 | 45 | 65 | 65 | 65 |

Architect. | Subr.-TI | Subr.-TI | Subr. | TI-SAR | Pipe-line | TI-SAR | Flash | Async. SAR | Flash | Interp.-Subr. | Two-Step SAR | VCO-based |

ENOB@NQ | 5.26 | 5.48 | 6.19 | 5.0 | 5.25 | 4.44 | 6.05 | 5.02 | 6.17 | 5.16 | 6.97 | 4.8 |

SNDR@NQ (dB) | 33.42 | 34.74 | 39 | 32 | 33.4 | 28.5 | 38.2 | 32 | 38.9 | 32.8 | 43.7 | 30.6 |

SFDR@NQ (dB) | 45.71 | 46.03 | 53 | 35 | 41.03 | 35.5 | 46.6 | 46 | NA | 44 | 58.1 | 36.2 |

Supply Voltage (V) | 1.2 | 1.2 | 1.2 | 1.2 | 1 | 1.3 | 1.2 | 1.2 | 1.15 | 1.1 | 1.3 | 1 |

Power (mW) | 10.5, 8.7 ^{2} | 11 | 16 | 32 | 62 | 20.1 | 204 | 5.3 | 33.24 | 9.9 | 5 | 3.62 |

Area (mm^{2}) | <0.72 ^{3}, <1.4 ^{4} | 0.72 ^{3}, 1.4 ^{4} | 0.2 | 0.09 | 0.3 | 0.24 | 1.2 | 0.12 | 0.085 | 0.044 | 0.013 | 0.012 |

FoM ^{1}@NQ (fJ/conv. step) | 274, 227 ^{5} | 246 | 219 | 800 | 1629 | 579 | 2053 | 272 | 330 | 278 | 35 | 162 |

^{1}FoM = Power/(2

^{ENOB@NQ}× F

_{s}),

^{2}estimated power consumption for a 6-bit redesign,

^{3}ADC core area only,

^{4}total area with calibration circuitry,

^{5}estimated FoM for a 6-bit redesign. ENOB: efficient number of bits.

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**MDPI and ACS Style**

Zahrai, S.A.; Onabajo, M.
Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters. *J. Low Power Electron. Appl.* **2018**, *8*, 12.
https://doi.org/10.3390/jlpea8020012

**AMA Style**

Zahrai SA, Onabajo M.
Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters. *Journal of Low Power Electronics and Applications*. 2018; 8(2):12.
https://doi.org/10.3390/jlpea8020012

**Chicago/Turabian Style**

Zahrai, Seyed Alireza, and Marvin Onabajo.
2018. "Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters" *Journal of Low Power Electronics and Applications* 8, no. 2: 12.
https://doi.org/10.3390/jlpea8020012