# A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications

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## Abstract

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## 1. Introduction

**Figure 1.**Structure of the proposed model. (

**a**) DC-DC efficiency modeling; (

**b**) System energy cost model.

_{L}), time of operation, parasitic capacitance on the block, switching frequency, and activity factor. These parameters can change dynamically in power management techniques like DVFS. Using these parameters as input, the model calculates the overhead cost and change in the efficiency of each DC-DC converter in the system and provides the total system level energy consumed while executing a power management technique for the given workload profile.

_{L}is discharged to a lower voltage by dissipating its stored energy. The actual benefits can be obtained by taking these losses and overhead into account. Figure 2 shows a block diagram of a typical inductor based DC-DC converter. It includes a bias generator and comparators that cause the static loss. The control scheme that implements the switching pattern of the power switches MP and MN can vary across topologies. The switching loss is a function of the control scheme and the load. The power switches MP and MN, parasitic resistance of inductor (L

_{PAR}), and capacitor (C

_{ESR}) cause the conduction loss, which is determined by the load current and output voltage. These losses are all a function of the operating condition. The proposed model accurately predicts the trends in behavior of DC-DC converters across topologies implementing both pulse width modulation (PWM) and pulse frequency modulation (PFM) control schemes.

## 2. DC-DC Converter Model

#### 2.1. DC-DC Efficiency with Load Current

#### 2.1.1. Model for PWM Control Scheme

_{L}is the load current; ∆i is the current ripple in the converter; fs is the switching frequency; C

_{L}is the decoupling capacitor; R

_{LO}is the inductor series resistance; and a, b, and d are constants. Equation (1) represents the power loss in terms of various constants that cannot be obtained and that are non-intuitive to approximate prior to the design of converter, so it is difficult to apply this equation for design space exploration or for general modeling of DC-DC converter trends.

_{2}is the peak efficiency occurring at load Io, and η

_{1}is the minimum efficiency at a given load. For the verification of the model proposed in Equation (2), let us consider the following cases.

_{L}) over power drawn:

_{2}in Equation (2) can be obtained by equating the constants in Equations (4) and (2),

_{L}becomes very small, but it can predict the behavior for light load condition in a PWM control switching scheme based DC-DC converter with less than 5% error. Figure 4 shows this result.

_{DSAT}is the saturation current of the transistor. Clearly, as load current increases, the resistance increases. For light load condition, it is correct to assume that resistance does not change as I

_{DSAT}is much larger compared to I

_{L}. However, with an increase in load, the MOS resistance increases, causing elevated conduction loss. Also, at higher load the increased current in the inductor causes elevated conduction loss in the inductor’s parasitic resistance. Overall, the I

^{2}R loss increases, because of the increase in current and because of the increase in resistance caused by that increase in current. For a high load we know that:

_{2}, η

_{1}, k

_{1}, etc. in Equation (11) can be obtained by equating with respect to the powers of I

_{L}in Equation (10). The proposed equation matches the trend of equation reported in literature [3].

#### 2.1.2. Model for PFM Control Scheme

_{Out}= VI

_{L}and expanding using Taylor series,

#### 2.3. Verification of the Model

**Figure 3.**Efficiency Variation with load current in (

**a**) pulse width modulation (PWM) scheme with η

_{2}= 0.9, η

_{1}= 0.68 and I

_{L}= 1 mA; (

**b**) pulse frequency modulation (PFM) scheme with η

_{2}= 0.88 and a = 5 × 10

^{−5}.

_{2}as the peak efficiency reported in the corresponding paper and I

_{O}as the load for that peak efficiency. The value of η

_{1}is obtained experimentally based on [5,6,7,8], and we set η

_{1}= 10 for all the papers ([5,6,7,8]) employing the PWM control scheme. The converters [5,6,7] and [8] in part implement PWM. We find that the model predicts the efficiency behavior of the converters very accurately (<5% error for these papers). For [5,7,8] the error is less than 3%.

_{2}as the peak efficiency reported in the corresponding paper. The constant a represents the static loss of the converter and will vary from one converter to another. It causes the degradation in efficiency at light load condition in a PFM control scheme. For this comparison, we set the value of constant a in Equation (14) to match the least efficiency reported in each paper. The model predicts the behavior of [6] correctly for the PFM scheme, while it deviates at higher load for [8]. This is because we assumed in our model that PFM scheme is used only for a light load condition, whereas [8] shows results for loads up to 400 mA.

_{O}.

#### 2.4. Efficiency with Output Voltage

_{O}and with load current assuming a PWM control scheme. A DC-DC converter designed for a specific voltage and load will follow this trend when its load current or output voltage changes.

#### 2.5. Settling Time

_{O}is expected to change. The settling time of a converter to reach the desired voltage becomes an important overhead for these scenarios. The settling time ∆T in our proposed model is approximated as,

#### 2.6. Supply Rail Switching Energy

_{in}, if the new voltage is higher than the previous voltage. The additional energy overhead Ec is given by Equation (18) where V

_{1}and V

_{2}are the new and previous voltages of the converter. If V

_{1}is greater than V

_{2}, work is to be done by the supply V

_{in}. When V

_{1}is less than V

_{2}, no work is done by V

_{in}hence energy overhead will be zero.

_{2}to V

_{1}while running workloads. In such cases E

_{C}will be lower than given by Equation (18). Equation (16) helps us to predict the losses at a given load or voltage condition, while Equations (17) and (18) give the conversion energy and timing overhead. These equations enable a framework where overheads that originate from dynamic changes to the DC-DC converter output can be calculated for techniques like DVFS to accurately measure their energy benefits.

## 3. Evaluation of DVS Techniques Using the Proposed Model

**Figure 6.**Energy consumption for a microcontroller across voltage with and without consideration of the DC-DC converter efficiency.

**Figure 7.**(

**a**) Efficiency profiles for two different converters and (

**b**) the impact of a converter change on the overall energy drawn from the battery.

#### 3.1. Framework for Energy Calculation in DVFS

_{op}is the operating energy and η is calculated using Equation (3).

_{OP}greater than 1µs with a maximum benefit of more than 150% achievable at slower rates of VDD transitions. This implies that, for these assumptions, the 5 VDD system would save energy relative to the single VDD system when transitioning VDD to adapt to changes in the workload that are slower than ~1 µs.

#### 2.3. Panoptic Dynamic Voltage Scaling (PDVS)

#### 2.4. Framework for Energy Calculation in PDVS

_{1}< 0.8 V) for T1 time, PDVS accomplishes it by connecting the block to 0.4 V for T

_{11}and 0.8 V for T

_{12}, such that T

_{11}+ T

_{12}= T

_{1}of Figure 9. This approach is called voltage dithering. T

_{11}and T

_{12}are such that the performance of the block does not change. A final operating condition is given by Figure 12b.

## 4. Comparison of DVFS and PDVS using the Proposed Model

**Figure 14.**Energy Benefits of PDVS for different values of the virtual VDD capacitance of the block.

## 5. Conclusions

## Acknowledgement

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**MDPI and ACS Style**

Shrivastava, A.; Calhoun, B.H.
A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications. *J. Low Power Electron. Appl.* **2013**, *3*, 215-232.
https://doi.org/10.3390/jlpea3030215

**AMA Style**

Shrivastava A, Calhoun BH.
A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications. *Journal of Low Power Electronics and Applications*. 2013; 3(3):215-232.
https://doi.org/10.3390/jlpea3030215

**Chicago/Turabian Style**

Shrivastava, Aatmesh, and Benton H. Calhoun.
2013. "A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications" *Journal of Low Power Electronics and Applications* 3, no. 3: 215-232.
https://doi.org/10.3390/jlpea3030215