LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology
Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsThis paper proposes a novel LC tank oscillator based on a new negative resistor in FDSOI technology. The authors discuss the limitations of Moore's Law for analog and RF circuits and how FDSOI technology can improve analog and mixed signal cells by reducing the effects of SCE and DIBL. They introduce a cross-coupled back-gate technique to reduce the surface of the integrated circuit and demonstrate how it can be applied to a current mirror to create a negative output resistor. The paper includes a safety analysis and an efficiency analysis comparing their LC tank oscillator to other technologies. Overall, the proposed solution offers a simpler design with a low phase noise and a smaller silicon area. However, I recommend the following revisions to improve the manuscript:
1. The introduction provides a good background on the limitations of Moore's Law for analog and RF circuits and the advantages of FDSOI technology. However, providing more context on the specific challenges associated with designing LC tank oscillators and how the proposed approach addresses these challenges would be helpful. Additionally, the authors should consider including more recent references to support their claims.
2. The cited references are relevant to the research, but some are outdated. The authors should consider including more recent references to support their claims and demonstrate their knowledge of the field's current state.
3. The research design is appropriate, but the authors should provide more details on the specific parameters used in their simulations and measurements. Additionally, it would be helpful to include a discussion on the potential limitations of the proposed approach and how they were addressed.
4. Provide a more comprehensive discussion on the safety considerations of the proposed oscillator, particularly about utilizing FDSOI technology and the novel negative resistor. This will further strengthen the practical implications of the research.
5. The results are presented, but the authors should consider including more details on the specific performance metrics used to evaluate the proposed oscillator. Additionally, it would be helpful to include a discussion on the potential sources of variation and how they were addressed.
6. Expand the efficiency analysis to include a comparative evaluation with existing oscillator technologies, highlighting the proposed approach's specific advantages and potential drawbacks. This will provide readers with a more comprehensive understanding of the performance metrics.
7. The results support the conclusions, but the authors should consider including a discussion on the proposed oscillator's potential practical implications and scalability. Additionally, it would be helpful to include a discussion on the potential future directions for research in this area. Incorporate a detailed discussion on the proposed LC tank oscillator's potential practical implications and scalability, particularly in real-world applications within the context of wireless communication systems. This will enhance the relevance and applicability of the research findings.
Author Response
- The introduction provides a good background on the limitations of Moore's Law for analog and RF circuits and the advantages of FDSOI technology. However, providing more context on the specific challenges associated with designing LC tank oscillators and how the proposed approach addresses these challenges would be helpful. Additionally, the authors should consider including more recent references to support their claims.
Answer: We've modified the introduction to meet your expectations and added two recent references (plus one at the end of the paper, all published in 2023).
- The cited references are relevant to the research, but some are outdated. The authors should consider including more recent references to support their claims and demonstrate their knowledge of the field's current state.
Answer: we added two recent references in the introduction and one more at the end of the paper (all published in 2023).
- The research design is appropriate, but the authors should provide more details on the specific parameters used in their simulations and measurements. Additionally, it would be helpful to include a discussion on the potential limitations of the proposed approach and how they were addressed.
Answer: The simulations were carried out in Cadence using the PDK (CMOS28 FDSOI 1.5.a) supplied by STMicroelectronics. As we are under NDA, we cannot publish the values of this PDK, in particular the Spice parameters.
We have specified in the manuscript (at the end of section 2 on the FDSOI) that we use this PDK. In paragraph 4, we have also added a section on the sensitivity of negative resistance as a function of channel length (cf. Figure 14), main limitation of this topology.
In fact, while for the current mirror (cf. Figure 10), sensitivity to this parameter is very important, it becomes negligible for the realization of the negative resistance. We have added some discussion about this feature in modified paper
- Provide a more comprehensive discussion on the safety considerations of the proposed oscillator, particularly about utilizing FDSOI technology and the novel negative resistor. This will further strengthen the practical implications of the research.
Answer: same answer as before (Comment 3).
- The results are presented, but the authors should consider including more details on the specific performance metrics used to evaluate the proposed oscillator. Additionally, it would be helpful to include a discussion on the potential sources of variation and how they were addressed.
Answer: The results were compared using as a metric the FOM given by relation 8 and given in the references used. On the other hand, we have added a discussion of potential sources of variation and how they have been dealt with, in particular the sensitivity of negative resistance to transistor size (and therefore also to technological variations). This resistor is very robust to these variations
- Expand the efficiency analysis to include a comparative evaluation with existing oscillator technologies, highlighting the proposed approach's specific advantages and potential drawbacks. This will provide readers with a more comprehensive understanding of the performance metrics.
Answer: Only FDSOI technology enables such a topology to be envisaged, thanks to the access and efficiency of the back gate. In the comparison table, we have compared the performance thus obtained with conventional bulk CMOS technology, FinFET technology and another topology in FDSOI technology, to give a comprehensive overview of current technologies. However, we have added another reference [30] on FinFET technology to the discussion.
- The results support the conclusions, but the authors should consider including a discussion on the proposed oscillator's potential practical implications and scalability. Additionally, it would be helpful to include a discussion on the potential future directions for research in this area. Incorporate a detailed discussion on the proposed LC tank oscillator's potential practical implications and scalability, particularly in real-world applications within the context of wireless communication systems. This will enhance the relevance and applicability of the research findings.
Answer: In response to these comments, we have substantially modified and extended the conclusion
Author Response File: 
Author Response.pdf
Reviewer 2 Report
Comments and Suggestions for AuthorsA back-gate control technique using UTBB-FDSOI transistors was
presented that effectively reduces the SCE and DIBL effects in analog cells.
These effects need to be reduced. Size of the analog cells is reduced. Performance is maintained.
The SCE and DIBL effects can create a negative resistor circuit.
They wanted to implement a negative resistance for the LC tank oscillator.
English is no good.
Author Response
Comments on the Quality of English Language
English is no good.
Answer: We have done our best (using a grammar correction tool) to correct the English
Author Response File: Author Response.pdf
Reviewer 3 Report
Comments and Suggestions for AuthorsThis paper proposes an original biasing of the back gates of UTBB FDSOI transistors used in a current mirror in order control the output resistance of the mirror. By tuning the length of the transistors, the output resistance may be set positive or negative. Then the authors use this negative resistance to build an original LC oscillator. Although only simulation results are given, the LC oscillator exhibits performances close to the state-of-the-art.
The paper is clear and easy to understand. It could be improved by
1) correcting a few typo :
1.1) In the introduction : "... to implement analog cells." instead of "... to implement, especially for analog cells."
1.2) Line 159 : "... a fixed width of 100nm was found..." instead of 100µm ?
1.3) Lines 259 and 266 "settling time" instead of " setting time"
1.4) Line 287 : "... flicker noise reduction by complementary..." instead of "... flicker noise by complementary..."
2) mentioning if the curves of figure 4 were obtained from simulations or from experimental results
3) In equation (2) and (3), the authors implicitly assume that VTHn doesn't depend on L, which is not the case. Please comment on it and how this short channel effect on VTHn is taken into account in the sizing of the transistors
4) In figures 11 and 12, there is a big discrepancy between simulations and expérimental results in the linear region of the current mirror. Although this is not the region of interest for the author, is there any explanation on this discrepancy ?
5) As seen in Figure 9, the output resistance of the current mirror is hugely sensitive to the value of L. So it should be also very sensitive to fabrication dispersions. Could comment on it ? Have you done some Monte Carlo simulations to assess the impact of fabriation dispersion ?
Author Response
The paper is clear and easy to understand. It could be improved by
1) correcting a few typo :
1.1) In the introduction : "... to implement analog cells." instead of "... to implement, especially for analog cells."
Answer: done (in the abstract)
1.2) Line 159 : "... a fixed width of 100nm was found..." instead of 100µm ?
Answer: 100µm is the good value
1.3) Lines 259 and 266 "settling time" instead of " setting time"
Answer: done
1.4) Line 287 : "... flicker noise reduction by complementary..." instead of "... flicker noise by complementary..."
Answer: done (and thank you for these corrections)
2) mentioning if the curves of figure 4 were obtained from simulations or from experimental results
Answer: This measurement comes from STMicroelectronics. We have added the reference at the end of the figure legend.
3) In equation (2) and (3), the authors implicitly assume that VTHn doesn't depend on L, which is not the case. Please comment on it and how this short channel effect on VTHn is taken into account in the sizing of the transistors
Answer: We fully agree, and indeed we haven't taken this phenomenon into account in these equations. It's precisely the aim of our new topology (with back-gate control) to address this feature. We can see that these equations (as eq. 4) are false in figure 8 (red curve).
4) In figures 11 and 12, there is a big discrepancy between simulations and expérimental results in the linear region of the current mirror. Although this is not the region of interest for the author, is there any explanation on this discrepancy ?
Answer: Indeed this region does not interest us, even less in the case of negative resistance. However, we have sought an explanation for this phenomenon, but have not found a satisfactory answer to date. However, we contacted specialists in semiconductor physics, as well as process and design engineers from the company STMicroelectronics.
5) As seen in Figure 9, the output resistance of the current mirror is hugely sensitive to the value of L. So it should be also very sensitive to fabrication dispersions. Could comment on it ? Have you done some Monte Carlo simulations to assess the impact of fabrication dispersion ?
Answer: Indeed, you are absolutely right and we have added some comments on this subject on the simulation and measurement results of the current mirror. We can confirm that the MC simulations also show this high sensitivity. However, this is not the purpose of this paper, since we do not want to create a perfect current mirror, but a negative resistance. We therefore added a part on the sensitivity of the negative resistance to this parameter (see Figure 14) and showed, on the other hand, the robustness of this resistance to the value of L and therefore to technological dispersions
Author Response File: Author Response.pdf
Round 2
Reviewer 1 Report
Comments and Suggestions for AuthorsThe authors have answered all the comments in the reviews. I am satisfied with their answers and, hence, now I consider the work can be accepted as is.
