# Class AB Voltage Follower and Low-Voltage Current Mirror with Very High Figures of Merit Based on the Flipped Voltage Follower

^{1}

^{2}

^{3}

^{4}

^{*}

## Abstract

**:**

_{SS}= 46 MHz pF/µW and a current efficiency figure of merit FOM

_{CE}= 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology.

## 1. Introduction

_{out}= 1/g

_{m}(in the order of tens of kΩs) close to the unity voltage gain, and relatively high bandwidth BW = g

_{m}/(2π C

_{L}). The flipped voltage follower of Figure 1b [4] is an improved voltage follower that uses local negative feedback to provide lower output resistance R

_{out}= 1/[g

_{m}(g

_{m}r

_{o})] = 1/(g

_{m}A) (hundreds of Ω), where C

_{L}is the load capacitance, g

_{m}and r

_{o}are the transconductance gain and output resistance, and A = g

_{m}r

_{o}is the intrinsic gain of the MOS transistor. The basic Flipped Voltage Follower(FVF) version of Figure 1b (denoted here as CONV_FVF) suffers the serious limitation that it has a very low peak-to-peak output swing V

_{oswingpp}, which is independent of the supply voltage and given by V

_{oswingpp}= V

_{TH}− V

_{DSsat}(where V

_{TH}is the threshold voltage and V

_{DSsat}is the drain-source saturation voltage of M

_{FVF}). It operates in class A with a peak positive output current and positive slew rate limited by the bias current I

_{bias}to a value SR

^{+}= I

_{bias}/C

_{L}. Several versions of the flipped voltage follower have been reported with improved output range and lower output resistance. For example, the cascode FVF (denoted here as CONV_CSCFVF) shown in Figure 1c and reported in [5] uses an additional branch with a cascode transistor M

_{CAS}that increases the local feedback loop gain and provides even lower output resistance by a factor A = g

_{m}r

_{o}so that, in this circuit, R

_{out}= 1/[g

_{m}(g

_{m}r

_{o})

^{2}] = 1/[g

_{m}A

^{2}] (on the order of tens of Ωs). It also has an increased output swing, which is dependent on the supply voltage and given by V

_{outswingpp}= V

_{DD}− (V

_{GS}+ V

_{DSsat}) = V

_{DD}− V

_{TH}− 2V

_{DSsat}. The cascode FVF of Figure 1c (denoted here as CONV_CSCFVF) is a class A circuit with a positive slew rate seriously limited by the bias current to a value: SR

^{+}= I

_{bias}/C

_{L}. Class AB versions of the FVF have also been reported [6,7,8,9] to overcome this limitation to a certain degree.

_{in}= 1/g

_{m}(on the order of tens of kΩs), moderately high output resistance R

_{out}= r

_{o}(g

_{m}r

_{o}) = r

_{o}A (on the order of tens of MΩs), high linearity, low gain error, low output compliance voltage (V

_{outmin}= 2V

_{DSSat}), and moderate input voltage requirements V

_{in}= V

_{GS}= V

_{TH}+ V

_{Dssat}. A simple rearrangement of the circuit of Figure 2a is shown in Figure 2b. It injects the input current source I

_{in}at the source of the cascode transistor M

_{1C}(node V

_{x}) instead of at its drain (node V

_{y}). This reduces the input voltage requirements from V

_{GS}to V

_{DSsat}and leads to a reduction in the input resistance by a factor A from R

_{in}= 1/g

_{m}to R

_{in}= 1/[g

_{m}(g

_{m}r

_{o})] = 1/[g

_{m}A]. Notice that, in this circuit, the input transistors M

_{1}and M

_{1C}form a flipped voltage follower with a constant input voltage V

_{cn}at the gate of M

_{1C}and the current input signal I

_{in}injected at the output terminal of the FVF (node V

_{x}). In spite of the improvement in the mirror characteristics, this modification suffers from a non-linear current mirror gain resulting from lambda effect and unequal drain source voltages in the input and output transistors M

_{1}and M

_{2}of the current mirror. This is due to the fact that the cascode input and output transistors M

_{1C}and M

_{2C}have unequal drain currents which cause their gate-source voltages to be different. The gate source voltages of M

_{1C}and M

_{2C}determine the drain-source voltages of M

_{1}and M

_{2}and the linearity of the mirror. This effect can be greatly mitigated in a BiCMOS process by replacing the cascode transistors by bipolar transistors.

## 2. Proposed Circuits

#### 2.1. High-Performance Class AB Voltage Follower HP_CSCFVF

#### 2.1.1. Description

_{source}that provides efficient class AB operation. M

_{source}has a small quiescent current I

_{Qsource}, but it can inject positive output currents I

_{out}into the load C

_{L}, which are much larger than I

_{Qsource}. On the other hand, transistor M

_{sink}can sink very large negative load currents (also much larger than the quiescent current of M

_{sink}given by I

_{Qsink}= I

_{Qsource}+ I

_{bias}), as is discussed below. The biasing branch has two diode-connected PMOS transistors M

_{b}and M

_{bC}. Based on replica biasing, this branch sets the voltage V

_{y}to a value V

_{y}= V

_{DD}− V

_{SGb}and the gate voltage of M

_{source}to a value V

_{g}= V

_{y}+ V

_{bat}, where V

_{bat}= I

_{bat}R

_{bat.}The values of I

_{bat}and R

_{bat}are selected so that V

_{bat}has an approximate value V

_{bat}= V

_{SDsat}= 0.1 V. In this case, the quiescent source-gate voltage of M

_{source}is given by V

^{Q}

_{SGsource}= V

_{SGb}− I

_{bat}R

_{bat}. This leads to a quiescent voltage V

^{Q}

_{SGsource}= V

_{SGb}− V

_{SDsat}≈ V

_{TH}close to the threshold voltage of M

_{source}. This quiescent source-gate voltage sets a relatively small quiescent current I

_{Qsource}in M

_{source}, which is independent of the supply voltage. A capacitor C

_{bat}forms a high-pass filter with R

_{bat}and C

_{bat}. This is used to transfer fast transient variations from V

_{x}to the gate V

_{g}of M

_{source.}

#### 2.1.2. Class AB Operation of Proposed Voltage Follower

_{in}, the output voltage V

_{oHPCSC}increases, and the gate voltage V

_{x}of M

_{sink}decreases. The current in M

_{sink}decreases (and eventually turns off) and the dynamic changes in V

_{x}are transferred to V

_{g}by C

_{bat}to the gate of M

_{source}. The decrease in V

_{g}causes the current I

_{source}of M

_{source}to increase, providing a positive output current I

_{out}that can be significantly larger than the quiescent current I

_{Qsource}of M

_{source}(in the design described in Section 3, I

_{Qsource}has a value I

_{Qsource}= 7 µA). For negative input voltages, the output voltage decreases, and V

_{x}increases. This increases the current I

_{sink}and provides a large negative output current I

_{out}that can be much larger than the quiescent current I

_{Qsink}of M

_{sink}. The FVFs in Figure 1b,c and Figure 3 use an RC compensation network formed by C

_{c}and R

_{c}for the local feedback loop. These elements provide a dominant pole and a high-frequency zero at V

_{x}that approximately match the output pole of the open loop gain ω

_{pout}= g

_{mFVF}/C

_{L}at the output node V

_{oHPCSC.}This allows FVF circuits to significantly improve their bandwidth with respect to the conventional voltage follower of Figure 1a. This simple but effective FVF compensation and bandwidth extension technique was reported in [10].

#### 2.2. High-Performance Low-Voltage Current Mirror (HP_CS_CM)

_{SEinvfcamp}with gain A

_{aux}and a level shifter FVF

_{levelshifter}. The transistor level implementation of the auxiliary amplifiers and the level shifter is shown in Figure 4b. Each of the amplifiers form local negative feedback loops with the cascode transistors M

_{1C}and M

_{2C}. They boost their effective gain by the gain A

_{aux}= (g

_{m}r

_{o})

^{2}= A

^{2}of the auxiliary amplifiers. They are implemented in Figure 4b using single-ended folded cascode inverting amplifiers formed by M

_{FCA1}and M

_{CA1}and by M

_{FCA2}and M

_{CA2}. A modified flipped voltage follower is used to generate a very-low-impedance node V

_{G}that operates as the signal ground (or reference node) for the input common source transistors M

_{FCA1}and M

_{FCA2}of the auxiliary amplifiers. Transistors M

_{BAT}, M

_{FCA1}, and M

_{FCA2}have the same W/L dimensions, the same quiescent current, and quiescent gate-source voltages. For this reason, the negative feedback loops of the auxiliary amplifiers shown in Figure 4a,b cause the gate voltages V

_{refX}, V

_{X}, and V

_{XP}to have the same value. This results in equal drain-source voltages of the input and output mirror transistors and leads to a highly linear and accurate current mirror gain. On the other hand, the large gain boosting of the cascode transistors M

_{1C}and M

_{2C}provided by the folded cascode auxiliary amplifiers leads to an extremely low input resistance R

_{in}= 1/(g

_{m}A

^{3})/2, which is lower by a factor of A

_{aux}= A

^{2}/2 than the input resistance of the FVF mirror of Figure 2b and to an extremely high output resistance R

_{out}= r

_{o}A

^{3}that is higher by the same factor A

_{aux}than the output resistance of the mirrors of Figure 2. The value of V

_{refX}(selected by the designer) sets the input voltage requirement V

_{in}of the mirror. It must be higher than V

_{DSsat}in order to keep the input and output mirror transistors in saturation. In the proposed design, V

_{refX}was selected to have a value V

_{refX}= 0.15 V, but it can also have been lower since input and output transistors had a value V

_{DSat}= 0.06 V in the design discussed in Section 3. Remarks: (1) The FVF level shifter is a modified version of the basic FVF (or CONV_FVF). It has a resistor R in series with transistor M

_{BFVF}. This resistor R in Figure 4a is used to generate a voltage drop that pulls down the voltage at node V

_{z}and allows transistor M

_{BAT}to have enough drain-source (V

_{DS}> V

_{DSSat}) voltage to operate in saturation. (2) The implementation of the auxiliary amplifiers using folded cascode amplifiers with a floating virtual ground node V

_{G}in which the nominal voltage is set by the designer has the purpose of reducing the supply requirements of the circuit. (3) A distinctive characteristic of the proposed mirror is that the modified FVF with resistor R allows the quiescent value of V

_{G}to be set to a value that is convenient to minimize the supply voltage and the input voltage requirements of the circuit. It also allows M

_{BAT}to be maintained in saturation. Previous implementations of mirrors with auxiliary amplifiers (i.e., the regulated cascode mirrors discussed in [1]) required the source of the auxiliary amplifier’s input transistors to be connected to one of the supply rails and does not allow the supply requirements to be minimized or V

_{in}to be set. (4) If required, the gain A

_{aux}of the auxiliary amplifiers can be further boosted from a value A

_{aux}= A

^{2}/2 in the circuit of Figure 4b to a value A

_{aux}= A

^{3}/2 by utilizing double-cascoded auxiliary amplifiers. This would also boost the output impedance by an additional factor A/2 and decrease the input impedance of the mirror by the same factor. (5) The local negative feedback loops formed by the auxiliary amplifiers have only one high-impedance node at V

_{Y}and V

_{YP}. Compensation elements R

_{c}and C

_{c}are used to generate a dominant pole (and a zero) at these nodes. This is in order to compensate these loops and to prevent instability. (6) In order to reduce power dissipation, the auxiliary amplifiers and the FVF level shifters are biased with currents I

_{bias}/k, which is a factor k times smaller than the bias current I

_{bias}of the input and output mirror transistors M

_{1}and M

_{2}. In the proposed design, a value k = 10 was used. This lead to a total quiescent current and power dissipation of the proposed mirror that is only 25% higher than the power dissipation of the mirrors of Figure 2. (7) The proposed current mirror can be easily transformed into a class AB mirror using the techniques reported in [11].

## 3. Simulation Results

#### 3.1. Simulations of the High-Perfromance Class AB Follower HP_CSCFVF

_{DD}= 0.75 V, V

_{SS}= −0.75 V (or V

_{supply}= V

_{DD}− V

_{SS}= 1.5 V), I

_{bias}= I

_{bCAS}= 5 µA, R

_{bat}= 55 kΩ, C

_{bat}= 2 pF, I

_{bat}= 2 µA, C

_{L}= 100 pF, and W/L = 5/0.2 (µm) for all PMOS, and NMOS transistors, except the PMOS and NMOS transistors, implementing biasing sources that had dimensions W/L = 5/0.4 (µm), values Cc = 0.6 pF, and Rc = 75 kΩ were used. In order to save on silicon area, R

_{c}was implemented with an NMOS transistor with W/L = 0.75/15 and with the gate connected to the positive rail V

_{DD}. R

_{c}and C

_{c}were selected to provide a dominant pole ω

_{pdom}= 1/R

_{x}C

_{c}at node V

_{X}: and a high-frequency zero ω

_{z}= 1/R

_{c}C

_{c}at V

_{x}that approximately matches at the output pole ω

_{pout}= g

_{mFVF}/C

_{L}at the output node V

_{oHPCSC}of the FVF, as suggested by the design guidelines in [10]. Transistors M

_{source}and M

_{sink}were scaled up by factors 10 and 3, respectively. This was performed in order to equalize their dynamic output currents and to achieve symmetrical slew rates (SR+ and SR−). The total quiescent current and power dissipation of the proposed circuit were I

_{TotQ}= 21 µA and P

_{dissQ}= 31.5 µW, respectively. The small signal transconductance g

_{m}and output conductance g

_{ds}of the NMOS and PMOS unit transistors had the following values: g

_{mN}= 148 µA/V, g

_{dsN}= 2.94 µA/V, g

_{mP}= 160 µA/V, and g

_{dsP}= 2.2 µA/V.

_{pp}pulse input. Figure 6b shows the corresponding load capacitor currents. It can be seen that the proposed circuit has close to symmetrical positive and negative peak output currents (and consequently slew rate) with the values I

_{outpk}

^{+}= 2.6 mA and I

_{outpk}

^{−}= 2.47 mA, respectively. Notice that the proposed circuit has peak output currents, which are a factor 118 times larger than the total quiescent current of the circuit. This corresponds to a very large current efficiency factor CE = I

_{outpk}/I

_{TotQ}= 118. The peak currents (and slew rates) of the conventional circuits is much lower due to their class A operation.

_{L}= 100 pF). Figure 7 shows the pulse response for various C

_{L}values of 10 pF, 32 pF, 55 pF, 80 pF, and 100 pF. It can be seen that, in all cases, the pulse response has a only a small overshoot. Figure 8 shows the AC response of the output resistance of the proposed circuit. It has a very low value R

_{out}= 2.11 Ω at low frequencies. The layout of the proposed design is shown in Figure 9. It occupies a 114 µm × 47 µm Si area.

_{pp}100 kHz input signal and 1% for a 0.5 V

_{pp}1 MHz sinusoidal input signal. The equivalent input noise power spectral density and RMS noise are 29 nV/√Hz and 130 µV

_{RMS}. The small signal figure of merit is FOM

_{SS}= 46 MHz·pF/µW, and the large signal current efficiency figure of merit is FOM

_{CE}= I

_{outpk}/I

_{TotQ}= MIN{I

_{outpk}+, I

_{outpk}−}/I

_{TotQ}= 118. The global figure of merit is $\mathrm{F}\mathrm{O}{\mathrm{M}}_{\mathrm{Global}}=\sqrt{\mathrm{F}\mathrm{O}{\mathrm{M}}_{\mathrm{S}\mathrm{S}}\mathrm{F}\mathrm{O}{\mathrm{M}}_{\mathrm{C}\mathrm{E}}}=73$.

_{SS}), a large signal and current efficiency (FOM

_{CE}), and global (FOM

_{Global}) figures of merit in the table.

#### 3.2. Simulation Results for Low-Voltage High-Performance Current Mirror HP_CS_CM

_{bias}= 2 µA. The resistor used to implement R

_{bat}in the FVF level shifter has a value 75 kΩ. It is implemented using a PMOS transistor. The W/L ratio of the PMOS and NMOS transistors used in the input and output stages of both current mirrors are W/L = 5 µm/0.4 µm. Transistors used in the auxiliary amplifiers and the FVF level shifter of the proposed current mirror are scaled down by factor k = 10. This was performed in order to reduce the quiescent power dissipation. The compensation elements had values C

_{c}= 1.5 pF and R

_{c}= 4 kΩ.

^{5}times lower than the CN_CS_CM.

_{in}from o to 10 µA. It can be seen that the proposed HP_CS_CM has a constant 0.15 V input voltage, while the input voltage of the conventional mirror CN_CS_CM varies from 450 mV to 550 mV.

_{out}− I

_{in})/I

_{in}] in the current transfer characteristic of the CN_CS_CM and the proposed HP_CS_CM as a function of the input current. It can be seen that, as expected, errors are similar since, in both mirrors, the drain-source voltages of input and output transistors are very similar. The total harmonic distortion of the proposed HP_CS_CM is given in Table 3 for a 200 µA amplitude sine wave at frequencies 500 Hz, 10 KHz, 1 MHz, and 100 MHz.

_{CM}= BW/P

_{diss}is used to compare the circuits. Notice that the proposed mirror has the highest FOM

_{CM}in the table (the input compliance voltage of the resistance based mirror in [18] is lower but it has the serious shortcoming that, with the reported 39.6 mV input voltage, it is subject in practice to very large random gain/linearity errors caused by mismatch in V

_{DS}due to random offset of input and output transistors in the control circuit).

## 4. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

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**Figure 2.**(

**a**) Conventional cascode current mirror and (

**b**) FVF-based low-voltage cascode current mirror with reduced input impedance.

**Figure 4.**(

**a**) Scheme of the proposed low-voltage high-performance current mirror, (

**b**) transistor level implementation and biasing circuit, and (

**c**) implementation of resistor R, cascode current source I

^{*}bias and simple current sources I

_{bias}.

**Figure 6.**(

**a**) Pulse response of the proposed HP_CSCFVF and CONV_CSCFVF for C

_{L}= 100 pF and (

**b**) output current of the HP_CSCFVF and CON_CSCFVF at C

_{L}= 100 pF.

**Figure 7.**Pulse response of proposed HP_CSCFVF for load capacitor values: 10 pF, 32 pF, 55 pF, 77.5 pF and 100 pF.

**Figure 10.**Monte Carlo analysis of the Proposed HP_CSCFVF quiescent power dissipation over 200 samples MC simulation for process and mismatch variation.

**Table 1.**(A) Corner analysis at 27 °C; (B) corner analysis at 120 °C; (C) corner analysis at −20 °C.

(A)
| ||||||

Corner | tt | ff | fs | sf | ss | SD |

I_{TotQ} (µA) | 21 | 22 | 21 | 22 | 21 | 0.49 |

f_{3dB} (MHZ) | 14.6 | 18 | 15.2 | 14.5 | 12.5 | 1.77 |

SR (V/µs) | 24.3 | 28 | 21.5 | 25.6 | 21.7 | 2.4 |

I_{outpk} (mA) | 2.68 | 3.04 | 2.5 | 2.7 | 2.42 | 0.2 |

(B)
| ||||||

Corner | tt | ff | fs | sf | ss | SD |

I_{TotQ} (µA) | 26 | 29 | 26 | 27 | 25 | 1.35 |

f_{3dB} (MHZ) | 15 | 18.5 | 15.2 | 14.8 | 12.7 | 1.86 |

SR (V/µs) | 22.5 | 25.5 | 20.18 | 22.34 | 20.13 | 1.9 |

I_{outpk} (mA) | 2.45 | 2.73 | 2.38 | 2.42 | 2.22 | 0.16 |

(C)
| ||||||

Corner | tt | ff | fs | sf | ss | SD |

I_{TotQ} (µA) | 20 | 20 | 20 | 19 | 19 | 0.49 |

f_{3dB} (MHZ) | 14.4 | 17.6 | 15.8 | 14.8 | 12.3 | 1.74 |

SR (V/µs) | 26.6 | 29.3 | 22.9 | 25.8 | 22.8 | 2.4 |

I_{outpk} (mA) | 2.79 | 3.06 | 2.67 | 2.8 | 2.5 | 0.18 |

Parameter | Ref./Year [6]/2012 | Ref./Year [12]/2016 | Ref./Year [13]/2018 | Ref./Year [14]/2016 | Ref./Year [15]/2021 | Ref./Year [16]/2018 | CONV_VF Figure 1a | This Work Figure 3 | |
---|---|---|---|---|---|---|---|---|---|

Process technology (µm) | 0.35 | 0.18 | 0.18 | 0.5 | 0.045 | 0.5 | 0.18 | 0.18 | 0.18 |

Exp | Sim by Auth. | Sim | Exp | Sim | Exp | Sim | Sim | Sim | |

Supply (V) | 3 | ±0.9 | 1.2 | 1.5 | 1.2 | 2 | 1.2 | ±0.75 | ±0.75 |

I_{TotQ} (µA) | 81 | 243 | 20.8 | 80 | 8.3 | 69 | 20 | 9 | 21 |

Load Cap. (pF) | 20 | 50 | 10/100 | 50 | 1 | 47 | 1 | 100 | 100 |

BW (MHz) | 5.8 | 3.65 | 15@100 pF | 10 | 170 | 32 | 670.2 | 0.347 | 14.6 |

I_{outpk}+ (mA) | 1.62 | 3.16 | 0.32 | 1.8 | 0.17 | 1.59 | 0.116 | 0.085 | 2.6 |

I_{outpk}− (mA) | 1.67 | 3.16 | NA | 1.8 | 0.08 | 1.42 | 0.120 | 0.034 | 2.47 |

SR^{+} (V/µS) | 79.4 | 63.2 | 32@10 pF | 36 | 42 | 33.8 | 116.6 | 2.5 | 34.47 |

SR^{−} (V/µS) | 83.6 | 63.2 | NA | 36 | 50 | 30.3 | 120.5 | 12 | 34.03 |

Output resistance (Ω) | NA | NA | 56 | NA | 1.15k | NA | 144 | 1.2k | 2.11 |

Quiescent power P_{dissQ} (µWatt) | 243 | 437 | 25 | 120 | 10 | 138 | 24 | 13.5 | 31.5 |

FOM_{CE} = I _{outpk}/I_{TotQ} | 20 | 12 | 15 | 22.5 | 10 | 20 | 5.8 | 3.7 | 118 |

FOM_{SS} = BWxC _{L}/P_{dissQ}[(MHz)pF]/µW | 0.47 | 0.42 | 60 | 4.16 | 17 | 10.9 | 28 | 2.5 | 46 |

FOM_{Global} | 3.06 | 2.24 | 30 | 9.7 | 13 | 15 | 12.7 | 3.04 | 73 |

**Table 3.**Variation in THD with frequency for HP_CS_CM at different frequencies with 200 µA amplitude sinusoidal current.

Frequency (Hz) | THD (dB) |
---|---|

500 | −60 |

10 k | −62 |

1 M | −60 |

100 M | −40 |

**Table 4.**Summary of results of 200 samples Monte Carlo analysis of proposed current mirror’s parameter.

Parameter Name | Mean Value | Standard Deviation |
---|---|---|

Bandwidth (MHz) | 144 | 0.789 |

Input resistance (dBΩ) | −13.7 | 0.728 |

Output Resistance(dBΩ) | 221 | 0.505 |

Quiescent Power (µW) | 5.33 | 0.066 |

Gain (A/A) | 0.999 | 17.8 µ |

Parameter | [17] | [18] | [19] | [20] | This Work |
---|---|---|---|---|---|

Input Compliance Voltage | 520 m | 39.6 m | - | - | 150 m |

Current Transfer error (%) | 1.71 | 0.6 | 0.16 | 0.22 | 0.1 |

Input resistance (Ω) | 21.43 | 496 | 68.3 | 130 | 0.212 |

Output Resistance (Ω) | 1.14 G | 1 M | 10.5 G | 9.5 G | 112 G |

Bandwidth (Hz) | 6.17 G | 181 M | 402 M | 2.7 G | 144 M |

Noise (pA/√Hz) | - | - | 7.8 | - | - |

Supply (V) | 1 | 0.9 | 1 | 1 | 1 |

Power (µW) | 916.65 | 154 | 110 | 142.9 | 5 |

FOM_{CM} (MHZ/µW) | 6.73 | 1.17 | 3.6 | 18.89 | 28.8 |

Technology (µm) | 0.18 | 0.18 | 0.18 | 0.18 | 0.18 |

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## Share and Cite

**MDPI and ACS Style**

Ramírez-Angulo, J.; Paul, A.; Gangineni, M.; Hinojo-Montero, J.M.; Huerta-Chua, J.
Class AB Voltage Follower and Low-Voltage Current Mirror with Very High Figures of Merit Based on the Flipped Voltage Follower. *J. Low Power Electron. Appl.* **2023**, *13*, 28.
https://doi.org/10.3390/jlpea13020028

**AMA Style**

Ramírez-Angulo J, Paul A, Gangineni M, Hinojo-Montero JM, Huerta-Chua J.
Class AB Voltage Follower and Low-Voltage Current Mirror with Very High Figures of Merit Based on the Flipped Voltage Follower. *Journal of Low Power Electronics and Applications*. 2023; 13(2):28.
https://doi.org/10.3390/jlpea13020028

**Chicago/Turabian Style**

Ramírez-Angulo, Jaime, Anindita Paul, Manaswini Gangineni, Jose Maria Hinojo-Montero, and Jesús Huerta-Chua.
2023. "Class AB Voltage Follower and Low-Voltage Current Mirror with Very High Figures of Merit Based on the Flipped Voltage Follower" *Journal of Low Power Electronics and Applications* 13, no. 2: 28.
https://doi.org/10.3390/jlpea13020028