# A Review of Algorithms and Hardware Implementations for Spiking Neural Networks

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## Abstract

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## 1. Introduction

## 2. Fundamentals of Spiking Neural Networks

#### 2.1. Neuron Models

#### 2.2. Synapse Models

#### 2.3. Encoding Information with Binary Input Spikes in SNNs

## 3. Learning Rules in Spiking Neural Networks

#### 3.1. Unsupervised Learning with STDP

#### 3.2. Supervised Learning with Backpropagation

#### 3.3. Conversion of SNN from DNN

## 4. Hardware Implementations of SNNs

#### 4.1. Large-Scale Neuromorphic Accelerator

#### 4.1.1. General Strategy

#### 4.1.2. Comparison of Large-Scale Neuromorphic Accelerator

#### 4.2. Low-Power SNN Accelerator

## 5. Future Possibilities for Spiking Neural Networks

## 6. Conclusions

## Funding

## Conflicts of Interest

## References

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**Figure 1.**Schematic representation of a spiking neuron. The neuron receives many input spikes from the previous layers’ neurons. Each input spike is modulated with a weight, producing weighted synaptic inputs. Those inputs are accumulated as the neuron membrane potential. If the membrane potential crosses a certain threshold, the neuron will emit a spike to the downstream layer and the membrane potential will be reset. A refractory period, where the neuron remains inactive (i.e., does not further integrate any incoming spikes) after firing, may be implemented in some models.

**Figure 2.**Several coding schemes for encoding analog values to spike trains. (

**a**) The rate-coding scheme. The analog values are represented as the rate at which input spikes are produced. In the example, there are five input spikes in a span of 10 timesteps. Hence, the analog value of $5\xf710=0.5$ is encoded. (

**b**) The TTFS scheme. In this encoding scheme, each analog value could be represented with only one input spike. The analog value to be encoded is inversely proportional to the delay of the input spike, i.e., a higher analog value will produce an earlier input spike. (

**c**) The ISI scheme. In this scheme, the precise inter-spike timings between two consecutive spikes are used to encode the analog input value.

**Figure 3.**Unsupervised learning with STDP. (

**a**) A graph showing the relationship between the change in synapse strength $\Delta w$ and the relative timing between the pre- and post-synaptic spikes $\Delta t$. The synapse strength decreases or increases exponentially with the relative timing. (

**b**) A diagram showing the interaction between neurons in two successive layers (layer 1 and layer 2 in the figure). The pre-synaptic spike from neuron 1 (in red) comes before the post-synaptic spikes, hence the synapse strength increases (LTP). In the case of neuron 2 (in blue), the post-synaptic spike happens after the pre-synaptic spike from neuron 2. In this case, the synapse strength decreases (LTD).

**Figure 4.**The conversion flow from DNNs to SNNs. Many different types of pre-trained networks from the DNN domain, such as Convolutional Neural Network (CNN), Multi-layer Perceptrons (MLP) or Recurrent Neural Network (RNN), can be converted to the SNN domain. The network parameters are directly transferred to the SNN model. Usually, to preserve accuracy, a weight/threshold normalization scheme is required. Many different network-specific operations may need to be modified, such as the max-pooling operations and the soft-max layer of CNN, or the gated operations of RNN. The input data with analog values in the DNN domain also need to be converted to spike trains with an input encoding scheme.

**Figure 6.**ODIN chip block-level diagram by Frenkel et al. [48]. The chip supports a form of online learning based on Spike-driven synaptic plasticity (SDSP). Local neuron memory and synapses memory is used to time-multiplex the dynamics of 256 neurons, using only a single neuron logic. The inputs and outputs of the chip use AER protocol to handle event-driven, asynchronous outputs. The neuron update logic supports both simple LIF and Izhikevich [16] neuron models.

**Figure 7.**Block diagram of the neuromorphic hardware proposed by Yin et al. [49]. The architecture achieves a high level of energy efficiency by fixing the size of the network to a three-layer, 256-256-10 configurations. The input spikes for each layer are encoded by the spike encoder to select only the active neurons. Based on these indexes, corresponding weight values are fetched and loaded to the neurons calculation logic. Dedicated SRAM to store the weights of each layer is included.

**Figure 8.**Block diagram of the neuromorphic chip proposed by Chen et al. [51]. The architecture consists of 64 neuromorphic cores, connected with a custom NoC. Each core has separate synapse memory and neuron update logic, which can support up to 64 neurons per core. High energy efficiency is achieved with a sparse connection mapping between neurons.

Processor | SpiNNaker [44] | Neurogrid [46] | TrueNorth [45] | Loihi [47] |
---|---|---|---|---|

Implementation | Digital | Analog | Digital | Digital |

Technology | 130 nm | 180 nm | 28 nm | 14 nm |

Weight Resolution | 8b–32b | 13b | 1b–4b | 1b–64b |

Online learning | Yes | No | No | Yes |

Neurons per cores | 1000 | 65,000 | 256 | 1024 |

Cores per chip | 16 | 1 | 4096 | 128 |

Energy/SOPS (pJ) | 27,000 | 941 | 26 | 15 |

Processor | Frenkel et al. [48] | Yin et al. [49] | Zheng et al. [50] | Chen et al. [51] |
---|---|---|---|---|

Implementation | Digital | Digital | Digital | Digital |

Technology | 28 nm | 28 nm | 65 nm | 10 nm |

Weight Resolution | 4b | 7b | 16b | 8b |

Online learning | Yes | No | Yes | Yes |

Networks models | FC | FC | FC | FC |

1 layer | 3 layers | 3 layers | 4 layers | |

Input coding scheme | Rate coding | Rate coding | Rate coding | Rate coding |

MNIST accuracy | 85.4% | 98.7% | 90% | 97.9% |

Core Area (mm^{2}) | 16 | 1 | 4096 | 128 |

Energy/classification | 15 nJ | 773 nJ | 1.12 J | 1.7 J |

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**MDPI and ACS Style**

Nguyen, D.-A.; Tran, X.-T.; Iacopi, F.
A Review of Algorithms and Hardware Implementations for Spiking Neural Networks. *J. Low Power Electron. Appl.* **2021**, *11*, 23.
https://doi.org/10.3390/jlpea11020023

**AMA Style**

Nguyen D-A, Tran X-T, Iacopi F.
A Review of Algorithms and Hardware Implementations for Spiking Neural Networks. *Journal of Low Power Electronics and Applications*. 2021; 11(2):23.
https://doi.org/10.3390/jlpea11020023

**Chicago/Turabian Style**

Nguyen, Duy-Anh, Xuan-Tu Tran, and Francesca Iacopi.
2021. "A Review of Algorithms and Hardware Implementations for Spiking Neural Networks" *Journal of Low Power Electronics and Applications* 11, no. 2: 23.
https://doi.org/10.3390/jlpea11020023