#
A g_{m}/I_{D}-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

^{*}

## Abstract

**:**

## 1. Introduction

## 2. The Three-Stage OTA

## 3. Design Strategy of the Three-Stage OTA for Sub-Threshold Region

#### 3.1. Small-Signal Analysis and Stability Requirements

#### 3.2. Settling Time, Slew Rate and Gain–Bandwidth Product

#### 3.3. Noise Analysis and First-Stage Transconductance

#### 3.4. Gain–Bandwidth Product and Current Dissipation

#### 3.5. The Design Procedure in the Sub-Threshold Region

`Specifications`’ can be changed by the designer on the basis of the final application. In Section ‘

`Step 1`’, the designer chooses the parameters

`gamma`,

`CC2`and

`r`. Similarly, in ‘

`Step 3`’ the designer sets the separation factors,

`Ke`and

`Ki`. The remaining part of the script evaluates the amplifier parameters. Note that the procedure can be implemented without any advanced computational tool and that the script is provided just to summarize the steps. In addition, in contrast to those procedures based on more advanced ad hoc tools (such as that offered in [72]), a fine tuning at the circuit simulator level is in general required to finalize the design.

## 4. OTA Design and Validation Results

#### Comparison with Other Recent Sub 1-V Amplifiers

## 5. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## Appendix A. MatLab Code of the Proposed Design Procedure

## References

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**Figure 1.**Block schematic of the three-stage OTA based on the reverse nested Miller compensation with feed-forward stage (RNMC-FF).

**Figure 2.**The transistor-level implementation of the three-stage OTA based on the reverse nested Miller compensation with feed-forward stage (RNMC-FF).

**Figure 3.**${g}_{m}/{I}_{D}$ ratio vs. the gate–source overdrive, ${V}_{GS}-{V}_{\mathrm{TH}}$, for the 65 nm regular threshold transistors. The plots are produced for two different channel lengths and for both the complementary devices. The plot puts into evidence the sub-threshold region and the saturation one. W and L are expressed in microns.

**Figure 4.**Bode plot of the open-loop gain of the OTA (magnitude and phase). Black lines: transistor typical models. Colored lines: 400-run Monte Carlo simulation with intra-die (local) and inter-die (global) variations.

**Figure 5.**Time response to step input signals. Black lines: transistor typical models. Colored lines: 400-run Monte Carlo simulation with intra-die (local) and inter-die (global) variations. (

**a**) Input step of $\pm 100\phantom{\rule{0.166667em}{0ex}}\mathrm{mV}$; (

**b**) Input step of $\pm 500\phantom{\rule{0.166667em}{0ex}}\mathrm{mV}$.

**Figure 6.**Monte-Carlo simulation of the settling time of the closed-loop OTA compensated with the RNMC-FF.

Parameter | Value |
---|---|

${G}_{\mathrm{m}1}$ | $3.97\phantom{\rule{0.166667em}{0ex}}\mathsf{\mu}\mathrm{A}/\mathrm{V}$ |

${G}_{\mathrm{m}2}$ | $23.4\phantom{\rule{0.166667em}{0ex}}\mathsf{\mu}\mathrm{A}/\mathrm{V}$ |

${G}_{\mathrm{m}3}$ | $26.0\phantom{\rule{0.166667em}{0ex}}\mathsf{\mu}\mathrm{A}/\mathrm{V}$ |

${G}_{\mathrm{mf}}$ | $26.0\phantom{\rule{0.166667em}{0ex}}\mathsf{\mu}\mathrm{A}/\mathrm{V}$ |

${I}_{1}$ | 132 nA |

${I}_{2}$ | 779 nA |

${I}_{3}$ | 865 nA |

${C}_{\mathrm{C}1}$ | $2.5\phantom{\rule{0.166667em}{0ex}}\mathrm{pF}$ |

${C}_{\mathrm{C}2}$ | $150\phantom{\rule{0.166667em}{0ex}}\mathrm{fF}$ |

Transistor | Aspect Ratio |
---|---|

M1 *, M2 * | $10/0.25$ |

M3, M4 | $3/0.25$ |

M5 | $6/0.5$ |

M6 | $18/0.25$ |

M7 | $16.5/0.5$ |

M8 | $4.5/0.25$ |

M9 ${}^{\u2020}$ | $6/0.25$ |

M10 ${}^{\u2020}$ | $24/0.25$ |

M11 | $18/0.25$ |

M12 ${}^{\u2020}$ | $0.5/8$ |

M13 | $10/0.5$ |

M14 ${}^{\u2020}$ | $1/1$ |

MBN | $5/0.5$ |

MBP | $3/0.5$ |

[26] | [27] | [28] | [29] | This Work | |
---|---|---|---|---|---|

Tech | 180 nm | 350 nm | 180 nm | 65 nm | 65 nm |

Year | 2016 | 2017 | 2020 | 2020 | 2021 |

Input-driven | Bulk | Gate | Bulk | Bulk | Gate |

${V}_{\mathrm{DD}}$ (V) | 0.7 | 0.9 | 0.3 | 0.25 | 1.0 |

${I}_{\mathrm{DD}}$ ($\mathsf{\mu}$A) | 36.3 | 27.0 | 0.043 | 0.104 | 2.12 |

Power ($\mathsf{\mu}$W) | 25.4 | 24.3 | 0.013 | 0.026 | 2.12 |

${C}_{\mathrm{L}}$ (pF) | 20 | 10 | 30 | 15 | 100 |

$\mathrm{GBW}$ (kHz) | 3000 | 1000 | 3.1 | 9.5 | 253 |

IFOM${}_{s}$ | 1653 | 370 | 2146 | 1370 | 11,934 |

FOM${}_{s}$ | 2361 | 412 | 7154 | 5481 | 11,934 |

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**MDPI and ACS Style**

Giustolisi, G.; Palumbo, G.
A *g*_{m}/*I*_{D}-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads. *J. Low Power Electron. Appl.* **2021**, *11*, 21.
https://doi.org/10.3390/jlpea11020021

**AMA Style**

Giustolisi G, Palumbo G.
A *g*_{m}/*I*_{D}-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads. *Journal of Low Power Electronics and Applications*. 2021; 11(2):21.
https://doi.org/10.3390/jlpea11020021

**Chicago/Turabian Style**

Giustolisi, Gianluca, and Gaetano Palumbo.
2021. "A *g*_{m}/*I*_{D}-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads" *Journal of Low Power Electronics and Applications* 11, no. 2: 21.
https://doi.org/10.3390/jlpea11020021