Physico-Chemical Origins of Electrical Characteristics and Instabilities in Solution-Processed ZnSnO Thin-Film Transistors

Round 1

Reviewer 1 Report

In this work, the authors fabricated ZnSnO Thin-Film Transistors via solution-processed method and also investigated the electrical properties of their devices under the change of the Sn/(Zn+Sn) ratio systematically. The optical Sn/(Zn+Sn) ratio of the devices was confirmed to 0.4, in which the electrical properties and bias stabilities are the best in all cases. This work is very meaningful for the development of commercial low-dimensional martials based FET, especially, 2D materials-based devices. Therefore, I recommend this paper for publishing on Coating after minor revision.                

 

1.It is noted that the title of this article, ie, “Physico-Chemical Origins of Bias Stabilities along with Electri- cal Characteristics obtained by Controlling the Composition Ratio in Solution-Processed ZnSnO Thin-Film Transistors” is too, too long and consuming, so this title should be improved to offer a concise but comprehensive summary.

 

2. Moreover, the author should check the spelling and punctuation mistakes in this article, e.g., “ZTO solutions with an Sn/(Zn+Sn) molar ratio of 0.3 to 0.6 were synthesized to demonstrate the underlying mech-anism of the electrical characteristics and bias-induced stabilities” in the abstract, "μsat" on line 228, "cm²/Vs" on line 229, etc. 

Comments for author File: Comments.docx

Author Response

Comment 1. It is noted that the title of this article, ie, “Physico-Chemical Origins of Bias Stabilities along with Electri- cal Characteristics obtained by Controlling the Composition Ratio in Solution-Processed ZnSnO Thin-Film Transistors” is too, too long and consuming, so this title should be improved to offer a concise but comprehensive summary.

Reply: As the reviewer suggested, we edited the title to provide a concise but comprehensive summary.

- [Revised manuscript] Lines 1-2: The title was changed from “Physico-Chemical Origins of Bias Stabilities along with Electrical Characteristics obtained by Controlling the Composition Ratio in Solution-Processed ZnSnO Thin-Film Transistors” to “Physico-Chemical Origins of Electrical Characteristics and Instabilities in Solution-Processed ZnSnO Thin-Film Transistors”

 

Comment 2. Moreover, the author should check the spelling and punctuation mistakes in this article, e.g., “ZTO solutions with an Sn/(Zn+Sn) molar ratio of 0.3 to 0.6 were synthesized to demonstrate the underlying mech-anism of the electrical characteristics and bias-induced stabilities” in the abstract, "μsat" on line 228, "cm2/Vs" on line 229, etc.

Reply: As the reviewer pointed out, we edited all mistakes. We appreciated to the reviewer’s fine review.

Author Response File: Author Response.docx

Reviewer 2 Report

Please consider the following points to improve the quality of the manuscript:

1. Please do FT-IR analysis to explain the interaction and the effect of different ratios.

2. Experimental section, you applied different temperatures, time and curing at different stages. Please mention the reference. If this has been done the first time, how have you optimized these experimental conditions?

Author Response

Comment 1. Please do FT-IR analysis to explain the interaction and the effect of different ratios.

Reply: As the reviewer suggested, we conducted FT-IR analysis to explain the effect of compositional ratio on the chemical characteristics of ZTO thin films. We tried to explain the effect of the composition ratio by observing O-H or C-H vibrations through FT-IR. Unfortunately, it was impossible to observe clear peaks and compare ZTO films with various composition ratios with each other through FT-IR through post-annealing at 500°C (ACS Appl. Mater. Interfaces 2014, 6, 20786 / ACS Appl. Mater. Interfaces 2021, 13, 8584). However, we analyzed the effect of the composition ratio of the ZTO film on the atomic state through XPS as shown in Figure 2. Since the characteristics of the ZTO thin films with various composition ratio were quantitatively analyzed through the ratio of M-O, Vo, and M-OH through XPS, we hope that the reviewer will consider this point. We would like to thank the reviewers for this suggestion, and we will proceed with quantitative and accurate chemical/physical/structural analysis of ZTO semiconductors through follow-up studies.

 

Comment 2. Experimental section, you applied different temperatures, time and curing at different stages. Please mention the reference. If this has been done the first time, how have you optimized these experimental conditions?

Reply: As suggested by the reviewer, we added a detailed explanation of why we applied the corresponding annealing temperature and time for each annealing step. References are also mentioned to aid the reader's understanding. The time and temperature we applied for each annealing step were optimized through many experiments. The background theories and experiments for optimization of annealing time and temperature in each step are described below. These descriptions have also been added to the revised manuscript. TFTs fabricated in this study have three stages of annealing process. First, pre-annealing was conducted at 120℃ for 30 min. Pre-annealing is a stage to form a solidified thin film by evaporating the solvent in the ZTO solution. When the pre-annealing temperature is too high, the roughness of the thin film is degraded, and pinholes or pore sites are formed, which can result in deterioration of electrical characteristics and bias stability. Thus, we have optimized the pre-annealing temperature through our previous study. We mentioned our previous study as a reference in revised manuscript (Electronics 2022, 11, 2822). Second, post-annealing was conducted at 500℃ for 1 h. Post-annealing activates the semiconductor by inducing condensation and densification of the thin film. The annealing temperature differs depending on the precursor, metal cation, and solvent. The desirable annealing temperature can be obtained through thermogravimetric analysis, and the post-annealing temperature of the solution-processed ZTO semiconductors are generally about 400~500℃ according to reported papers. We optimized the post-annealing temperature to 500℃ for 1 h through our knowledge and TFT experiments. We added the regarding reference in revised manuscript (Adv. Funct. Mater. 2020, 30, 1904632). Finally, low-pressure thermal treatment was conducted after deposition of source/drain electrodes. The low-pressure thermal treatment induces hydrophobic semiconductor surface and densification of the thin film. Thus, this process improves the switching characteristics of solution-processed ZTO TFTs. The study regarding low-pressure thermal treatment was conducted in our group, and the study is now preparing for publication to a journal. A more detailed description has been added to the revised manuscript.

- [Revised manuscript] Lines 84-94, 98-100: 8 sentences of “Pre-annealing is a stage to form … the ZTO solution.”, “When the pre-annealing temperature is … characteristics and bias stability [21].”, “Thus, we have optimized … our previous study [21].”, “Post-annealing activates the semiconductor … of the thin film [3].”, “The annealing temperature … metal cation, and solvent.”, “The desirable annealing temperature … our TFT experiments [3,14,15,21].”, “The low-pressure thermal treatment … of the thin film.” and “thus, this process improves … solution-processed ZTO TFTs.” were added.

Author Response File: Author Response.docx

Round 2

Reviewer 2 Report

The manuscript has been revised accordingly, its recommendation for publication.