Nb₂O₅ and Ti-Doped Nb₂O₅ Charge Trapping Nano-Layers Applied in Flash Memory

Abstract

High-k material charge trapping nano-layers in flash memory applications have faster program/erase speeds and better data retention because of larger conduction band offsets and higher dielectric constants. In addition, Ti-doped high-k materials can improve memory device performance, such as leakage current reduction, k-value enhancement, and breakdown voltage increase. In this study, the structural and electrical properties of different annealing temperatures on the Nb₂O₅ and Ti-doped Nb₂O₅(TiNb₂O₇) materials used as charge-trapping nano-layers in metal-oxide-high k-oxide-semiconductor (MOHOS)-type memory were investigated using X-ray diffraction (XRD) and atomic force microscopy (AFM). Analysis of the C-V hysteresis curve shows that the flat-band shift (∆V_FB) window of the TiNb₂O₇ charge-trapping nano-layer in a memory device can reach as high as 6.06 V. The larger memory window of the TiNb₂O₇ nano-layer is because of a better electrical and structural performance, compared to the Nb₂O₅ nano-layer.

1. Introduction

Conventional polysilicon floating gate issues have been explored in recent years because of problems related to the downscaling of memory devices [1,2,3,4,5]. For this study, high-k materials were chosen as replacements for conventional polysilicon floating gate memory to form metal-oxide-high k-oxide-semiconductor (MOHOS)-type memories [6,7]. Compared with the traditional SONOS-type memory, MOHOS-type has larger memory windows [8,9,10,11]. Otherwise, charge-trapping layers using high-k materials have faster program/erase speeds and better data retention because of larger conduction band offsets and higher dielectric constants [12,13,14,15,16]. Among various rare earth oxides, High-k Nb₂O₅ shows a high dielectric constant (k = 40), wide band gap (E_G = 3.2 eV), and a large conduction band offset [17]. To further enhance the memory performance of the device, addition of Ti atoms into trapping layer has been conducted, and some studies [18,19,20,21,22,23] reported that Ti-doped high-k materials as charge-trapping layers can improve memory device performance such as leakage current reduction, k-value enhancement, program/erase speeds improvement, and charge loss reduction. On the other hand, the performances of other different types of memory structures were presented by previous studies; Ostraat et al. reported that aerosol nanocrystal devices with 0.2 mm channel lengths exhibit large threshold voltage shifts (>3 V), excellent endurance (>10⁵ program/erase cycles), and long-term non-volatility (>10⁶ s) for low-cost non-volatile memory applications [24,25]. Ruffino et al. studied the electrical conduction of Au nanoclusters embedded in SiO₂ films. The local I-V_tip characteristics exhibited an asymmetric behavior with a clear threshold voltage Vth for the electrical conduction, decreasing with the average Au grain size [26].

In our study, this work investigated the differences between metal-oxide-high k-oxide- semiconductor (MOHOS)-type flash memory devices using Nb₂O₅ or TiNb₂O₇ as charge-trapping nano-layers. Our research indicates that the Ti-doped Nb₂O₅ (TiNb₂O₇) charge trapping nano-layer has a larger memory window because of the better electrical and structural properties. Therefore, the Ti-doped Nb₂O₅-based flash memory might be promising for future industrial memory applications. Structural analyses included X-ray diffraction (XRD) and atomic force microscopy (AFM), while electrical analyses included Capacitance-Voltage (C-V) hysteresis, program/erase speed, and data retention measurements.

2. Materials and Methods

The schematic diagrams of Al/SiO₂/Nb₂O₅/SiO₂/Si and Al/SiO₂/TiNb₂O₇/SiO₂/Si (MOHOS)-type flash memory devices are shown in Figure 1a,b, respectively. First, single-crystal 4-inch n-type silicon (100) wafers were cleaned using a standard RCA process. Then, a 3-nm SiO₂ film was thermally grown as a tunneling oxide layer using a dry oxidation furnace system at 850 °C. Then, (a) a 12-nm Nb₂O₅ trapping nano-layer was deposited by RF sputtering with a pure niobium target (99.99% pure) in argon (Ar) and oxygen (O₂) gas ambient, while (b) an approximately 12-nm Ti-doped Nb₂O₅ (TiNb₂O₇) trapping nano-layer was deposited by RF co-sputtering of a niobium and titanium target as comparison. After that, the above two kinds of samples underwent rapid thermal annealing treatment in O₂ ambient for 30 second from 700, 800, 900 and 950 °C to form Nb₂O₅ and TiNb₂O₇ charge trapping nano-layers, respectively. Subsequently, a 20-nm SiO₂ film was deposited as a blocking oxide layer by plasma-enhanced chemical vapor deposition at a substrate temperature of 300 °C. After deposition of the blocking oxide layer, a 300-nm Al film was deposited by thermal evaporator and a gate pattern was defined through lithography and wet etching. Finally, a 300-nm Al film was deposited on the backside. C-V hysteresis and data retention were measured with an HP-4284 LCR meter, P/E speed was measured by an HP8110 pulse generator, and leakage current was measured using an HP4156C semiconductor parameter analyzer. Structural analyses of the Nb₂O₅ and TiNb₂O₇ trapping layers were performed by XRD and AFM to examine the connections between electrical characteristics and structural properties. The XRD spectrum was performed by a grazing incidence of CuKa (k = 1.542 A) radiation. The system used a grazing incidence angle (θ = 0.5) in an XRD spectrum in the diffraction angle range (2θ) from 20° to 60°. The surface morphologies of the Nb₂O₅ and TiNb₂O₇ charge-trapping nano-layers were monitored using atomic force microscopy (AFM) by a Veeco model D5000 operated in tapping mode using an Applied Nano silicon tip with a 50 N/m spring constant. The scan area was 3 um x 3 um with a set engagement ratio of 80%.

3. Results and Discussion

To examine device performance under different annealing conditions, we compared different C-V hysteresis curves under sweeping voltages, as shown in Figure 2a,b and Figure S1 of the Supplementary Materials. The forward sweep began from inversion region to accumulation and the reverse sweep moved in another direction with the electrons charging into and discharging from the trapping film. The C-V curves indicate that annealing could enlarge the memory window of the device. The Ti-doped Nb₂O₅ (TiNb₂O₇) sample which underwent RTA treatment at 900 °С had a larger memory window (6.06 V) and better storage capability compared with that of the Nb₂O₅ sample annealed at 900 °С (4.64 V). Our research shows that the TiNb₂O₇ nano-layer possesses better electrical characteristics than the Nb₂O₅ nano-layer, likely because of the enhanced dielectric constants, increased breakdown voltage, and reduced leakage current provided by the addition of Ti. According to the result, it also can be seen that the memory window increased with the annealing temperature from 700 to 900 °С, and the sample annealed at 900 °С had the largest memory window (Nb₂O₅: 700 °С/0.99 V, 800 °С/2.73 V, 900 °С/4.64 V; TiNb₂O₇: 700 °С/1.3 V, 800 °С/4.37 V, 900 °С/6.06 V). As the material quality of the charge-trapping layer is a decisive factor in trapped electron storage capability, the results indicate that the TiNb₂O₇ charge-trapping nano-layer annealing at 900 °С can enhance the formation of a well-crystallized structure.

Figure 3a,b shows the programming and erasing speed of the Nb₂O₅ and TiNb₂O₇ charge-trapping nano-layers for 800 and 900 °C annealing under Vg = 13 V programming voltage and −16 V erasing voltage. By the way, the programming and erasing speed of the above samples with applying various bias were also presented in Figures S2 and S3 of the Supplementary Materials. The V_fb shift is defined as the change in the flat-band voltage between the virginal and erased states. During supply forward bias, the electron will inject from the Si channel to high-k trapping layers and storage in trapping layers and it will change in fla-band voltage. On the other hand, if we supply reverse bias, the electron will de-trapped from high-k trapping layers to Si channel. In these figures, the programmed state was measured at Vg = 13 V with various time from 1 us to 10 s, and the erase state was measured at Vg = –16 V with various time from 1 ms to 10 s. In our result, it can be found that the TiNb₂O₇ charge-trapping nano-layer annealed at 900 °C showed a faster program/erase speed than other samples when operating at same programming/erasing voltage. It can be attributed the TiNb₂O₇ charge-trapping nano-layer can enhance higher dielectric constant, which can increase the effective electric field across the tunneling oxide and permit electron easily through FN-tunneling from Si channel to the charge-trapping layers.

Figure 4a,b shows the retention characteristics of Nb₂O₅ and TiNb₂O₇ charge-trapping layer after annealing at 800 and 900 °С. The curves were measured at room temperature and 85 °С. The programmed state was the same Vg = 9 V for 100 ms. Charge loss rate was calculated as:

$$Chargelossrate(\%)=\left[\frac{V_{(t)}-V_o}{V_1-V_o}\right]\times 100\%$$

where V_(t) is the V_fb of various time, V₁ is the first V_fb after being programmed, and V₀ is the fresh one. In our result, the sample annealing at 900 °C has better retention characteristics than that at 800 °C, it’s because of formation structures in high temperature. On the other hand, the MOHOS-type memory with TiNb₂O₇ charge-trapping nano-layer after annealed at 900 °C shows a smaller charge loss rate than other samples. The sample annealed at 900 °C shows a smaller charge loss of 9.3% at room temperature (RT) and 17.8% at 85 °C after 1 × 10⁴ s, this is possibly because of the formation of well-crystallized TiNb₂O₇ trapping nano-layer. In Figure 4c, shows the leakage current curves of Nb₂O₅ and TiNb₂O₇ trapping nano-layer, it can be seen that the TiNb₂O₇ sample shows a lower leakage current than Nb₂O₅ sample, this is because the TiNb₂O₇ can reduce the leakage current and enhance the breakdown of the electric field to improve effectively the above charge loss.

In order to identify the composition of Nb₂O₅ and TiNb₂O₇ structures at different temperatures, the X-ray diffraction has been used for analysis of Nb₂O₅ and TiNb₂O₇ structures. The XRD analysis in the range of diffraction angle 2θ from 20° to 60° was obtained by grazing incidence angle (θ = 0.5°) measurements. Figure 5a,b show the XRD analysis of MOHOS-type memory with Nb₂O₅ and TiNb₂O₇ trapping nano-layer before and after annealing at different temperatures. For the Nb₂O₅ nano-layer, it can be seen that the temperature will induce crystallization in high-k trapping layer. According to the XRD analysis, the Nb₂O₅ trapping nano-layer has some Nb₂O₅ diffraction peaks in (0 0 5), (−2 1 5), (1 1 2), (6 2 1), and (3 8 1) at 29.6°, 33.1°, 47.8°, 54.6°, and 56.4°. The peak intensity became stronger at higher annealing temperatures, and the Nb₂O₅ nano-layer annealing at 900 °C exhibited stronger peak intensity in Nb₂O₅ (−215), it can be seen that the sample annealing at 900 °C formed a better Nb₂O₅ nano-layer structure. For the TiNb₂O₇ trapping nano-layer, it has some TiNb₂O₇ diffraction peaks in TiNb₂O₇ (−3 1 2), TiNb₂O₇ (0 2 0), TiNbO₄ (2 2 0), and TiNb₂O₇ (−11 1 2) at 28.6°, 47.8°, 54.7°, and 56.4°. The similar trend that the TiNb₂O₇ peak intensity also became stronger at higher annealing temperature and the TiNb₂O₇ nano-layer annealing at 900 °C exhibited the strongest peak intensity in TiNb₂O₇ (020) than the other temperatures. This means the crystallization enhancement can be found when the sample annealing is at high temperatures. However, when the annealing temperature increased to 950 °C, the TiNb₂O₇ peaks declined. This may be because of the formation of a thicker Nb-silicate layer between TiNb₂O₇ charge-trapping nano-layer and oxide interface layer to degrade the crystallinity of TiNb₂O₇ layer [27].

To visualize the film surface texture in a more practical manner, AFM was used to examine surface roughness of the Nb₂O₅ and TiNb₂O₇ nano-layers for the as-deposited and RTA-annealed samples at 900 °С, as shown in Figure 6a–d. It can be seen that the surface roughness of Nb₂O₅ and TiNb₂O₇ nano-layers of the as-deposited and 900 °С annealed samples exhibit 0.41 nm, 0.51 nm, 2.68 nm, and 3.51 nm, respectively. Since annealing could effectively increase the surface roughness of the film and reinforce the crystallization of TiNb₂O₇ nano-layers, larger roughness values and larger grains could be observed with increasing annealing temperatures. In line with the above results, the roughest surface and largest grains occurred for the TiNb₂O₇ nano-layers after RTA treatment at 900 °С. The increase in surface roughness is attributed to the niobium oxide intermixing with the titanium film, resulting in the enhancement of grain growth when annealed at 900 °C. However, the TiNb₂O₇ nano-layer annealed at 950 °C exhibited a decrease of roughness as compared to 900 °C, indicating that the oxygen leaving the TiNb₂O₇ layer and moving to the TiNb₂O₇/oxide interface resulted in a poorly crystallized TiNb₂O₇ structure and a low-k interfacial Nb silicate layer at the TiNb₂O₇/oxide interface [28]. Figure 6e shows details of the surface roughness of Nb₂O₅ and TiNb₂O₇ nano-layers, with increasing annealing temperature. Overly, all the samples with Ti-doping show higher surface roughness as compared to Nb₂O₅. Larger grains are formed owing to the higher oxygen affinity of Ti increases in the reaction of Nb₂O₅ and thus enhances the formation of grain growth to cause rougher surface [29,30]. Moreover, the Ti-doped Nb₂O₅ (TiNb₂O₇) charge-trapping layer at 900 °C exhibited a larger grain size with more uniform distribution compared with the Nb₂O₅ layer at 900 °C. The increase in surface roughness is attributed to the titanium-incorporated niobium oxide film resulting in the enhancement of grain growth to obtain a larger grain size [31,32,33,34].

4. Conclusions

Our research evaluated Nb₂O₅ and Ti-doped Nb₂O₅ charge trapping layers for non-volatile memory applications. Compared with the Nb₂O₅ trapping layer, the devices with a TiNb₂O₇ trapping layer exhibited a larger memory window and faster program/erase speeds. The results indicate that the TiNb₂O₇ charge-trapping nano-layer annealing at 900 °С can reinforce the bonding strength to enhance the formation of a well-crystallized structure for performance improvement.

In addition, the TiNb₂O₇ trapping layer shows a smaller charge loss of about 9.3% at room temperature and 17.8% at 85 °C after 10⁴ s, because the TiNb₂O₇ layer can reduce the leakage current and enhance the breakdown electric field to effectively improve the charge loss. Moreover, structural analyses of the Nb₂O₅ and TiNb₂O₇ trapping layers were performed by XRD and AFM to investigate and confirm the connections between electrical characteristics and structural properties. Therefore, the MOHOS-type memory device with the Ti-doped Nb₂O₅ charge-trapping nano-layer shows itself to be a very promising candidate for future non-volatile flash memory.