IGBT Overvoltage Protection Based on Dynamic Voltage Feedback and Active Clamping

Abstract

In view of the stability of the unmanned aerial vehicle (UAV) power system, this paper found that the voltage spike generated by IGBT mainly occurs when the IGBT is turned off in the study of the power system interior and IGBT drive and overvoltage protection, and an excessive voltage spike will lead to IGBT damage. To eliminate this serious threat to the safe operation of the circuit, an IGBT overvoltage protection circuit combining dynamic voltage feedback and active clamping is proposed. In this method, active clamping and dynamic voltage feedback circuits are operated alternately, and the drive circuit is controlled by the feedback of capacitor’s the dynamic voltage rise rate. The gate current output of the IGBT is directly compensated to control the signal delay of the gate, combined with improving the lifting effect of the active clamp circuit on the gate voltage and suppressing the peak of the turn-off voltage. According to the IGBT turn off process, combined with SABER simulation, this paper finally builds IGBT turn off experimental circuit to prove that the proposed method suppresses the size of the turn off voltage spike, further analyzes the effect of key circuit parameters on the suppression of the turn off voltage spike, thereby ensuring the safe operation of the IGBT, and improving the stability of the UAV power system.

1. Introduction

Insulated gate bipolar transistors (IGBTs) have the advantages of high switching frequency, high withstand voltage, low on-state voltage and easy driving in switching circuits. IGBTs play an important role in high-power applications such as inverters [1,2,3,4]. However, in the actual process, because of fast IGBT switching [5], the collector current drop rate of the IGBT is relatively high, resulting in excessive transient voltage spikes between the collector and the emitter [6,7,8]. Voltage spikes exceeding the rated collector–emitter voltage of the IGBT will cause the IGBT to breakdown, which seriously threatens the operational safety of the inverter circuit [9].

The passive snubber circuit uses capacitance to suppress the voltage rise rate of the device, which can simply and effectively solve the problem of voltage spikes, but it will increase the device loss [10,11,12]. In contrast to the passive snubber circuit, the effect of voltage spike suppression is achieved by controlling the IGBT gate. This method is collectively referred to as IGBT active gate control technology. Among them, high-voltage spikes are suppressed by changing the gate resistance of the IGBT during switching [13]. IGBT gate-driving methods based on the feedbacks di/dt and dv/dt [14,15,16,17,18] are also used to suppress voltage overshoot. Usually, the turn-off voltage spike of an IGBT is limited by using an active voltage clamping method [19,20,21,22,23], but the operating loss is large, which affects the reliability of the circuit, so dynamic voltage feedback can be used. The IGBT gate is controlled in advance to reduce the operating loss of the clamping circuit.

In this paper, an overvoltage suppression method combining dynamic voltage feedback and active clamping is proposed. The IGBT gate is controlled by the capacitive feedback voltage rise rate, and the turn-off voltage spike is fed back to the gate through the active clamping circuit to recharge the gate, thus suppressing voltage spikes.

In this paper, through an analysis of the IGBT turn-off process, combined with SABER simulation, the influence of important parameters in the dynamic voltage feedback circuit on the turn-off process is studied, and the suppression effects of different parameters on the turn-off voltage spike are proposed. Finally, the corresponding circuit verification is built to verify the suppression effect of different parameters.

2. Analysis of IGBT Turn-Off Voltage Spike

According to the working principle of an IGBT, the commutation circuit of an IGBT with an inductive load can be simplified to the application circuit shown in Figure 1, where Q is the IGBT to be tested, $R_g$ is the gate resistance, D is the antiparallel diode, L is the load inductance, and $V_{DC}$ is the DC voltage source.

When testing the IGBT through the circuit in Figure 1, according to the measured waveform of the IGBT tube, the turn-off process of the IGBT can be divided into five stages, as shown in Figure 2, where $V_{th}$ is the threshold voltage of the IGBT, $V_m$ is the Miller plateau voltage of the IGBT, $V_H$ is the positive terminal voltage, and $V_L$ is the negative terminal voltage.

Assuming that the IGBT is turned on in the initial state, at $t_0$, the control signal is reversed from high to low, and the IGBT is controlled to turn off and the IGBT enters stage I ($t_0$∼$t_1$), the IGBT current is the load inductor current $i_L$ and remains unchanged, and the gate voltage $V_{ge}$ begins to drop to the Miller plateau. Because of the higher Miller voltage $V_m$, the IGBT works as usual, and the IGBT turn-on voltage drop and turn-on current remain unchanged. In stage II ($t_1$∼$t_2$), the collector–emitter voltage $V_{ce}$ begins to rise, the total current $I_T$ remains unchanged, and the IGBT begins to exit the saturation region and charges the Miller capacitor to maintain this state, thereby forming a Miller platform. The Miller platform ends and the turn-off process enters stage III ($t_2$∼$t_3$), the IGBT begins to exit the saturation region, the gate voltage $V_{ge}$ continues to drop to the threshold voltage $V_{th}$, $V_{ce}$ rises to the DC voltage value, and the IGBT current $I_T$ decreases slightly. At this time, the descending speed depends on the ascending speed of $V_{gc}$. From time $t_3$, $V_{ce}$ rises to the stable value of the DC voltage, the freewheeling diode starts to conducting, and $I_T$ starts to drop rapidly. Because of the existence of parasitic inductance in the circuit, resonance occurs, making the voltage at both ends of the IGBT higher than the voltage of the DC bus, thus generating a voltage spike. In stage V, $V_{ge}$ continues to drop, $I_T$ enters the current tailing process, and the IGBT exits the saturation zone and enters the cut-off zone. At time $t_5$, $V_{ge}$ drops to the turn-off voltage (a normally negative value ensures reliable turn-off), the tailing current ends, the IGBT completely enters the cut-off zone, and the whole turn-off process ends.

According to the IGBT turn-off process, the turn-off overvoltage spike of the IGBT is inevitable, which is due to the switching action of the IGBT, and the current value flowing through the parasitic inductance changes rapidly. Therefore, the turn-off current change rate and parasitic inductance $L_q$ determine the turn-off overvoltage peak value $\Delta U$ of the IGBT, and the relationship is as follows:

$$\Delta U=L_q\frac{\mathrm{d}{i}_c}{\mathrm{d}t}$$

(1)

$$i_c=i_L+C_{gc}\frac{\mathrm{d}{V}_{ce}}{\mathrm{d}t}$$

(2)

Formula (1) shows that reducing the rate of change of the off current and the parasitic inductance can reduce the turn-off overvoltage spike. The main influence of the parasitic inductance comes from the connection inductance between the IGBT module and the DC capacitor. In practice, the parasitic inductance can be reduced by reducing the length of the DC loop or reducing the length of the positive and negative DC bus bars while increasing their width. Because of the limitation of the process level, when the parasitic inductance is limited to 200 nH, greatly reducing it further is difficult. In Formula (2), $i_L$ is the load current, and the current value of the IGBT is related to its voltage rise rate. Therefore, controlling the voltage rise rate becomes the main method for reducing the turn-off overvoltage spike.

3. Overvoltage Suppression Circuit Combining an Active Clamp and Dynamic Feedback

3.1. Circuit Design

As an improvement on the traditional overvoltage suppression circuit of an active clamp, the design idea of the overvoltage suppression circuit in this paper is as follows: (1) The overvoltage suppression circuit is composed of two independent parts: an active clamp and dynamic voltage feedback; (2) a capacitor is used to feedback the dynamic voltage rise rate; (3) the active clamp circuit is improved and the overvoltage feedback loop is increased; (4) a voltage source $V_{CC}$ is added to the IGBT gate to prevent the gate voltage from being too high due to feedback, and the gate voltage is clamped.

In summary, the designed active clamp and dynamic voltage feedback combined with the overvoltage suppression schematic diagram are shown in Figure 3. This figure includes an overvoltage suppression circuit and IGBT gate drive circuit. The overvoltage suppression circuit consists of the following parts: dynamic voltage rise rate feedback circuit composed of transient suppression diode $Z_{s1}$ and capacitor $C_1$, and improved active clamping circuit composed of transient suppression diodes $Z_{s2}$, $Z_{s3}$, $Z_{s4}$, capacitor $C_2$ and resistor $R_5$; IGBT grid drive circuit: a push-pull circuit composed of $T_1$ and $T_2$ triodes serves as the drive power amplifier of the grid, $R_1$ and $R_3$ are current limiting protection resistors, and OC1 is optocoupler for photoelectric isolation protection. In addition, $D_1$ and $D_2$ are universal diodes to prevent the IGBT gate signal from being shunted to the overvoltage suppression circuit.

3.2. Turn Off Voltage Spike Suppression Process

Before the IGBT is turned off, the whole circuit is in the on state, and the collector potential of the IGBT (Q4) is 0. Because of the action of the transient suppression diode, the active clamp and the dynamic voltage feedback circuit do not work. Figure 2 shows that at time $t_0$, the IGBT control signal is inverted, and the circuit operation process is as follows: The switching waveform does not change from $t_0$ to $t_1$, and the overvoltage suppression circuit stops working. The voltage and current of the IGBT at this stage meet the following requirements:

$$I_T\left(t\right)=i_L$$

(3)

$$V_{ce}\left(t\right)=V_{on}$$

(4)

where $V_{on}$ is the on-voltage drop of the IGBT in stage I.

From time $t_1$, $V_{ce}$ starts to rise, and when $V_{ce}$ rises to the breakdown voltage $U_{ZS4}$ of the transient suppression diode $Z_{s4}$, which is lower than the breakdown voltage of $Z_{s2}$, $Z_{s3}$ and $Z_{s4}$, $Z_{s4}$ is broken down, and capacitor $C_2$ begins to charge. Since $C_2$ is parallel to the Miller capacitance and much larger than the Miller capacitance, the Miller capacitance can be ignored, and the voltage rise speed of $V_{ce}$ can be slowed down. The voltage rise speed of $V_{ce}$ at this time can be expressed as follows:

$$\frac{\mathrm{d}{V}_{ce}}{\mathrm{d}t}=\frac{I_g}{C_2}$$

(5)

When $V_{ce}$ rises to the breakdown voltage $U_{ZS1}$ of $Z_{s1}$, $C_1$ starts to charge. The current $i_{C1}$ flowing through $C_1$ can be expressed as follows:

$$i_{C1}=C_1\frac{\mathrm{d}{U}_{ce}}{\mathrm{d}t}$$

(6)

$I_{C1}$ passes through resistor $R_4$. Because of the presence of the diode, $i_{C1}$ is fed back to the gate push–pull circuit composed of $T_1$ and $T_2$ to increase its current driving ability, reduce the falling rate of the gate voltage, and compensate for the delay of the entire active gate-driving circuit. At time $t_3$, $I_T$ starts to drop. The voltage drop rate of the gate at this time directly reflects the change rate of $I_T$, and the function of $i_{C1}$ is equivalent to increasing the value of $I_T$, reducing the discharge speed of the gate, lessening the change rate of $I_T$, and reducing the voltage spike; at the same time, since $V_{ce}$ exceeds the clamping voltage set by $Z_{s2}$, $Z_{s3}$ and $Z_{s4}$ at time $t_3$, the voltage spike appears, the transient suppression diodes $Z_{s2}$, $Z_{s3}$ and $Z_{s4}$ of the active clamping circuit are simultaneously broken down, and the active clamping circuit starts to work. The voltage spike is absorbed by the active clamping circuit and fed back to the IGBT gate, thereby raising the gate voltage, stopping $V_{ce}$ from rising, and finally falling and stabilizing near the DC bus voltage of the circuit until the entire off process is completed.

From the characteristic curve of the IGBT observed during the whole turning-off process of the IGBT, the main function of the dynamic voltage feedback circuit is to prolong the voltage rise time of $V_{ce}$. The main function of the active clamp circuit is to quickly react and compensate the IGBT gate after $V_{ce}$ reaches the voltage peak to pull down $V_{ce}$, avoid an excessive voltage peak and protect the circuit.

4. Parameter Influence of the Dynamic Voltage Feedback Circuit

The influence of the parameters of the dynamic voltage feedback circuit on the turn-off characteristics of the IGBT at each stage during the turn-off process is shown in

Table 1. Influence of parameters on turn-off characteristics at various stages.

Time	Regular Constant	Dynamic Voltage Feedback Parameters	Result
$t_0$∼$t_1$	$R_g$	None	Turn-off delay
$t_1$∼$t_2$	$R_g$	None	d$U_{ce}$/dt
$t_2$∼$t_3$	$R_g$ d$U_{ce}$/dt	$C_1$$R_4$$U_{ZS1}$	d$U_{ce}$/dt
$t_3$∼$t_4$	$R_g$ d$U_{ce}$/dt	$C_1$$R_4$	$\Delta U_{ce}$ d$I_c$/dt

. Among them, $\Delta U_{ce}$ is the difference between the off-voltage peak and the DC bus voltage, and $R_g$ is the off-resistance.

4.1. $C_1$ Impact Mechanism Analysis

As seen from Table 1, $C_1$, $R_4$ and $U_{ZS1}$ have the most important influence on the performance of the dynamic voltage feedback circuit. To deeply study the influence of $C_1$, $R_4$ and $U_{ZS1}$ on the dynamic voltage feedback circuit, we provide a basis for the parameter selection of the dynamic voltage feedback circuit, analyze the role of the dynamic voltage feedback circuit in each stage of the IGBT turn-off process, and list the corresponding expressions.

Table 1 shows that in stage III, $C_1$, $R_4$ and $U_{ZS1}$ influence the turn-off voltage rise rate. When the IGBT is turned off in stage III, its collector–emitter voltage can be expressed as follows:

$$V_{ce}\left(t\right)=V_{ge}\left(t\right)+V_{gc}\left(t\right)$$

(7)

Since $V_{ce}$ continues to rise at this time, its value is related to $V_{ge}$ and $V_{gc}$, and the values of $V_{ge}$ and $V_{gc}$ in stage III can be based on the following formulas:

$$\left\{\begin{array}{cc}\hfill & V_{gc}\left(t\right)=V_m-V_{ce-on}+\frac{1}{C_{gc}}\underset{t1}{\overset{t}{\int }}{i}_{gc}\left(t\right)\hfill \\ \hfill & V_{ge}\left(t\right)=V_L-I_g\left(t\right)•R_g\hfill \end{array}\right.$$

(8)

In Formula (8), $V_m$ is the Miller voltage, and $V_{ce-on}$ is the turn-on voltage of the IGBT. Since both voltages are fixed values, which are determined by the IGBT manufacturing process, the Miller capacitance $C_{gc}$ becomes an important factor at this time. After the dynamic voltage feedback circuit is added, after entering stage III, the transient suppression diode $Z_{s1}$ is reversely broken down, and capacitor $C_1$ begins to charge. At this time, the dynamic feedback circuit is turned on, and $C_1$ is equivalent to being connected in parallel with both ends of $C_{gc}$. The value is much larger than $C_{gc}$, raising the Miller capacitance value of the IGBT and thereby reducing $V_{gc}$. Since the dynamic voltage feedback circuit feeds back the gate current of the IGBT as $i_{C1}$, $I_g$(t) = $i_{C1}$ + $i_g$ increases accordingly, $V_{ge}$ decreases, and finally $V_{ce}$ decreases, suppressing the voltage spike.

When setting the value of capacitor $C_1$ constant, the current discharged through $C_1$ can be obtained from Formula (6), which acts on the push–pull circuit of the control pole, according to the output characteristic curve of the triode. When the triode works in the amplification area, the base current of the triode increases, the emitter current also increases, and finally, the IGBT gate current increases. According to Formula (8), $V_{ge}$ decreases, which reduces $V_{ce}$. From the changes in $V_{gc}$(t) and $V_{ge}$(t) in Formula (8), it can be concluded that when $R_4$ and $U_{ZS1}$ remain unchanged and $C_1$ increases, the values of $V_{ge}$ and $V_{gc}$ will decrease, resulting in a decrease in $V_{ce}$. The simulation platform shown in Figure 3 is built in SABER, and the simulation diagrams in Figure 4 and 5 represent the $V_{ge}$ and $V_{ce}$ turn-off waveforms corresponding to different $C_1$ values, respectively. The change in $C_1$ has a substantial impact on the turn-off voltage spike. Figure 4 shows that the larger the value of $C_1$ is, the lower the rising rate of $V_{ce}$, which reduces the voltage spike; Figure 5 shows that the larger the value of $C_1$ is, the smaller the drop rate of $V_{ge}$ will be. Additionally, the later the active clamp circuit will be triggered to work, the longer the time for raising the gate voltage at time $t_3$ will be, and at the same time, the smaller the gate voltage will be.

Set $R_4$ and $U_{ZS1}$ unchanged, change the value of $C_1$, and then conduct multiple groups of simulations to obtain the curve of voltage spike $V_{ce\left(max\right)}$ changing with $C_1$ as shown in Figure 6. It can be seen that when $C_1$ < 400 pF, the change of C1 has a significant impact on $V_{ce\left(max\right)}$; when $C_1$ > 400 pF, it has little effect on $V_{ce\left(max\right)}$. This shows that the suppression circuit can reduce the voltage spike, but can not completely eliminate the turn off voltage spike.

4.2. $R_4$ Impact Mechanism Analysis

$R_4$ mainly affects the charging and discharging time of the capacitor and the feedback current in the dynamic voltage feedback circuit, wherein the charging and discharging expression of the capacitor is as follows:

$$\left\{\begin{array}{c}\tau =RC\hfill \\ U_{CC}=U\times [1-e^{(-t/\tau )}]\hfill \\ U_{CD}=U_0\times e^{(-t/\tau )}\hfill \end{array}\right.$$

(9)

where $\tau$ is the charge time constant, U is the power supply voltage, $U_0$ is the voltage on the capacitor before discharge, $U_{CC}$ is the charge voltage value at time t on capacitor $C_1$, and $U_{CD}$ is the discharge voltage value of the capacitor.

The discharge current can be expressed as as follows:

$$I=U_{CD}/R$$

(10)

According to Formulas (9) and (10), $R_4$ affects the off-voltage spike. Changing the size of $R_4$ will affect the discharge voltage value of capacitor $C_1$ at any time and change the size of the feedback current, thus causing the rise rate of $V_{ge}$ to change and affecting the voltage spike of $V_{ce}$. Figure 7 and Figure 8 show the simulation waveform images of $V_{ce}$ and $V_{ge}$, respectively, when the size of $R_4$ is changed under the condition of constant $C_1$ and $U_{ZS1}$.

The also figure shows that with an increase in the value of $R_4$, the rising rate of $V_{ce}$ will be larger, resulting in a larger voltage spike of $V_{ce}$, which will trigger the active clamp circuit earlier, and at the same time, the falling rate of $V_{ge}$ will also be larger, resulting in $V_{ge}$ at time $t_3$, a larger voltage boost appears to suppress the voltage spike.

Change the size of $R_4$ for many times, keep $C_1$ and $U_{ZS1}$ unchanged, and get the curve of $V_{ce\left(max\right)}$ changing with $R_4$ as shown in Figure 9. It can be seen that $R_4$ has the same effect on $V_{ce\left(max\right)}$ as $C_1$, but the change rate of $V_{ce\left(max\right)}$ is small.

4.3. $U_{ZS1}$ Impact Mechanism Analysis

Setting the values of $C_1$ and $R_4$ as constant, the effects of different values of $U_{ZS1}$ on $V_{ce}$ and $V_{ge}$ are shown in Figure 10 and Figure 11. Through multiple groups of simulations, the curve of $V_{ce\left(max\right)}$ versus $U_{ZS1}$ in Figure 12 can be obtained.The effect of $U_{ZS1}$ on $V_{ce}$ is small. The figure shows that the smaller $U_{ZS1}$ is, the longer the duration of stage III, resulting in longer off-time, resulting in additional losses that do not affect the value of $V_{ce}$. At this time, the turn-off loss of the IGBT can be expressed as follows:

$$E_{off}=\underset{t_0}{\overset{t_3}{\int }}{u}_{ce}\left(t\right)·i_c\left(t\right)dt$$

(11)

Assuming that the rise of IGBT collector voltage in this process is linear, Equation (11) can be expressed as follows:

$$E_{off}=\frac{i_c·(t_3-t_0)·(u_{ce}\left(t_3\right)-u_{ce}\left(t_0\right))}{2}$$

(12)

$T_3$ and $t_0$ are the time points when the IGBT starts to turn on and completely turns off, respectively. Where $u_{ce}$(t) is the voltage of each time period when the IGBT is turned off and $i_c$(t) is the current of each time period when the IGBT is turned off. Since $u_{ce}$(t) and $i_c$(t) are related to $d{U}_{ce}$/dt, the additional loss caused by the IGBT increases with the decrease in $d{U}_{ce}$/dt of the IGBT.

5. Experimental Analysis

To test the influence of the parameters of the dynamic voltage feedback circuit on the voltage spike and gate voltage during the turn-off transient of the IGBT, the experimental platform shown in Figure 13 was built according to Figure 3 for the experiment, and the IGBT model GF10NC60KD was selected for test comparison and analysis. Its rated voltage is 600 V, collector current $i_c$ = 20 A ($T_j$ = 25 °C), saturation voltage drop $V_{CE\left(sat\right)}$ = 2.2 V, threshold voltage $V_{G\left(th\right)}$ =$4.5\sim 6.5$ V, gate drive voltage $V_{GE}$ = ±20 V. The input signal of the push–pull circuit selects 24V DC power supply. IGBT test input DC bus voltage $V_d$ = 300 V, and selects 300 V DC power supply with power of 1500 W as its input.

5.1. Influence of Capacitance on the Performance of a Dynamic Voltage Feedback Circuit

To analyze the suppression effect of capacitance on the IGBT voltage spike and the influence of the gate signal in the dynamic voltage feedback circuit, set $U_{ZS1}$ = 100 V, $R_4$ = $100\mathsf{\Omega }$, $U_{ZS2}$ = 300 V, where $U_{ZS2}$ is the clamping voltage set by $Z_{S2}$, $Z_{S3}$ and $Z_{S4}$ in the circuit. We obtain the waveform images of $V_{ce}$ and $V_{ge}$ in Figure 14 when $C_1$ = 100 pF, and key parameters of IGBT shutdown in

Table 2. Influence of $C_1$ on the turn off characteristics.

${\mathit{C}}_1$	${\mathit{R}}_4$	${\mathit{U}}_{\mathit{ZS}1}$	${\mathit{t}}_3$-${\mathit{t}}_0$	${\mathit{V}}_{\mathit{ce}}$
100 pF	100 Ω	100 V	550 ns	382 V
500 pF	100 Ω	100 V	1080 ns	346 V

, where $V_{ce}$ is measured with the $\times 10$ probe of the oscilloscope. Figure 15 is a waveform image when only $C_1$ = 500 pf is changed. A comparison shows that the change in $C_1$ has a significant impact on the voltage spike of $V_{ce}$. When $C_1$ = 100 pF, the maximum value of $V_{ce}$ is 382 V, and when $C_1$ = 500 pF, the maximum value of $V_{ce}$ is 346 V. First, the larger the value of $C_1$ is, the longer the time from $t_0$ to $t_3$ will be, which will lead to a decrease in d$i_c$/dt, and in turn reduces the voltage spike of $V_{ce}$, which has a better suppression effect. At this time, the dynamic voltage feedback circuit behaves as a pair of d$i_c$/dt suppression effects of the IGBT.

The main function of the feedback signal of the dynamic voltage feedback circuit is to increase the gate signal, which is manifested as the influence of increasing the slope of d$V_{ge}$/dt, while the active clamp circuit manifests as a direct lift effect on the gate signal. When the IGBT turn-off voltage exceeds the $U_{ZS2}$ set by the active clamp circuit, the gate signal will have a substantial rise. The experimental waveforms with $C_1$ of 100 pF (Figure 14) and 500 pF (Figure 15) show that the larger the value of $C_1$ is, the smaller the d$V_{ge}$/dt, the longer the time for $V_{ce}$ to reach the voltage peak, and the later the time to trigger turning on the active clamp circuit.

5.2. Effect of Resistors on the Performance of Dynamic Voltage Feedback Circuits

We set $U_{ZS1}$ = 100 V, $U_{ZS2}$ = 300 V, $C_1$ = 100 pF, change the value of $R_4$, and obtain the IGBT turn-off waveform when $R_4$ = $10\mathsf{\Omega }$, as shown in Figure 16, and key parameters in

Table 3. Influence of $R_4$ on the turn off characteristics.

${\mathit{C}}_1$	${\mathit{R}}_4$	${\mathit{U}}_{\mathit{ZS}1}$	${\mathit{t}}_3$-${\mathit{t}}_0$	${\mathit{V}}_{\mathit{ce}}$
100 pF	10 Ω	100 V	2200 ns	368 V

are obtained. Compared with the turning-off waveform of the IGBT when the resistance $R_4$ = $100\mathsf{\Omega }$ in Table 2, it was found that as the resistance $R_4$ decreases from $100\mathsf{\Omega }$ to $10\mathsf{\Omega }$, the turning-off voltage peak of the IGBT decreases from 382 V to 368 V, and the rising slope of the IGBT $V_{ce}$ decreases during the turning-off process. According to the analysis in Chapter 3, this decrease occurs because increasing the resistance prolongs the charge and discharge time of the capacitor and reduces the current fed back to the gate.

The influence of resistance on the gate signal in the dynamic voltage feedback circuit is analyzed. Compared with $R_4$ = $100\mathsf{\Omega }$ (Figure 14) and $R_4$ = $10\mathsf{\Omega }$ (Figure 16), the change in $R_4$ affects the change in $V_{ge}$. The smaller the $R_4$ value is, the slower the decline rate of $V_{ge}$. In Figure 11, $t_3$-$t_0$ = 550 ns; in Figure 13, $t_3$-$t_0$ = 2.2 µs. During the IGBT off process, with the decrease in $R_4$, the feedback signal of the gate increases, which decreases d$V_{ge}$/dt, and finally extends the time beyond the DC bus voltage $V_d$ to reduce the voltage spike. The gate needs to feed back a small voltage signal through the active clamp circuit to suppress the voltage spike.

5.3. Effect of UZS1 on the Performance of the Dynamic Voltage Feedback Circuit

Figure 17 shows the waveform images of $V_{ce}$ and $V_{ge}$ of the IGBT in the off process when $U_{ZS1}$ = 100 V, $R_4$ = 100 Ω, $U_{ZS2}$ = 300 V, $C_1$ = 100 pF and $U_{ZS1}$ = 60 V are changed. From the key parameters in

Table 4. Influence of $U_{ZS1}$ on the turn off characteristics.

${\mathit{C}}_1$	${\mathit{R}}_4$	${\mathit{U}}_{\mathit{ZS}1}$	${\mathit{t}}_3$-${\mathit{t}}_0$	${\mathit{V}}_{\mathit{ce}}$
100 pF	100 Ω	60 V	740 ns	386 V

, it can be seen that $U_{ZS1}$ has little effect on the voltage spike of $V_{ce}$. After the value of $U_{ZS1}$ is increased from 30 V to 60 V, the voltage spike of $V_{ce}$ is 386 V, which is almost unchanged. In addition, the smaller $U_{ZS1}$ is, the longer the time from time $t_0$ to time $t_3$. In Figure 14, $t_3$-$t_0$ = 550 ns, while in Figure 17, $t_3$-$t_0$ = 740 ns, which leads to an extension of the off time of the IGBT and further generates additional losses.

6. Conclusions

(1)

Aiming at the problem of off-voltage spikes in IGBT applications, a voltage spike suppression circuit combining dynamic voltage feedback and an active clamp is proposed. The voltage rise rate of the IGBT is fed back by the capacitor to solve the problem of feedback signal delay in the circuit. Combined with the active clamp circuit, the voltage spike is suppressed to ensure safe and reliable operation of the IGBT.

(2)

Research and analysis show that adjusting $C_1$ and $R_4$ in the dynamic voltage feedback circuit can clearly suppress the off-voltage spike.

(3)

The experimental results show that by increasing the value of $C_1$ and decreasing the value of $R_4$, the signal fed back to the IGBT gate by the dynamic voltage feedback circuit is increased to reduce the voltage rise rate and the turn-off voltage peak of the IGBT during the turn-off process. Changing $U_{ZS1}$ cannot reduce the off-voltage spike of the IGBT.