Performing Arithmetic Operations with Locally Homogeneous Spiking Neural P Systems

Abstract

The parallelism of rule execution in membrane computing provides support for improving computational efficiency. Membrane computing models have been applied in many fields. In arithmetic operations, designing basic arithmetic operation spiking neural P systems using fewer neurons and rule types has been an important field of membrane computing application research in recent years. We discuss the application of locally homogeneous spiking neural P systems in arithmetic operations. The purpose is to design a spiking neural P system with fewer neurons and rule types to perform arithmetic operations. We designed the addition and subtraction of a locally homogeneous spiking neural P system without weight and delay. They include two input neurons to achieve any two binary number subtraction, one input neuron to achieve any two binary number addition and subtraction, and one input neuron to achieve any n binary number addition and subtraction. This is an attempt to apply the locally homogeneous spiking neural P system in arithmetic operations. Compared with the current excellent spiking neural P system performing arithmetic operations, our designed locally homogeneous spiking neural P system is more concise. The system we designed reduces the number of neurons required for n number addition operations by k − 6 and reduces the number of rule types by 5k − 14.

1. Introduction

Membrane computing [1,2] is one of the newest branches of biological computing. Membrane computing is inspired by cells and neural networks in the human body. The aim is to abstract the computational model from the way that living cells process compounds in a hierarchical structure, and obtain a new distributed and parallel computational model, which is called the P system. The spiking neural P system [3] (in short SN P system) is a biological computing system established with the idea of membrane computing. SN P system is one of the main types of P system. SN P system has the advantages of distribution, parallelism, and uncertainty. It provides a new algorithm model for biological system modeling and simulation. It also introduces new computational ideas and methods to computer science.

The spiking neural P system [1] consists of neurons, synapses, spikings, and rules. Intuitively, the SN P system is usually to represented as a graph. In the graph, nodes denote neurons, edges between nodes denote synapses, spikings and rules are seen as properties of nodes. Neurons are connected by synapses. Neurons send or receive spiking along the synapses. Rules in a neuron are designed according to its function. In each time slice, each neuron with an applicable rule must use and can use only one rule [4]. The spiking neural P system achieves computation with great parallelism of rule execution among neurons, resulting in powerful computational power. In recent years, researchers have proposed several variants of the SN P systems, which also have high computational performance and computational completeness. For example, a homogeneous SN P system with the same set of rules in each neuron. The Materials and Methods should be described with sufficient details to allow others to replicate and build on the published results. For example, ref. [5] proposed a homogeneous SN P system HSNPS with the same rule set in each neuron. Ref. [6] proposed a weighted fuzzy spiking neural P system WFSNPS, which can represent and process fuzzy and uncertain knowledge. Ref. [7] proposed an SN P systems RSSNPS that uses synapses as processors (synapses with rules). Ref. [8] proposed an astroglial spiking neural P system SNPAS composed of astrocytes and neurons. Ref. [9] proposed an SN P system ESNPS for combinatorial optimization problem solving with selection probability. Ref. [10] proposed an SN P system SNPSPS for synaptic remodeling accomplished by the invocation of rules in neurons. Ref. [11] proposed an adaptive optimization SN P system AOSNPS.

Homogeneous spiking neural P system (in short HSNP systems) is a new type of SN P system derived from the development of SN P systems. It has become one of the hotspots of membrane computing in recent years. Pan Linqiang et al. proposed the concept of HSNPS in the homogeneous spiking nervous P system in [5]. All neurons in the new SN P system are unified. All neurons in the P system have the same rule set. Since HSNPS was proposed, many variants of HSNP systems and different modes of operation have been studied. For example, ref. [12] proves that the HSNP system is universal as both generator and receiver in a sequential mode with a maximum number of spikes. Ref. [13] studied the small universal HSNP system with weights. Ref. [14] studied the HSNP system with reverse spiking without delay rule and synaptic weight. In [15], the HSNP system without delay rule is studied under the two conditions of weighted and unweighted synapses. Ref. [16] studied the number of neurons needed when the HSNP system works with maximum sequence and maximum spiking. Ref. [17] studied that the HSNP system with inhibitory synapses can reduce the types of neurons in the system. Ref. [18] applied the no-amnesia rule and HSNP system with astrocytes in the design of the logic gate, and constructed a more complex Boolean circuit. Ref. [19] verifies that the locally homogeneous spiking neural P system (LHSNP system) with the same set of rules for neurons in the same module can reduce the execution time of the system. HSNP systems with spikes and the same set of rules are studied in [20]. The HSNP system with structural plasticity that can delete and generate synapses has been studied in [21]. Ref. [22] studied the tag language generation method of the HSNP system with structural plasticity. Ref. [23] studied locally homogeneous SN P systems with local neurons having the same set of rules.

The research on arithmetic operations in the HSNP system is the foundation of the application research of the HSNP systems. At present, although there are more theoretical studies based on HSNP systems, there are fewer studies on the application of HSNP systems, especially arithmetic operations. The research results that can be used for reference mainly come from the research on arithmetic operations in SN P systems. For example, ref. [24] investigated SN P systems with n input neurons for addition, subtraction, and multiplication operations. Ref. [25] studied an SN P system with one input neuron and no weights in the synapse to perform the product of n natural numbers and any two natural numbers multiply. Ref. [26] studied an SN P system with multiple input neurons. It can perform integer arithmetic operations with signed operands. Refs. [27,28] studied an SN P system with multiple input neurons and takes the time interval between two spikings as the calculation result. They can perform arithmetic operations on any two natural numbers. Refs. [29,30] studied SN P systems with anti-spiking. It can perform addition and subtraction of symmetric three-valued integers. Ref. [31] studied an SN P system that uses CMOS circuits to implement the arithmetic module. Ref. [32] studied an SN P system with multiple input neurons and no delay. It can perform arithmetic operations. An SN P system with four neurons controlled by astrocytes was implemented through an arithmetic circuit [33]. An SN P system with rule sets and weights at synapses for calculating the maximum common divisor [34].

The fact that each neuron in the HSNP system has the same structure provides good support for the implementation of SN P systems. However, this also makes it difficult to represent the complexity and diversity of the computational process using the HSNP system. We studied the SN P system for performing arithmetic operations based on the LHSNP system. Our main contributions are as follows:

① This LSHNP system was designed to perform arithmetic operations and has no weight or delay. And we have added overflow monitoring neurons to monitor the overflow of calculation results in the system.

② We designed two LHSNP systems for addition. They are an LHSNP system with one input neuron that performs any two k-bit binary number addition operations. And an LHSNP system with one input neuron that performs any n k-bit binary number addition operations.

③ We designed three LHSNP systems for subtraction. LHSNP systems with multiple input neurons perform any 2 k-bit binary number subtraction operations. An LHSNP system with one input neuron can perform any 2 k-bit binary number subtraction operations. An LHSNP system with one input neuron can perform any n k-bit binary number subtraction operations.

The rest of the paper is structured as follows. Section 2 gives a brief description of the SN P system. In Section 3, we discussed the design of two LHSNP systems for addition, and in Section 4 we discussed the design of three LHSNP systems for subtraction. In Section 5, the conclusions of this paper and the issues to be further investigated are given.

2. Related Research

2.1. Spiking Neuronal P System

An SN P system of degree m (m ≥ 1) composed of five elements: the singleton alphabet, the neurons, the set of synapses, the input neurons, and the output neurons is a construct of the form [3]:

П = (O, σ₁, σ₂, …, σ_m, syn, in, out)

(1)

where:

• O = {a} is the singleton alphabet, and a is spiking;
• σ₁, σ₂, …, σ_m are neurons of the form σ_i = (n_i, R_i), 1 ≤ i ≤ m, n_i is the initial number of spiking in the neuron σ_i at the beginning of the calculation, n_i ≥ 0. R_i is the finite set of rules in each neuron. R_i has two forms of rules (we collectively refer to them as spiking rules):

①

E/a^c → a^p; d, where E is a regular expression over O, c ≥ 1, p ≥ 1, and c ≥ p, d indicates delayed time, d ≥ 0;

②

E′/a^s → λ, s ≥ 1, for any rule E/a^c → a^p; d from any R_i, all meet the condition L(E)∩L(E′) = Φ;

• syn is the set of synapses. The element in syn is an ordered pair of elements shaped like (i, j). (i, j) indicates neurons σ_i to σ_j are connected by synapses, with i, j ∈ {1, 2, …, m}, i ≠ j;
• in, out ∈ {1, 2, …, m} indicate the input and output neurons.

In the SN P system, E/a^c → a^p; d is called a generalized firing rule. If L(E) = {a^c}, then the rule can be written in the simplified form a^c → a^p; d. If p = 1, then the rule E/a^c → a; d is called the standard firing rule. If p = 1 and d = 0, then the rule can be written in the simplified form E/a^c → a. E′/a^s → λ is called the forgetting rule. If L(E) = {a^s}, then the rule can be written in the simplified form a^s → λ.

In this work, we use the no delayed rule (i.e., d = 0). Spiking rules are applied as follows: if at a time slice, neuron σ_i contains k spikings and a^k ∈ L(E), k ≥ c, then the rule E/a^c → a^p ∈ R_i is enabled, σ_i is fired. σ_i will consume c spikings (only k-c spikes remain in σ_i) and send p spikings to all neurons connected to it. When σ_i contains s spikings (s ≥ 1), activating the forgetting rule a^s → λ ∈ R_i in σ_i. σ_i consum s spikings and do not send spikings to any neurons connected to it.

When all neurons in an SN P system have the same firing and forgetting rules, the system is called a homogeneous SN P system (HSNP system) [5]. The limitation of the HSNP system is that it is difficult to express efficient computation in the absence of redundant rules in neurons. For example, a binary adder with two input neurons can not be represented by an HSNP system without redundant rules. Therefore, this paper will study the local HSNP system (LHSNP system).

If the neurons in the system can be divided into several groups, and the neurons in each group use the same rules without redundancy, then we call it the LHSNP system. The goal of designing an LHSNP system that can perform effective calculations is to use the fewest number of neurons and the fewest number of neuronal groups in the system. For example, Formula (2) is an LHSNP system П_Add1 with two input neurons that can perform binary addition.

П_Add1 = (O, σ_in1, σ_in2, σ_Add, syn, Input₁, Input₂, out)

(2)

where:

(1)

O = {a};

(2)

σ_in1 = (0, R_in);

(3)

σ_in2 = (0, R_in);

(4)

σ_Add = (0, R_Add);

(5)

syn = {(in₁, Add), (in₂, Add)};

(6)

in₁ = Input₁, in₂ = Input₂;

(7)

out = Add;

(8)

R_in = {a$\to$a}, R_add = {a$\to$a, a²/$\mathrm{a}\to \lambda$, a³/a²$\to$a}.

2.2. Related Literature

The arithmetic operations we discussed in the article are performed in the eld of natural numbers (integers not less than 0) or their binary representation. The natural number N can be expressed as the k-bit binary number shown in Formula (3). The 2ⁱ (0 ≤ i ≤ k − 1) is called the bit weight, and aⁱ is the value of the i + 1 bit (0 ≤ i ≤ k − 1).

N = a₀*2⁰ + a₁*2¹ + a₂*2² + a₃*2³ + … + a_k−1*2^k−1

(3)

In the LHSNP system, we assume that the system has a global clock to realize the synchronous execution of neuronal rules in parallel, with each rule executed in a time slice. The LHSNP system we designed to perform addition arithmetic operations is mainly compared to [25,34], and the LHSNP system that performs subtraction operations is mainly compared to [23].

Zhang Xingyi designed an SN P system with one input to perform n natural number addition in [25], which is weightless and has a delay. This SN P system with 3k + 5 neurons and 9 rule types requires (n + 1) k + 4 time slices to complete addition operations.

Wang Huifang designed an SN P system with one input to perform n natural number addition in [34], which has weights and delays. This SN P system with 2k + 4 neurons and 5k − 1 rule types requires a 5k − 1 time slice to complete addition operations.

Zeng Xiangxiang designed an SN P system with multiple inputs to perform two natural number subtraction in [23], which has no weight and delay. This SN P system with 12 neurons and 4 rule types requires a time slice that is free.

3. An Locally Homogeneous Spiking Neural P System for Addition

In this section, we will present two kinds of LHSNP systems with one input neuron. It can perform k-bit (k ≥ 4) binary number addition. They, respectively, perform addition operations on two numbers and on multiple numbers. In our designed system, if the representation of k-bit (k ≥ 4) binary numbers is less than k bits, the high bits of the binary numbers are automatically zeroed in.

The binary numbers involved in the calculation are input in order from low to high. The binary number 0 represents 0 spiking. The binary number 1 represents 1 spiking. The calculation results are output in the form of a spiking sequence (0 spiking represents binary number 0, 1 spiking represents binary number 1, and 4 spikings represent data overflow) to the environment.

3.1. An LHSNP System with 1 Input Neuron for 2 Numbers Addition

An LHSNP system П_Add2 with one input neuron as Formula (4). The structure of П_Add2 is shown in Figure 1. In Figure 1, the solid arrows represents the directed connection between two neurons. The dashed arrows indicates the omission of connections between multiple neurons. П_Add2 design idea is as follows: ① Input part of the system is divided into two modules, which are the input module and the input cache module. The input module is composed of an input assist module and an input selection module. The input module controls the input of the summand and addend. It controls the summand through the auxiliary neuron σ_aux3 transmitted, and the addend through the additive neuron σ_addend transmitted. When the summand input is completed and the addend input begins, with the assistance of the input auxiliary module, blocking addend pass through σ_aux3, and firing addend auxiliary neuron σ_addend to transmit addend numbers. ② Auxiliary neuron σ_aux4 monitors the input of the highest bit of two binary numbers. When the highest bit of these two binary numbers arrived in the addition neuron σ_Add. Auxiliary neurons σ_aux4 mark the highest bit corresponding spiking. ③ Summand and addend are calculated in the adder σ_Add and the calculation result is sent to the environment. ④ Overflow monitoring neuron σ_OF monitors the calculation results whether overflow.

The rules of П_Add2 are divided into four groups: (1) Homogeneous neurons: auxiliary neurons, summand catch neurons, and input neurons use rule set R_aux = {a → a}. (2) Overflow monitoring neurons σ_aux4 uses rule set R_aux4 = {a^{k + 1} → a⁴}. (3) Addend neuron σ_addend uses rule set R_addend = {a → ƛ; a² → ƛ; a³ → a}. (4) Adder neuron σ_Add uses ruleset R_Add = {a → a; a²/a → ƛ; a³/a² → a; a⁵ → a⁴}.

The formal definition of П_Add2 is as Formula (4):

П_Add2 = (O, σ_in, σ_addend, σ_aux1,0, σ_aux1,1, …, σ_{aux1,k + 1}, σ_aux2,0, σ_aux2,1, σ_aux3, σ_aux4, σ_sum0, σ_sum1, …, σ_sumk−1, σ_Add, syn, Input, out)

(4)

where:

(1)

O = {a};

(2)

σ_in = (0, R_aux);

(3)

σ_addend = (0, R_addend);

(4)

σ_aux1,i = (1, R_aux), i = 0, 1;

(5)

σ_aux1,i = (0, R_aux), i = 2, …, k + 1;

(6)

σ_aux2,i = (0, R_aux), i = 0, 1;

(7)

σ_aux3 = (0, R_aux);

(8)

σ_aux4 = (0, R_aux4);

(9)

σ_sumi = (0, R_sum), i = 0, …, k − 1;

(10)

σ_Add = (0, R_Add);

(11)

syn = {(in, aux₃), (in, addend), (addend, Add), (aux_1,1, aux_1,0), (aux_{1,k + 1}, aux_2,0), (aux_{1,k + 1}, aux_{2, 1}), (aux_2,0, aux₃), (aux_2,1, aux₃), (aux_2,0, addend), (aux_2,1, addend), (aux_2,0, aux_1,0), (aux_2,0, aux_1,1), (aux_2,1, aux₄), (aux₄, Add), (aux₃, sum_k−1), (sum₀, Add)}∪{aux_1,i, aux_{1,i + 1}}|i ∈ {0, 1, …, k}∪{sum_{i + 1}, sum_i}|i ∈ {0, 1, …, k − 2};

(12)

in = Input;

(13)

out = Add.

Analysis of П_Add2 and its rule set shows that П_Add2 contains 8 rules and 2k + 9 neurons. Performing the addition operation of 2 k-bit binary numbers requires 2k + 3 time slices. Furthermore, we have the following conclusions:

Theorem 1.

П_Add2 with 1 input neuron can perform any 2 k-bit binary number addition. In other words, П_Add2 after receiving the spiking corresponding to each binary number bit in order from low to high, П_Add2 can correctly perform addition and output the results to the environment.

Proof of Theorem 1.

Let t represent time slice. At the initial state t = 0, there is one spiking in σ_aux1,0 and σ_aux1,1. Starting from t = 1 time slice, two binary addends are in order received by σ_in from low to high. When the binary bit is 1, σ_in received 1 spiking, otherwise σ_in received 0 spiking. The corresponding binary bit of the summand are sequentially passed to σ_Add along σ_aux3, σ_sumi (0 ≤ i ≤ k − 1) in summand cache module. The addend are sequentially passed to σ_Add through σ_addend. The calculation process of П_Add2 is as follows:

①

Input Auxiliary Module

The function of the input auxiliary module is to distinguish the summand from the addend. t = 1 to k + 1, the input auxiliary module does not generate spiking output. During this period, the spiking from σ_in (each bit of summand) is sent to the summand cache module through σ_aux3. σ_addend consumed these spiking using rule a→λ. At t = k + 2 time slice, σ_aux2,0 and σ_aux2,1, respectively, send 1 spiking to σ_aux3. Maintain at least 2 spikings in σ_aux3. This prevents the addition input by σ_in from entering the neurons of the summand cache module. At the same time, σ_addend received two spikings from σ_aux2,0 and σ_aux2,1, at least two spikings in σ_addend. Thereby enabling the addend bit to enter σ_Add to perform addition operations. The operation process of the input auxiliary module is as follows:

(1)

At t = 0 time slice, there is 1 spiking in σ_aux1,0 and σ_aux1,1.

(2)

t = 1 to k + 1, σ_aux1,0 and σ_aux1,1 send 1 spiking to each other and maintain 1 spiking. At the same time, σ_aux1,1 send 1 spiking to σ_aux1,2, which will follow the neurons σ_aux1,3, σ_aux1,4, …, σ_{aux1, k + 1} sequential transmission. The input auxiliary module has no spiking output. At t = k + 1 time slice, there is 1 spiking in homogeneous neurons in the input auxiliary module.

(3)

t = k + 2 to 2k + 3, the input auxiliary module continues to generate spiking output. σ_aux2,0 send 1 spiking to σ_aux1,0 and σ_aux1,1 at each time slice to prevent σ_aux1,0 and σ_aux1,1 from continuously generating spiking. At t = k + 3 to 2k + 2 time slice, the spikings in σ_aux1,2, σ_aux1,3, …, σ_{aux1,k + 1} are sequentially cleared. At t = 2k + 3 time slice, the spikings in σ_aux2,0 and σ_aux2,1 are cleared. And there are no rules that can be fired in all neurons in the input auxiliary module.

②

Summand Input

The summand bits sent by σ_in transferred to σ_Add along σ_aux3, σ_sumi (0 ≤ i ≤ k − 1). At t = 1 to k + 2 time slice, the summand cache module does not generate spiking output. At t = k + 3 to 2k + 2 time slice, σ_sum0 sends the corresponding spiking of each summand to σ_Add at each time slice. The transmission process of the summand is as follows:

(1)

t = 1 to k, the spiking corresponding to each summand bit is received by σ_in in order from low to high. At t = k time slice, the input of the summand is completed. These spikings follow σ_aux3, σ_sumk−1, σ_sumk−2, …, σ_sum0 sequential transmission to σ_Add.

(2)

t = k + 1 to k + 2, the summand cache module does not generate spiking output. At t = k + 2 time slice, the bits of the summand are stored in σ_sum0, σ_sum1, …, σ_sumk−1 in order from low to high. At the same time, σ_aux3 starts continuous reception spikings from σ_aux2,0, σ_aux2,1, and σ_in. Until 2k + 3 time slice, these spikings are piled up in σ_aux3.

(3)

t = k + 3 to 2k + 2, the summand cache module continuously generates spiking outputs. At each time slice, σ_sum0 sends the corresponding spiking of each summand to σ_Add in sequence. At the same time, the spiking in σ_sumk−1, σ_sumk−2, …, σ_sum0 are sequentially cleared. Starting from 2k + 2 time slice, there are no rules that can use in the transmit addend neurons.

③

Addend Input

The spiking corresponding to each addend sent by σ_in is sent to σ_Add through σ_addend. At t = 1 to k + 2 time slice, σ_Add does not generate spiking output. At t = k + 3 to 2k + 3 time slice, σ_addend sends the corresponding spiking of each addend bit to σ_Add at each time slice. The transmission process of σ_addend is as follows:

(1)

t = 1 to k + 2, σ_addend does not generate spiking output. During this time, σ_addend received spiking sent by σ_in is consume by forgetting rule a → ƛ.

(2)

t = k + 1 to 2k, the spiking corresponding to each binary addend is transmitted in order from low to high send to σ_in. At t = 2k time slice, the addend input is completed. These spikings through σ_addend transferred to σ_Add.

(3)

t = k + 2 to 2k + 1, σ_addend receives spikings sent by σ_in. At each time slice, σ_Add also receives 2 spikings sent by σ_aux2,0 and σ_aux2,1. With the assistance of σ_aux2,0 and σ_aux2,1,σ_addend send spiking to σ_Add transmission addend. During this time slice, if there are 2 spikings in σ_addend, σ_addend use the forgetting rule a² → ƛ consuming 2 spikings and sending 0 spikings out. Indicates that the binary addend passed is 0₂. If there are 3 spikings in σ_addend, firing rule a³ → a, consume 3 spikings and send 1 spiking out, indicating that the binary addend passed is 1₂. At t = k + 3 time slice, the spiking corresponding to the lowest bit of the addend is sent to σ_Add. At t = 2k + 2 time slice, the spiking corresponding to the highest bit of the addend is sent to σ_Add.

④

Data Overflow Detection

The way to detect data overflow in σ_Add is to use 4 spikings sent by σ_aux4 to detect whether the highest bit of the 2 addends have carry after calculation in σ_Add. If there is a carry, then σ_Add firing rule a⁵ → a⁴ and send 4 spikings to the environment to indicate data overflow. The input process for data overflow monitoring is as follows:

(1)

t = 1 to k + 1, σ_aux4 has no spiking input.

(2)

t = k + 2 to 2k + 2, σ_aux4 received 1 spiking sent by σ_aux2,1 at each time slice. These spikings are stacked in σ_aux4. At t = 2k + 2 time slice, σ_aux4 accumulated k + 1 spikings.

(3)

t = 2k + 3, σ_Add received four spikings sent by σ_aux4 firing rule a^{k + 1} → a⁴. At the same time, σ_aux4 received 1 spiking sent by σ_aux2,1, which accumulates in σ_aux4 until the system stops. If there are 4 spikings in σ_Add, it means that the calculation result does not overflow. If there are 5 spikings in σ_Add, it indicates that the calculation result overflows. σ_Add use the rule a⁵ → a⁴ to send 4 spikings to the environment.

⑤

Addition Operation

Two addends are sent to σ_Add in order of binary bits from low to high. At t = k + 3 to 2k + 2 time slice, the spiking corresponding to each of the two addends is sent to σ_Add. At t = k + 4 to 2k + 3 time slice, σ_Add send the calculation results to the environment. If 1 spiking is received in the environment, it represents binary number 1. If 0 spiking is received in the environment, it represents binary number 0. If 4 spikings are received in the environment at 2k + 4 time slices, it indicates data overflow. The design idea of σ_Add is as follows: 1 spiking represents the binary number 1, and 0 spiking represents the binary number 0. If there is a carry generation after addition, retain 1 spiking in σ_Add to indicate carry 1. The corresponding formulas for each rule in σ_Add are as follows:

(1)

Rule a → a indicates performing addition operation: 1₂ + 0₂ = 1₂ or performing addition operation 0₂ + 0₂ + 1₂ = 0₂(there are carry reservations in σ_Add). There are two types of sources for this spiking in σ_Add. Case 1: This 1 spiking comes from σ_sum0 or σ_addend. It indicates that the two binary addends input are 0 and 1. Case 2: This spiking comes from reserved in σ_Add, and the two addends are 0. At this point, σ_Add is fired using rule a → a, consumes 1 spiking and generates 1 spiking, and sends it to the environment.

(2)

Rule a²/a → ƛ indicates performing an addition operation: 1₂ + 1₂ = 10₂, or 1₂ + 0₂ + 1₂ = 10₂ (there is carry reservation in σ_Add). There are two sources of these two spikings in σ_Add. Case 1: these two spikings come from σ_sum0 and σ_addend. This indicates that the two binary addends input are 1 and 1. Case 2: one spiking comes from σ_sum0 or σ_addend, another spiking from σ_Add (i.e., carry 1). At this point, σ_Add is fired using rule a²/a → ƛ, consume 1 spiking, retain 1 spiking (i.e., carry 1), and send 0 spiking to the environment.

(3)

Rule a³/a² → a indicates performing an addition operation: 1₂ + 1₂ + 1₂ = 11₂. These 3 spikings come from σ_sum0 and σ_addend (the 2 binary addends input are 1 and 1) and 1 spiking reserved in σ_Add (i.e., carry 1). At this point, σ_Add is fired using rule a³/a² → a, consumes 2 spikings, retains 1 spiking (i.e., carry 1), generates 1 spiking, and sends it to the environment.

(4)

Rule a⁵ → a⁴ indicates data overflow. Among these 5 spikings, 4 spikings come from σ_aux4, and 1 spiking comes from the two addends with the highest bits after calculation retained in σ_Add (i.e., carry 1). At this point, rule a⁵ → a⁴ is fired in σ_Add, which consumes 5 spikings and generates 4 spikings to be sent to the environment.

In summary, П_Add2 can correctly perform the sum of 2 k-bit binary numbers. □

To illustrate the operation process in П_Add2, an example is used to calculate the sum of 5 and 6. If the number of bits in the current system is 8, then 5 + 6 = 11 is represented as 00000101₂ + 00000110₂ = 00001011₂ in П_Add2. During the calculation process, the number of spiking in all neurons at each time slice and the number of spiking sent to the environment are shown in

Table 1. The number of spiking of all neurons in the П_Add2 and the number of spiking sent to the environment during the calculating of 00000101₂ + 00000110₂ = 00001011₂.

t	in	aux3	sum7	sum6, …, sum1	sum0	aux1,0	aux1,1	aux1,2	aux1,3, …,aux1,8	aux1,9	aux2,0	aux2,1	aux4	addend	Add	out	OF
t = 0	-	0	0	…	0	1	1	0	…	0	0	0	0	0	0	-	0
t = 1	1	0	0	…	0	1	1	1	…	0	0	0	0	0	0	-	0
t = 2	0	1	0	…	0	1	1	1	…	0	0	0	0	1	0	-	0
t = 3	1	0	1	…	0	1	1	1	…	0	0	0	0	0	0	-	0
t = 4	0	1	0	…	0	1	1	1	…	0	0	0	0	1	0	-	0
5,…,8	…	…	…	…	…	…	…	…	…	…	…	…	0	…	…	…	…
t = 9	0	0	0	…	0	1	1	1	…	1	1	1	0	0	0	-	0
t = 10	1	2	0	…	1	2	2	1	…	1	1	1	1	2	0	-	0
t = 11	1	5	0	…	0	3	3	0	…	1	1	1	2	3	1	-	0
t = 12	0	8	0	…	1	4	4	0	…	1	1	1	3	3	1	1	1
t = 13	0	10	0	…	0	5	5	0	…	1	1	1	4	2	2	1	1
t = 14	0	12	0	…	0	6	6	0	…	1	1	1	5	2	1	0	0
t = 15	0	14	0	…	0	7	7	0	…	1	1	1	6	2	0	1	1
16,…,18	…	…	…	…	…	…	…	…	…	…	…	…	…	…	…	…	…
t = 19	-	22	0	…	0	11	11	0	…	0	0	0	1	2	4	0	0

. In Table 1, “t” represents the time slice, and in represents the number of spiking in σ_in. “in” represents the number of spiking in neuron σ_in. “aux₃” and “aux₄” represent the number of spiking in auxiliary neurons σ_auxi (i = 3, 4). “aux_1,i (0 ≤ i ≤ 9) ”and “aux_2,i (0 ≤ i ≤ 1)” represent the number of spiking in auxiliary neurons σ_auxj,i (1 ≤ j ≤ 2, 0 ≤ i ≤ 9). “sum_i” represents the number of spiking in the auxiliary neuron σ_sumi (0 ≤ i ≤ 7). “addend” represents the number of spiking in additive neuron σ_addend. “Add” represents the number of spiking in the addition operation neuron σ_Add. “out” represents the number of spiking sent to the environment. “sum₆ … sum₁” indicates the omission of presenting spiking in σ_sum1 to σ_sum6. “aux_1,3 … aux_1,8” indicates the omission of spiking in σ_sum1,3 to σ_sum1,8. The two binary addends input and the calculation results are represented in bold font.

The process of calculating the sum of 00000101₂ and 00000110₂ in П_Add2 is as follows:

①

Input Auxiliary Module

The spiking in the auxiliary module send by σ_aux1,1 is transmitted along σ_aux1,2, σ_aux1,3, …, σ_aux1,9. All of them are homogeneous neurons, and the transmission situation of each neuron is similar. Therefore, the description of spiking situations in aux_1,3…aux_1,8 is omitted in Table 1.

(1)

t = 1 to 9, the input auxiliary module does not generate spiking output. At each time slice, σ_aux1,0 and σ_aux1,1 continuously send spiking to each other, while σ_aux1,1 continuously sends spiking to σ_aux1,2. This spiking along σ_aux1,3, σ_aux1,4, …, σ_aux1,9, σ_aux2,i (i = 0, 1) sequential transmission. At t = 9 time slice, all neurons in the input auxiliary module have 1 spiking.

(2)

t = 10 to 19, σ_aux2,0 continuously sending spiking to σ_aux1,0 and σ_aux1,1. At t = 10 time slice, σ_aux1,0 and σ_aux1,1 also received 1 spiking sent by each other. These spikings are stacked in σ_aux1,0 and σ_aux1,1. At t = 11 time slice, σ_aux1,0 and σ_aux1,1 stop generating spiking output. At t = 10 to 19 time slices, σ_aux2,0 and σ_aux2,1 continuously generate spiking output. At t = 11 to 19 time slices, the spikings in σ_aux1,2, σ_aux1,3, …, σ_aux1,9, σ_aux2, i (i = 0, 1) are sequentially cleared. At t = 19 time slice, there are 11 spikings stacked in σ_aux1,0 and σ_aux1,1. And there is no spiking in σ_aux1,3, σ_aux1,4, …, σ_aux1,9, σ_aux2, i (i = 0, 1).

②

Summand Input

The spiking corresponding to the addend bit is received by σ_in in order from low to high. These spikings along the σ_aux3, σ_sum7, …, σ_sum0 transferred to σ_Add. Due to the fact that the summand input during time slice t = 5 to 8 are all 0, the spiking situation in the system during that time period is omitted from Table 1.

(1)

t = 1 to 8, the spiking 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 corresponding to the summand from low to high are sequentially received by σ_in. These spikings along the σ_aux3, σ_sum7, …, σ_sum0 transferred to σ_Add. At t = 1 time slice, spiking 1 corresponding to the lowest bit of the summand is received by σ_in. At t = 8 time slice, the spiking 0 corresponding to the highest bit of the addend is received by σ_in.

(2)

t = 2 to 9, σ_in sends spiking to both σ_aux3 and σ_addend. σ_addend uses forgetting rule a → ƛ to consume these spiking.

(3)

t = 10, the summand is stored in ascending order from low to high in the σ_sum0, σ_sum1, …, σ_sum7. There are 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 spikings in σ_sum0, σ_sum1, …, σ_sum7.

(4)

t = 11 to 18, the spiking corresponding to each summand is sequentially in order from low to high received by σ_Add.

③

Addend Input

The spiking corresponding to the addend is sorted in order from low to high received by σ_in. These spikings pass through σ_addend transferred to σ_Add. Due to the fact that the spiking output to the environment during the time slice t = 16 to 18 is all 0, the spiking situation in the system during this time period is omitted from Table 1.

(1)

t = 1 to 10, there is no spiking output in σ_addend.

(2)

t = 9 to 16, the corresponding spiking 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 of the addend from low to high are sequentially represented received by σ_in. These spikings through σ_addend transferred to σ_Add. At t = 9 time slice, the spiking 0 corresponding to the lowest bit of the addend is received by σ_in. At t = 16 time slice, the spiking 0 corresponding to the highest bit of the addend is received by σ_in.

(3)

t = 10 to 17, there are 2, 3, 3, 2, 2, 2, 2, 2, 2 spikings in σ_addend at each time slice. These spikings come from σ_aux2,0, σ_aux2,1, and σ_in. During the time slice t = 10 to 17, σ_aux3 receives spikings sent by σ_aux2,0, σ_aux2,1 and σ_in at each time slice. At t = 17 time slice, there are 18 spikings stacked in σ_aux3.

(4)

t = 11 to 18, the spiking in σ_sum7, σ_sum6, …, σ_sum0 are sequentially cleared.

④

Overflow Monitoring

(1)

t = 0 to 9, there is no spiking input in σ_aux4.

(2)

t = 10 to 18, σ_aux4 receives 1 spiking sent by σ_aux2,1 at each time slice. And stack these spiking in σ_aux4. At t = 18 time slice, 9 spikings stacked in σ_aux4.

(3)

At t = 19 time slice, σ_aux4 sends 4 spikings after using rule a⁹ → a⁴ to σ_Add. At this point, the highest bit of the two addends have been calculated and no carry has been generated. There are 4 spikings in σ_Add, no rules can be use, and there is no data overflow. At the same time, σ_aux4 received 1 spiking sent by σ_aux2,1, which is stacked in σ_aux4.

⑤

Addition Operation

(1)

t = 1 to 10, there is no spiking input in σ_Add.

(2)

t = 11 to 18, the spiking corresponding to each of the two binary addends is sent in sequence from low to high to σ_Add. At t = 11 time slice, σ_Add received the spiking corresponding to the lowest order of two addends. At this time, there is 1 spiking in σ_Add. At t = 18 time slice, σ_Add received spiking corresponding to the highest bit of 2 addends, there are 0 spiking in σ_Add.

(3)

t = 12 to 19, it is the effective output time of П_Add2. During this time slice, the calculation results are sent to the environment in order from low to high. In each time slice, the environment received 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 spikings in sequence.

(4)

t = 19, σ_Add received 4 spikings sent by σ_aux4. At this time, there are no rules that can be used in П_Add2, and the system operation stops. The system П_Add2 calculates that the sum of 00000101₂ and 00000110₂ is 00001011₂, and the calculation result is correct.

From Table 1, it can be seen that the effective output time of the system is t = 12. And the sum of two natural numbers 5 and 6 is 00001011₂, which is 11. The addition LHSNP system constructed of П_Add2 can perform the addition operation of 2 k-bit binary numbers.

3.2. An LHSNP System with 1 Input Neuron for n-addition

П_Add2 can only add two binary numbers, which has limitations in practical applications. In practical applications, it is more necessary to complete n-addition. Therefore, this section has made improvements to П_Add2, and the structure of the improved LHSNP system П_Add3 with one input neuron is shown in Figure 2. In Figure 2, the solid arrows represents the directed connection between two neurons. The dashed arrows indicates the omission of connections between multiple neurons. Due to the similarity between П_Add3 and П_Add2, the formal definition of П_Add3 has been omitted.

The design thought of П_Add3 is as follows: ① The system input part is divided into two modules, namely the input module and the input cache module. The input module is composed of an input selection module and an input assistance module. The input module controls the input of the summand and addend: the summand (the first addend) is transmitted through the auxiliary neuron σ_aux3, while the addend is transmitted through the addend neuron σ_addend. After the input of the summand is completed, with the assistance of the input auxiliary module, the addend is stopped through σ_aux3 transmitted. And σ_addend is firing to translate addend. ② High-level monitoring neuron σ_aux4 monitors the highest bit of two binary addends. When the highest bit of two binary addends are reached the addition operation neuron σ_Add. σ_aux4 sends 4 spiking to σ_Add to mark the highest bit. ③ Two addends complete the addition calculation in σ_Add and send the operation results to the environment and the summand cache module. The spiking waiting stored in the summand cache module completes the addition calculation with the next addend in σ_Add, thereby achieving accumulate plus. ④ Overflow monitoring neuron σ_OF monitors whether the calculation overflow. If the calculation result overflow, σ_OF sends spiking to the environment and some neurons in П_Add3, the aim is terminal the operation of П_Add3. ⑤ Spiking control neuron σ_aux5 controls σ_aux1,0 and σ_aux1,1 to stop generating spiking output.

The rules of П_Add3 are divided into six groups: (1) Homogeneous neurons: auxiliary neurons, summand cache neurons, σ_aux3, and input neurons use rule set R = {a → a}. (2) High-level monitoring neuron σ_aux4 uses rule set R_aux4 = {a^k → a⁴}. (3) Spiking control neuron σ_aux5 uses rule set R _aux5 = {a^(n−1)k → a}. (4) Addend neuron σ_addend uses rule set R_addend = {a → ƛ; a² → ƛ; a³ → a}. (5) Addition operator neuron σ_Add uses rule set R_Add = {a → a; a²/a → ƛ; a³/a² → a; a⁴ → ƛ; a⁵ → a; a⁶ → a⁴; a⁷ → a⁴}. (6) Overflow monitoring neuron σ_OF uses rule set R_OF = {a → ƛ; a⁴ → a⁴}.

Analyzing Figure 2, it can be seen that П_Add3 contains 13 rules, 2k + 11 neurons, and completing n-addition operations requires nk + 3 time slices. Furthermore, we have the following conclusion:

Theorem 2.

П_Add3 can perform any n k-bit binary number addition operations with 1 input neuron. That is, П_Add3 receives spiking corresponding to binary numbers in order from low to high. And it can correctly complete the addition operation and output result to the environment in order from low to high.

Proof of Theorem 2.

Let t stand the time slice. At the initial state t = 0, there is 1 spiking in σ_aux1,0 and σ_aux1,1. Starting from t = 1 time slice, the spiking corresponding to n k-bit binary addends are received by σ_in in order from low to high. The spiking corresponding to the first binary addend is sequentially transmitted to σ_Add through σ_aux3 and the auxiliary neuron σ_sumi (0 ≤ i ≤ k − 1) in the summand cache module. The spiking corresponding to the 2nd to nth addends is sequentially transmitted to σ_Add through σ_addend. The calculation process of П_Add3 is as follows:

①

Input Assistance Module

The input assistance module of П_Add3 is similar to П_Add2, and compared to П_Add2, П_Add3 has made the following improvements:

(1)

Add an auxiliary neuron σ_aux5. σ_aux5 and σ_aux1,0 connected to each other. And σ_aux5 is also connected to σ_aux1,1. σ_aux5 controls σ_aux1,0 and σ_aux1,1 to stop generating spiking. σ_aux1,0 send 1 spiking to σ_aux1,1 while also sending 1 spiking to σ_aux5. These spikings accumulate in σ_aux5 until the number of spiking reaches (n − 1)k. When there are (n − 1)k spikings, σ_aux5 is fired and sends spiking to σ_aux1,0 and σ_aux1,1 to stop generating spiking output.

(2)

Add a connection between σ_Add and σ_sumk−2. σ_Add send the calculation results to both the environment and σ_sumk−2 for accumulate plus.

(3)

Add overflow monitoring neuron σ_OF. If data overflow, σ_OF sends 4 spikings to some neurons in the system truncation spiking transmission. The aim is to stop the system.

(4)

Modify the conditions for firing σ_aux4. If the number of stacked spiking in σ_aux4 reaches k, then firing σ_aux4 sends 4 spikings to σ_Add to mark the highest bit of the 2 addends in σ_Add.

②

The First Addend Input

The first addend is passed to σ_Add through the auxiliary neurons σ_in, σ_aux3, and the addend cache module in order of binary bits from low to high. The process of inputting the first addend is as follows:

(1)

t = 1 to k, the spiking corresponding to the first binary addend is received by σ_in in order from low to high. At each time slice, these spikings are transmitted sequentially along σ_aux3, σ_sumk−1, σ_sumk−2, …, σ_sum0. At the same time, σ_addend also receives spikings from σ_in at each time slice. These spikings are consumed by rule a → ƛ in σ_addend. In order to stop the first addend transmit through σ_addend.

(2)

t = k + 1 to k + 2, the addend cache module does not generate spiking output. At t = k + 2 time slice, the spiking corresponding to each bit of the first binary addend is sequentially stored in σ_sum0, σ_sum1, …, σ_sumk−1 from low to high. At the same time, σ_aux3 continues to receive spiking sent by σ_in, σ_aux2,0, σ_aux2,1 until (n − 1) k + 3 time slice. And these spikings accumulate in σ_aux3.

(3)

t = k + 3 to 2k + 2, the spiking corresponding to the first binary addend is sequentially received by σ_Add. At t = 2k + 2 time slice, the spiking corresponding to the highest bit of the first addend is received by σ_Add.

③

The 2nd to nth Addend Input

The spiking corresponding to the second to nth binary addends are received by σ_in in order from low to high. And these spikings are transmitted to σ_Add through σ_addend. The process of inputting the 2nd to nth addends is as follows:

(1)

t = 1 to k + 1, σ_addend does not generate spiking output.

(2)

t = (i − 1) k + 1 to ik (2 ≤ i ≤ n), the spiking corresponding to the i-th binary addend is received by σ_in in order from low to high. At each time slice, these spikings are transmitted to σ_Add through σ_addend.

(3)

t = (i − 1) k + 2 to ik + 1 (2 ≤ i ≤ n), the spiking corresponding to the i-th binary addend is sequentially received by σ_addend. At the same time, σ_addend will also receive 1 spiking sent by σ_aux2,0 and σ_aux2,1 at each time slice. σ_aux2,0 and σ_aux2,1, σ_addend is fired and send spiking to σ_Add. If there are 2 spikings in σ_addend, σ_addend firing rule a² → ƛ sends 0 spiking to σ_Add. If there are 3 spikings in σ_addend, σ_addend firing rule a³ → a to send 1 spiking to σ_Add.

(4)

t = (i − 1) k + 3 to ik + 2 (2 ≤ i ≤ n), the spiking corresponding to the nth binary addend is sequentially received by σ_Add. At t = ik + 2 (2 ≤ i ≤ n) time slice, the highest bit of the 2nd to nth addend is received by σ_Add.

④

N-addition

For each time slice starting from k + 3, σ_Add receive the spiking corresponding to two binary addends in sequence from low to high. And outputs the operation results to σ_sumk−2, the environment, σ_OF, and summand cache module. The spiking output to the environment represents the current calculation result. If there is no overflow in the calculation result, the effective output time of П_Add3 is (n − 1) k + 4 to nk + 3. σ_Add sends the operation results to σ_sumk−2 and waits for the next addend to complete the accumulated subtraction in σ_Add. That is, the operation results of the two addends in this operation with the next addend accumulate subtraction in σ_Add. σ_OF monitors whether the highest bit calculation result in σ_Add overflows. The process of implementing the accumulation of n k-bit binary numbers is as follows:

(1)

t = 1 to k + 2, there is no spiking input in σ_Add.

(2)

t = k + 3 to 2k + 2, the spiking corresponding to the first and the second addends are sequentially received by σ_Add. At t = k + 4 to 2k + 3 time slice, σ_Add simultaneously sends the calculation results to the environment, σ_sumk−2 and σ_OF at each time slice. At t = k + 4 time slice, the lowest order of the results of two addend operations is output to the environment, σ_OF, and σ_sumk−2. At t = (i − 1) k + 4 to ik + 3 (2 ≤ i ≤ n) time slice, σ_Add sends the calculation results to the environment, σ_sumk−2 and σ_OF at each time slice.

(3)

At t = k + 4 until the system stops, the summand cache module receives spiking sent by σ_Add at each time slice. These spikings are transmitted along σ_sumk−3, σ_sumk−4, …, σ_sum0. At t = 2k + 2 time slice, the results of the first and the second addends are stored in σ_sum0, σ_sum1, …, σ_sumk−1 in order from low to high. At t = ik + 2 (2 ≤ i ≤ n) time slice, the operation results of n addends are stored in σ_sum0, σ_sum1, …, σ_sumk−1 in order from low to high.

(4)

From t = 2k + 3 to 3k + 2, complete accumulate plus in σ_Add. At t = (i − 1) k + 3 to ik + 2 (2 ≤ i ≤ n), complete the accumulation with the i-th addend.

(5)

In the absence of overflow in the calculation results, (n − 1) k + 4 to nk + 3 time slice is the effective output time of П_Add3. At nk + 3 time slice, the highest bit of n addend calculation results is output to the environment.

⑤

Adder

The process of implementing the addition operation in П_Add3 by the addition operator σ_Add is as follows:

There are a total of seven rules in σ_Add, of which four are: a⁴ → ƛ; a⁵ → a; a⁶ → a⁴; a⁷ → a⁴ is used to detect whether the highest bit of two binary addends participates in the calculation of σ_Add and whether the calculation result overflows. The implementation of the seven rules in σ_Add is as follows:

(1)

Rule a → a represents executing equation 1₂ + 0₂ = 1₂. It consume one spiking in σ_Add and send one spiking outward, which is the calculation result.

(2)

a²/a → ƛ indicates the execution of equation 1₂ + 1₂ = 10₂. One spiking retainedin σ_Add indicating carry 1, and zero spikings sent outward indicating the operation result 0.

(3)

a³/a² → a indicates the execution of equation 1₂ + 1₂ + 1₂ = 11₂. One spiking retain in σ_Add indicates carry 1, and one spiking sent outward indicates the operation result 1.

(4)

a⁴ → ƛ; a⁵ → a; a⁶ → a⁴; a⁷ → a⁴ is used to perform the highest order operation. a⁴ → ƛ indicates that the highest order calculation performed is 0₂ + 0₂ = 0₂. a⁵ → a indicates that the highest order calculation performed is 1₂ + 0₂ = 1₂. a⁶ → a⁴ indicates that the highest bit calculation performed is 1₂ + 1₂ = 10₂, which indicates that data overflow and sends out 4 spikings. a⁷ → a⁴ indicates that the highest bit calculation performed is 1₂ + 1₂ + 1₂ = 11₂, which indicates that data overflow. σ_Add sends 4 spikings outward.

⑥

Data Overflow Monitoring

σ_aux4 send spiking to σ_Add to mark the highest bit of each addition operation in σ_Add. Pass 4 rules in σ_Add: a⁴ → ƛ; a⁵ → a; a⁶ → a⁴; a⁷ → a⁴ detects whether the highest bit calculation result overflows. If the calculation result overflows, σ_Add sends 4 spikings outward. If the environment received 4 spikings, it indicates that data overflow. After receiving 4 spikings in σ_OF, 4 spikings are sent to each neuron σ_aux1,i (0 ≤ i ≤ k + 1), σ_aux2,i (0 ≤ i ≤ k − 3), σ_Add and σ_addend to cut off the transmission of spiking in П_Add3, causing the system to stop running. The process of data overflow monitoring is as follows:

(1)

t = 1 to k + 1, there is no spiking input in σ_aux4.

(2)

t = (i − 1) k + 2 to ik + 1 (2 ≤ i ≤ n), σ_aux4 receives 1 spiking sent by σ_aux2,1 at each time slice, and these spikings are stacked in σ_aux4. At t = ik + 2 (1 ≤ i ≤ n) time slice, σ_aux4 is fired using rule a^k → a send 4 spikings to σ_Add.

In summary, the above П_Add3 can perform any n k-bit binary number addition operations with one input neuron. □

To illustrate the operation process of П_Add3 shown in Figure 2, take the sum of three natural numbers 134, 134, and 1 as an example for illustration. The binary form of these three natural numbers is 10000110₂, 10000110₂, and 00000001₂. In П_Add3, n is 3 and the system is 8-bit, which means k is 8.

Table 2. The number of spiking of all neurons in П_Add3 and the number of spiking sent to the environment during the calculation of 10000110₂ + 10000110₂ + 00000001₂.

t	in	aux3	sum7	sum6, …, sum1	sum0	aux1,0	aux1,1	aux1,2	aux1,3, …, aux1,9	aux2,0	aux2,1	aux4	aux5	addend	Add	Out	OF
t = 0	-	0	0	…	0	1	1	0	…	0	0	0	0	0	0	-	0
t = 1	0	0	0	…	0	1	1	1	…	0	0	0	0	0	0	-	0
2, …, 7	…	…	…	…	…	…	…	…	…	…	…	…	…	…	…	…	…
t = 8	1	0	0	…	0	1	1	1	…	0	0	0	7	0	0	-	0
t = 9	0	1	0	…	0	1	1	1	…	1	1	0	8	1	0	-	0
t = 10	1	2	1	…	0	1	1	1	…	1	1	1	9	2	0	-	0
t = 11	1	5	0	…	1	1	1	1	…	1	1	2	10	3	0	-	0
t = 12	0	8	0	…	1	1	1	1	…	1	1	3	11	3	2	0	0
t = 13	0	10	0	…	0	1	1	1	…	1	1	4	12	2	3	0	0
t = 14	0	12	0	…	0	1	1	1	…	1	1	5	13	2	1	1	0
t = 15	0	14	0	…	0	1	1	1	…	1	1	6	14	2	0	1	0
t = 16	1	16	0	…	0	1	1	1	…	1	1	7	15	2	0	0	0
t = 17	1	19	0	…	1	1	1	1	…	1	1	8	16	3	0	0	0
t = 18	0	22	0	…	0	2	2	1	…	1	1	1	1	3	6	0	0
t = 19	0	24	0	…	0	2	2	0	…	1	1	2	1	2	1	4	4
t = 20	0	26	0	…	5	6	6	4	…	1	1	3	1	6	4	1	1
t = 21	0	28	0	…	5	6	6	4	…	0	0	4	1	8	0	0	0

shows the number of spiking in all neurons at each time slice in П_Add3. In Table 2, “t” represents the time slice. “in” represents the number of spiking in neuron σ_in. “aux_1,i (0 ≤ i ≤ k + 1)”, ”aux_2,i (0 ≤ i ≤ 1)” and “aux₃” represents the number of spiking in the auxiliary neuron. “aux₄” represents the number of spiking in the high-level monitoring neuron σ_aux4. “aux₅” represents the number of spiking in the spiking control neuron σ_aux5. “sum_i (0 ≤ i ≤ k − 1)” represents the number of spiking in the summand auxiliary neuron σ_sumi (0 ≤ i ≤ k − 1). “addend” represents the number of spiking in the addend neuron σ_addend. “Add” represents the number of spiking in the addition operation neuron σ_Add. “out” represents the number of spiking sent to the environment. “OF” represents the number of spiking in the overflow monitoring neuron σ_OF. The input n addends and the output operation results are represented in bold font.

The calculation process for the three binary numbers 0000110₂, 10000110₂, and 00000001₂ in П_Add3 is as follows:

①

Input Auxiliary Module

(1)

t = 0, there is 1 spiking in σ_aux1,0 and σ_aux1,1.

(2)

t = 1 to 9, σ_aux1,0 and σ_aux1,1 send spiking to each other and maintain one spiking in. At the same time, σ_aux1,1 send 1 spiking to σ_aux1,2 at each time slice. These spikings are transmitted sequentially along σ_aux1,2, σ_aux1,3, …, σ_aux1,9. σ_aux1,1 will send 1 spiking to σ_aux5 at each time slice, these spikings are stacked in the σ_aux5. During this time slice, the input auxiliary module does not generate spiking output.

(3)

t = 10 to 17, all neurons in the input auxiliary module maintain 1 spiking. At the same time, σ_aux2,1 send 1 spiking to σ_aux4 at each time slice. And these spikings are stacked in σ_aux4. σ_aux1,1 send 1 spiking to σ_aux5 at each time slice. And these spikings are stacked in σ_aux5. At t = 17 time slice, there are 8 spikings stacked in σ_aux4 and 16 spikings stacked in σ_aux5.

(4)

t = 18 to 21, the neurons in the input auxiliary module stop sending spikings in the order of (σ_aux1,0, σ_aux1,1), σ_aux1,2, σ_aux1,3, …, σ_aux1,9, (σ_aux2,0, σ_aux2,1). At t = 18 time slice, σ_aux1,0 and σ_aux1,1 receives 1 spiking sent by σ_aux5 firing rule a¹⁶ → a. σ_Add received 4 spikings sent by σ_aux4 firing rule a⁸ → a⁴. At t = 20 time slice, σ_aux1,0, σ_aux1,1, σ_aux1,2, …, σ_aux1,9 receives 4 spikings sent by σ_OF and cut off the transmission of the spiking in neurons. At t = 21 time slice, the spiking in σ_aux2,0, σ_aux2,1 are consumed and there are no rules to fire in the input auxiliary module.

②

The First Addend Input

(1)

t = 1 to 8, σ_in received spiking corresponding to bit of the first binary addend.

(2)

t = 2 to 18, the first addend is transmitted along σ_aux3, σ_sum7, σ_sum6, …, σ_sum0, σ_Add at each time slice. At t = 2 to 9 time slice, σ_addend received spiking sent by σ_in. This spikings are consumed by the forgetting rule a → ƛ in σ_addend. At t = 10 time slice, the spiking corresponding to the first addend is stored in σ_sum7, σ_sum6, …, σ_sum0 in order from low to high. At t = 11 time slice, the spiking corresponding to the lowest bit of the first addend is received by σ_Add. At t = 18 time slice, the spiking corresponding to the highest bit of the first addend is received by σ_Add.

③

The Second Addend Input

(1)

t = 1 to 9, σ_addend does not generate spiking output.

(2)

t = 9 to 16, σ_in receives bits of the second binary addend.

(3)

t = 10 to 18, the second addend is transmitted along σ_addend and σ_Add at each time slice. At t = 10 to 17 time slice, σ_aux3 received spiking sent by σ_in, and 2 spikings sent by σ_aux1,0 and σ_aux1,1. These spikings are stacked in σ_addend. At t = 11 time slice, the spiking corresponding to the lowest bit of the second addend is received by σ_Add. At t = 18 time slice, the spiking corresponding to the highest bit of the second addend is received by σ_Add.

④

The Third Addend Input

(1)

t = 17 to 21, σ_in receives the last 5 bits of the third binary addend.

(2)

t = 18 to 21, the third addend is transmitted along σ_addend and σ_Add at each time slice. At t = 18 to 21 time slice, σ_aux3 received spiking sent by σ_in, and 1 spiking sent by σ_aux1,0 and σ_aux1,1. These spikings are stacked in σ_addend. At t = 19 time slice, the spiking corresponding to the lowest bit of the third addend is received by σ_Add. At t = 21 time slice, the spiking corresponding to the a⁶ bit of the third addend is received by σ_Add.

⑤

Addition

(1)

t = 1 to 10 does not have an addend reaching σ_Add. So, there is no spiking in σ_Add.

(2)

t = 11 to 18, the first and the second addends are received by σ_Add in order from low to high. At t = 18 time slice, the highest bits of the first and second addends are received by σ_Add, and the 4 spikings sent by σ_aux4 are received by σ_Add too.

(3)

t = 12 to 19, the operation results of the first and the second addends are sent to the environment, σ_OF and σ_sum6. At t = 19 time slice, the environment, σ_OF and σ_sum6 receive 4 spikings sent by σ_Add using rule a⁶ → a⁴. It indicates data overflow.

(4)

t = 20, σ_OF is fired and send 4 spikings to σ_Add, σ_aux1,2, σ_aux1,3, … σ_aux1,9. At the same time, the environment, σ_OF and σ_sum6 received 1 spiking sent by σ_Add.

(5)

At t = 21 time slice, there is no rule can be firing in σ_Add and σ_OF. П_Add3 stops running.

From Table 2, it can be seen that data overflow occurred during the calculation process of П_Add3. At t = 19 time slice, the spiking sent to the environment is 4. Therefore, the calculation result is abnormal and exceeded the range of П_Add3 calculation, resulting is overflow. At t = 21 time slice, the system stops running.

3.3. Comparison

This section implements two different types of addition LHSNP systems П_Add2 and П_Add3. The two additive LHSNP systems designed in this article and the additive P systems designed in [25,34] require the number of neurons, the time required to complete the operation, and the number of rules in the system, as shown in

Table 3. Two types of LHSNP systems for addition.

	SN P System	SN P System with 1 Input for 2 Natural Number Addition			SN P System with 1 Input for n Natural Number Addition
Parameter
		Number of Neurons	Complete Time	Number of Rules	Number of Neurons	Complete Time	Number of Rules
This work		2k + 9	2k + 3	8	2k + 11	nk + 3	13
Zhang Xingyi [25]		-	-	-	3k + 5	(n + 1)k + 4	9
Wang Huifang [34]		-	-	-	2k + 4	(n + 1)k + 1	5k − 1

.

There is no SN P system with one input for two k-bit binary number addition designed in [25,34]. Therefore, П_Add2 is analyzed in comparison with П_Add3. П_Add3 adds 2 neurons compared to П_Add2. П_Add3 completes calculations with (n − 2)k more time slice than П_Add2. П_Add3 has 5 more rules than П_Add2. Although П_Add2 is superior to П_Add3. But П_Add3 can implement the addition operation of n k-bit binary numbers. П_Add3 has a wider range of applications.

П_Add3 has 13 rules, requiring 2k + 11 neurons and nk + 3 time slices to complete the calculation. Compared to the SN P system for addition proposed by Zhang Xingyi in [25]. Our designed П_Add3 has increased the number of rules by 4. But the number of neurons has been reduced by k − 6 compared to [25], and the time required to complete the calculation has been reduced by k + 1 time slice. It greatly optimizes the additive SN P system. In the SN P system with weights and delays for addition proposed by Wang Huifang et al. in [34], we removed weights and delays by increasing the number of neurons. Compared with [34], our designed П_Add3 adds 7 neurons, but the time required to complete the calculation has been reduced by k − 2 time slice, and the number of rules has been reduced by 5k − 14. This not only simplifies the system but also greatly improves its performance.

4. An Locally Homogeneous Spiking Neural P System for Subtraction

In this section, we will present three kinds of LHSNP systems with one and two input neurons for k-bit (k ≥ 5) binary number subtraction. They perform subtraction operations on two numbers and multiple numbers. In our designed system, if the representation of the k-bit (k ≥ 5) binary number participating in the calculation is less than k bits, the high bits of the binary number are automatically zeroed in. The binary numbers involved in the calculation are input in the order from low to high (0 spiking represents 0₂ and 1 spiking represents 1₂). The results are output into the environment in the form of a spiking sequence (0 spiking for binary number 0, 1 spiking for binary number 1, and 4 spikings for data overflow).

4.1. An LHSNP System with 2 Input Neurons for 2 Numbers Subtraction

An LHSNP system П_Sub1 with 2 input neurons as formula (5). The structure of П_Sub1 is as Figure 3. In Figure 3, the solid arrows represents the directed connection between two neurons. The design idea of П_Sub1 is as follows: ① Input auxiliary module adjusts the spiking corresponding to the minuend binary number 0. It uses 2 spikings to represent the minuend binary number 0 in σ_Sub. In order to distinguish it from the spiking corresponding to the subtrahend binary number 0. ② Spiking controlled neuron σ_aux2 control σ_aux1,0 and σ_aux1,1 stops generating spiking output. ③ After the minuend is received by input neuron σ_in1, it follows the auxiliary neuron σ_aux1,6 and the minuend neurons σ_minuend passed to σ_Sub. ④ After the subtrahend is received by input neuron σ_in2, it follows the auxiliary neuron σ_aux1,7 and subtrahend neurons σ_subtrahend passed to σ_Sub. ⑤ Minuend and subtrahend complete the calculation in σ_Sub and send the calculation results to the environment. ⑥ Overflow monitoring neurons σ_aux3 monitors after the highest order of the minuend and subtracted numbers in σ_Sub performing subtraction, whether the calculation result is overflow.

The rules of П_Sub1 are divided into 5 groups: (1) Homogeneous neurons: rule set R_aux = {a → a} for auxiliary neurons, subtrahend neurons, and input neurons. (2) Minuend neuron σ_m uses rule set R_m = {a² → a², a³ → a}. (3) Spiking control neuron σ_aux2 uses rule set R_aux2 = {a^k−1 → a}. (4) Overflow monitoring neuron σ_aux3 uses rule set R_aux3 = {a^k → a⁵}. (5) Subtraction operator neuron σ_Sub uses rule set R_Sub = {a → a; a² → ƛ; a³/a² → a; a⁴/a³ → ƛ; a⁶ → a⁴}.

The formal definition of П_Sub1 is as follows:

П_Sub1 = (O, σ_in1, σ_in2, σ_aux1,0, σ_aux1,1, …, σ_aux1,7, σ_aux2, σ_aux3, σ_m, σ_s, σ_Sub, syn, Input₁, Input₂, out)

(5)

where:

(1)

O= {a};

(2)

σ_in1 = (0, R_aux);

(3)

σ_in2 = (0, R_aux);

(4)

σ_aux1,i = (1, R_aux), 0 ≤ i ≤ 1;

(5)

σ_aux1,i = (0, R_aux), 2 ≤ i ≤ 7;

(6)

σ_aux2 = (0, R_aux2);

(7)

σ_aux3 = (0, R_aux3);

(8)

σ_m = (0, R_m);

(9)

σ_s = (0, R_aux);

(10)

σ_Sub = (0, R_Sub);

(11)

syn = {(in₁, aux_1,6), (in₂, aux_1,7), (aux_1,6, m), (aux_1,7, s), (m, Sub), (s, Sub), (aux_1,0, aux_1,1), (aux_1,1, aux_1,0), (aux_1,1, aux₂), (aux₂, aux_1,0), (aux₂, aux_1,1), (aux_1,1, aux_1,2), (aux_1,2, aux_1,3), (aux_1,2, aux_1,4), (aux_1,3, aux_m), (aux_1,4, aux_m), (aux_1,4, aux_1,5), (aux_1,5, aux₃), (aux₃, Sub)};

(12)

in₁ = Input₁, in₂ = Input₂;

(13)

out = Sub.

Through analysis П_Sub1 and its rule set, we can see: П_Sub1 contains 15 neurons and 9 rules, and completing the subtraction operation of 2 k-bit binary numbers requires a k + 4 time slice.

Theorem 3.

П_Sub1 can perform any 2 k-bit binary numbers subtraction with 2 input neurons. Namely, after П_Sub1 receives k-bit binary numbers in the order from low to high, it can correctly perform subtraction and output spiking to the environment in the order from low to high.

Proof of Theorem 3.

Let t represent the time slice. At the initial state t = 0, there is one spiking in σ_aux1,0 and σ_aux1,1. Starting from t = 1 time slice, two binary numbers are sequentially received by σ_in1 and σ_in2 from low to high. When the binary bit is 1, σ_in1 and σ_in2 received 1 spiking, otherwise 0 spiking were received. The minuend passes through σ_aux1,6 and σ_minuend passed to σ_Sub participates in subtraction operations. Subtraction is passed in the order of σ_in1,7, σ_subtahend, and σ_Sub. The calculation process of П_Sub1 is as follows:

①

Input Auxiliary Module

The function of the input auxiliary module is to adjust the number of spiking corresponding to the binary number 0 represented by the minuend number during transmission. The purpose is to make the spiking representing the minuend and subtrahend corresponding to the binary number 0 different. The process for inputting auxiliary modules is as follows:

(1)

t = 0, there is one spiking in σ_aux1,0 and σ_aux1,1.

(2)

t = 1 to 2, the input auxiliary module does not generate spiking output. At each time slice, σ_aux1,0 and σ_aux1,1 send spiking to each other and maintain 1 spiking. At the same time, σ_aux1,0 at every time slice sends 1 spiking to σ_aux1,2. These spikings are transmitted along σ_aux1,2 and (σ_aux1,3, σ_aux1,4).

(3)

t = 3 to k + 2, the input auxiliary module does not send spiking output. σ_aux1,3 and σ_aux1,4 send one spiking to σ_minuend at each time slice. t = 3 to k − 1, σ_aux1,0 and σ_aux1,1 send spiking to each other. And σ_aux1,0 at each time sends 1 spiking to σ_aux1,2. At k − 1 time slice, k − 1 spikings stacked in σ_aux2. At t = k time slice, σ_aux1,0 and σ_aux1,1 received 2 spiking. One of the spiking comes from what they send to each other. Another spiking is sent by σ_aux2 using rule a^k−1 → a. At k + 1 time slice, the spiking in σ_aux1,2 is cleared to zero. At k + 1 time slice, the spiking in σ_aux1,3 and σ_aux1,4 is cleared to zero.

(4)

At the k + 3 time slice, σ_aux1,5 send 1 spiking to σ_aux3. There are 8 spikings stacked in σ_aux3.

(5)

At the k + 4 time slice, the input auxiliary module no longer generates spiking.

②

Minuend Input

(1)

t = 1 to k, the spiking corresponding to each binary bit of the minuend is sequentially received by σ_in1 in order from low to high. These spikings are transmitted along σ_aux1,6, σ_minuend, and σ_Sub.

(2)

t = 3 to k + 2, the spiking corresponding to each binary bit of the minuend is sequentially received by σ_minuend. At the same time, σ_minuend also received 2 spikings at each time from σ_aux1,3 and σ_aux1,4.

(3)

t = 4 to k + 3, the spiking corresponding to each binary bit of the minuend sent by σ_minuend is sequentially received by σ_Sub. At each time slice, one spiking sent by minuend represents the binary number 1, and 2 spiking represents the binary number 0. At k + 3 time slice, the highest bit of the minuend is received by σ_Sub.

③

Subtrahend Input

(1)

t = 1 to k, the spiking corresponding to each binary bit of the subtrahend is sequentially received by σ_in2 in order from low to high. These spikings are transmitted along σ_aux1,7, σ_sutrahend, and σ_Sub.

(2)

t = 3 to k + 2, the spiking corresponding to each binary bit of the subtrahend is sequentially received by σ_sutrahend.

(3)

t = 4 to k + 3, the spiking corresponding to each binary bit of the subtrahend is sequentially received by σ_Sub. At each time slice, one spiking sent by σ_sutrahend represents the binary number 1, and zero spiking represents the binary number 0. At k + 3 time slice, the highest bit of the subtrahend is received by σ_Sub.

④

Subtraction Operation

(1)

t = 1 to 3, there is no spiking were received in σ_sub.

(2)

t = 4 to k + 3, the spiking corresponding to each binary bit of the minuend and subtrahend sent by σ_minuend and σ_sutrahend are sequentially received by σ_Sub.

(3)

t = 5 to k + 4, σ_sub sends calculation results to the environment at each time slice. It is the effective output time of П_Sub1 when there is no overflow in the calculation. At t = k + 3 time slice, the highest bit of the two subtractors is calculated. At t = k + 4 time slice, σ_aux3 uses rule a^k → a⁵ to send 5 spikings to σ_sub. These 5 spikings in the σ_sub detect whether there is a carry after the calculation of the highest bit of the two subtractions. If there is a carry generation, σ_sub uses rule a⁶ → a⁴ to send 4 spikings to the environment to indicate data overflow.

⑤

Subtraction Rules

There are 5 rules in σ_Sub represent subtraction operations. The situation of performing subtraction in σ_Sub is as follows:

(1)

Rule a → a indicates performing subtraction calculation: 1₂ − 0₂ = 1₂. There is one spiking in σ_sub, which comes from σ_minuend. It represents the subtracted binary bit 1. Rule a → a represents consumption 1 spiking in σ_sub, and sending 1 spiking to the environment, namely performing subtraction operation 1₂ − 0₂ = 1₂.

(2)

Rule a² → ƛ indicates performing subtraction calculation: 0₂ − 0₂ = 0₂ or 1₂ − 1₂ = 0₂. There are two spikings in the σ_sub, and there are three sources of these two spikings. In the first case, these two spikings have come from σ_minuend and σ_subtrahend. In the second case, one of them come from σ_sub retained spiking in σ_sub (be borrowed), and the other one come from σ_subtrahend. In the third case, these two spikings came from σ_minuend. Rule a² → ƛ consumption 2 spikings in σ_sub, and send 0 spiking to the environment, namely performance subtraction operation 0₂ − 0₂ = 0₂ or 1₂ − 1₂ = 0₂.

(3)

Rule a³/a² → a indicates performing subtraction calculation: 0₂ − 1₂ = 1₂ and borrowing one digit forward. Two spikings come from σ_minuend and one spiking comes from σ_addend. Rule a³/a² → a represents consuming 2 spikings in σ_sub, retaining 1 spiking (representing forward borrowing), and sending 1 spiking to the environment. That is, the subtraction operation performed is 0₂ − 1₂ = 1₂ and borrowing 1 digit forward.

(4)

Rule a⁴/a³ → ƛ means to perform subtraction: 0₂ − 1₂ − 1₂ = 0₂ and borrow 1 bit forward. Two spikings were sent by σ_minuend, one spiking was sent by σ_addend, and one spiking was retained in σ_Sub. Rule a⁴/a³ → ƛ means that 3 spikings in σ_Sub are consumed, 1 spiking is reserved (representing forward borrowing), and 0 spikings are sent to the environment. That is, the subtraction operation is 0₂ − 1₂ − 1₂ = 0₂, and 1 bit is borrowed forward.

(5)

Rule a⁶ → a⁴ indicates that the highest bit of two binary numbers is carried during calculation in σ_sub, data overflow. A total of 5 spikings come from the σ_aux3 and 1 spiking comes from σ_sub reservation. Rule a⁶ → a⁴ means that 6 spikings in σ_sub are consumed and generate 4 spikings are sent to the environment, indicating data overflow.

In summary, П_Sub1 can correctly calculate the difference between 2 k-bit binary numbers. □

In order to illustrate the operating process of П_Sub1, take the difference between 13 and 7 as an example for explanation. Assuming the current system is 8-bit. The equation 13 − 7 = 6 is expressed as 00001101₂ − 00000111₂ = 00000110₂ in П_Sub1. In the П_Sub1 calculation process, the number of spiking in all neurons and the number of spikings sent to the environment at each time slice are shown in

Table 4. The number of spiking of all neurons in П_Sub1 and the number of spiking sent to the environment during the calculation of 0000101₂ − 00000111₂ = 00000110₂.

t	in1	in2	aux1,0	aux1,1	aux1,2	aux1,3	aux1,4	aux1,5	aux1,6	aux1,7	aux2	aux3	m	s	Sub	out
t = 0	-	-	1	1	0	0	0	0	0	0	0	0	0	0	0	-
t = 1	1	1	1	1	1	0	0	0	0	0	1	0	0	0	0	-
t = 2	0	1	1	1	1	1	1	0	1	1	2	0	0	0	0	-
t = 3	1	1	1	1	1	1	1	1	0	1	3	0	3	1	0	-
t = 4	1	0	1	1	1	1	1	1	1	1	4	1	2	1	2	-
t = 5	0	0	1	1	1	1	1	1	1	0	5	2	3	1	3	0
t = 6	0	0	1	1	1	1	1	1	0	0	6	3	3	0	3	1
t = 7	0	0	1	1	1	1	1	1	0	0	7	4	2	0	2	1
t = 8	0	0	2	2	1	1	1	1	0	0	1	5	2	0	2	0
t = 9	-	-	2	2	0	1	1	1	0	0	1	6	2	0	2	0
t = 10	-	-	2	2	0	0	0	1	0	0	1	7	2	0	2	0
t = 11	-	-	2	2	0	0	0	0	0	0	1	8	0	0	2	0
t = 12	-	-	2	2	0	0	0	0	0	0	1	0	0	0	5	0

. In Table 4, “t” represents the time slice. “in₁” represents the number of spiking in σ_in1. “in₂” represents the number of spiking in σ_in2. “aux_1,i (0 ≤ i ≤ 7)” represents the number of spiking in the auxiliary neuron σ_aux1,i. “aux₂” represents the number of spiking in σ_aux2. “aux₃” represents the number of spiking in σ_aux3. “m” represents the number of spiking in σ_minuend. “s” represents the number of spiking in σ_subtrahend. “Sub” represents the number of spiking in σ_Sub. “out” represent the number of spiking sent to the environment. The 2 k-bit binary numbers input and the calculation results are represented in bold font.

The process of calculating the difference between 0000101₂ and 00000111₂ in П_Sub1 is as follows:

①

Input Auxiliary Module

(1)

At t = 0 time slice, there is one spiking in σ_aux1,0 and σ_aux1,1.

(2)

t = 1 to 7, σ_aux1,0 and σ_aux1,1 send 1 spiking to each other and maintain one spiking in. At the same time, σ_aux1,1 will send one spiking to σ_aux2 and σ_aux1,2. After receiving spiking, these spikings accumulate inside σ_aux2. And at t = 7 time slice, σ_aux2 accumulates 7 spikings. The spiking received by σ_aux1,2 is transmitted along three paths.

The first path: These spikings are transmitted along σ_aux1,3 to σ_m. At t = 3 time slice, σ_m receives the first spiking sent by σ_aux1,3.

The second path: These spikings are transmitted along σ_aux1,4 to σ_m. At t = 3 time slice, σ_m receives the first spiking sent by σ_aux1,4.

The third path: These spikings are sent to σ_aux3 along σ_aux1,4, σ_aux1,5. After receiving the spikings, σ_aux3 accumulates them in the neurons.

(3)

At t = 8 time slice, σ_aux1,0 and σ_aux1,1 sent 1 spiking to each other. And σ_aux1,0, σ_aux1,1 receives 1 spiking from σ_aux2 using rule a⁷ → a. At the same time, σ_aux2 received 1 spiking sent by σ_aux1,1. And when the system stops, there is only 1 spiking in σ_aux2.

(4)

At t = 9 time slice, σ_aux1,0 and σ_aux1,1 stop generating spiking. At the same time, the spiking in σ_aux1,2 is consumed.

(5)

At t = 10 time slice, σ_aux1,0, σ_aux1,1, …, σ_aux1,4 stop generating spiking.

(6)

At t = 11 time slice, 8 spikings sent by σ_aux1,5 are stacked in σ_aux3.

(7)

At t = 12 time slice, there are no rules to execute in the input auxiliary module.

②

Minuend Input

The minuend number transmits along σ_in1, σ_aux1,6, σ_m to σ_sub. When minuend binary bits pass through σ_m, with the assistance of σ_aux1,3 and σ_aux1,4, the spiking corresponding to the transmitted binary number 0 is modified to 2, in order to distinguish it from the spiking corresponding to the subtracted number 0 in the σ_sub. The transmission of the minuend is as follows:

(1)

t = 1 to 8, the corresponding spiking of the minuend binary bits are sequentially received by σ_in1 in order from low to high.

(2)

t = 2 to 9, the corresponding spiking of the minuend binary bits are sequentially received by σ_aux1,6.

(3)

t = 3 to 10, the corresponding spiking of the minuend binary bits are sequentially received by σ_m. At each time slice, σ_m receives 2 spiking sent by σ_aux1,3 and σ_aux1,4.

(4)

t = 4 to 11, the corresponding spiking of the minuend binary bits are sequentially received by σ_sub. In σ_sub, 1 spiking represent binary number 1, and 2 spikings represent binary number 0.

③

Subtrahend Input

Subtrahend are transmitted to σ_sub along σ_in2, σ_aux1,7 and σ_s. The transmission process of subtraction is as follows:

(1)

t = 1 to 8, the corresponding spiking of the subtrahend binary bit is sequentially received by σ_in2 in order from low to high.

(2)

t = 2 to 9, the corresponding spiking of the subtrahend binary bit is sequentially received by σ_aux1,7.

(3)

t = 3 to 10, the corresponding spiking of the subtrahend binary bit is sequentially received by σ_s.

(4)

t = 4 to 11, the corresponding spiking of the subtrahend binary bit is sequentially received by σ_sub. Subtrahend in σ_sub represents binary number 1 with 1 spiking, and 0 spiking represent binary number 0.

④

Subtraction Operation

(1)

t = 1 to 3, there is no spiking in the σ_sub.

(2)

t = 4 to 11, the spiking corresponding to the minuend and subtracted binary bit is received by the σ_sub in order from low to high.

(3)

t = 5 to 12 is the effective output time of П_Sub1. During this time slice, σ_sub sends the calculation result 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 to the environment in order from low to high. At t = 12 time slice, σ_sub receives 5 spikings sent by σ_aux3 using rule a^k → a⁵, and these 5 spikings are stacked in σ_sub, the calculation result did not overflow.

From Table 4, it can be seen that the operation results of the 2 natural numbers are 00000110₂, which is 6. The result is correct and verified that П_Sub1 can correctly perform subtraction operations on two binary numbers.

4.2. An LHSNP System with 1 Input Neuron for 2 Number Subtraction

The LHSNP system П_Sub2 with one input neuron that implements any two k-bit binary number subtraction is shown in Formula (6). The structure of the П_Sub2 system is shown in Figure 4. In Figure 4, the solid arrows represents the directed connection between two neurons. The dashed arrows indicates the omission of connections between multiple neurons. The П_Sub2 design idea is as follows: ① The system input part is divided into two modules, namely the input module and the minuend cache module. The input module consists of an input assist module and an input selection module. The input auxiliary module controls the transmission of the minuend through σ_aux4, and the subtrahend is transmitted through the subtrahend neuron σ_s. ② σ_mi (0 ≤ i ≤ k − 1) in the minuend catch module is used to cache the spiking corresponding to each bit of the minuend. When the minuend passes through σ_m0, with the assistance of the input auxiliary module, adjust the spiking represents the binary number 0 in σ_m0. The purpose is to distinguish the spiking corresponding to the subtrahend binary number 0 in σ_Sub. ③ Minuend and subtrahend are calculated in the subtraction operation neuron σ_Sub, and the operation results are sent to the environment in order from low to high. ④ Overflow monitoring neuron σ_aux5 marks the carry after the end of the highest-bit calculation in σ_Sub. If there is a carry, it stands the calculation result overflows.

The rules in П_Sub2 are divided into 5 groups: (1) Homogeneous neurons: auxiliary neurons, minuend cache neurons (m_i (1 ≤ i ≤ k − 1)), and input neurons with a rule set of R = {a → a}; (2) The rule set for minuend spiking adjustment neuron σ_m0 is R_m = {a² → a²; a³ → a}; (3) Overflow detection neuron σ_aux5 use rule set R_aux5 = {a^k → a⁵}; (4) Subtrahend neuron σ_s use rule set R_s = {a → ƛ; a² → ƛ; a³ → a}; (5) Subtraction operator neuron σ_Sub use rule set R_Sub = {a → a; a² → ƛ; a³/a² → a; a⁴/a³ → ƛ; a⁶ → a⁴}.

The formal definition of this system is as follows:

П_Sub2 = (O, σ_in, σ_aux1,0, σ_aux1,1, …, σ_{aux1,k + 1}, σ_aux2,0, σ_aux2,1, σ_aux2,2, σ_aux3, σ_aux4, σ_aux5, σ_m0, σ_m1, …, σ_mk−1, σ_s, σ_Sub, syn, Input, out)

(6)

where:

(1)

O= {a};

(2)

σ_in = (0, R_aux);

(3)

σ_aux1,i = (0, R_aux), i = 0, 1;

(4)

σ_aux1,i = (1, R_aux), i = 2, …, k + 1;

(5)

σ_aux2,i = (0, R_aux), i = 0, 1, 2;

(6)

σ_auxi = (0, R_aux), i = 3, 4;

(7)

σ_aux5 = (0, R_aux5);

(8)

σ_m0 = (0, R_m);

(9)

σ_mi = (0, R_aux), i = 1, 2, …, k − 1;

(10)

σ_s = (0, R_s);

(11)

σ_Sub = (0, R_Sub);

(12)

syn = {(in, aux₄), (in, s), (s, Sub), (aux₄, m_k−1), (m₀, Sub), (aux_1,1, aux_1,0), (aux_1,k−1, aux₃), (aux_1,k−1, aux₃), (aux₃, aux_1,1), (aux₃, aux_1,0), (aux_{1,k + 1}, aux_2,0), (aux_{1,k + 1}, aux_2,1), (aux_2,0, aux₄), (aux_2,1, aux₄), (aux_2,0, m₀), (aux_2,1, m₀), (aux_2,1, aux_2,2), (aux_2,1, s), (aux_2,2, aux₅), (aux₅, Sub), (s, Sub)}∪{(aux_1,i, aux_{1,i + 1}), i ∈ {0, 1, …, k}}∪{(m_i−1, m_i), i ∈ {1, 2, …, k}};

(13)

in = Input;

(14)

out = Sub.

Analyzing П_Sub2 and its rule set, it can be seen that П_Sub2 contains 9 rules with 2k + 11 neurons, and completing 2 k-bit binary subtraction operations requires 2k + 3 time slices. Furthermore, we have the following conclusion:

Theorem 4.

П_Sub2 can perform any 2 k (k ≥ 5) bit binary number subtraction operations with one input neuron. Namely, after receiving binary number spiking in order from low to high, П_Sub2 can correctly perform subtraction and output the operation results to the environment in order from low to high.

Proof of Theorem 4.

Let t represent the time slice. When the initial state t = 0, there is one spiking in σ_aux1,0 and σ_aux1,1. Starting from t = 1, two binary subtractions are received by σ_in in order from low to high. When the binary bit is 1, σ_in receives 1 spiking, otherwise 0 spiking. The minuend bits are sequentially passed to σ_Sub through σ_aux4 and the σ_mi (0 ≤ i ≤ k − 1) in the minuend cache module to participate in the subtraction operation. The subtrahend bits are sequentially passed to σ_Sub through σ_s to participate in the subtraction operation. The calculation process of П_Sub2 is as follows:

①

Input Auxiliary Module

The function of the input assist module is to distinguish the subtrahend and the minuend and monitor whether the highest-bit calculation result in the σ_Sub overflows. During the time from t = 1 to k + 1, the input auxiliary module does not generate spiking output. During this period, the spiking sent by σ_in is sent to the neurons of the minuend cache module via σ_aux4. And at the same time, rule a³ → ƛ is firing in σ_s. At time t = k + 2, σ_aux2,0 and σ_aux2,1, respectively, send 1 spiking to σ_aux4 to maintain at least 2 spiking in σ_aux4, thereby preventing the subtrahend bits input from σ_in from entering the neurons of the minuend cache module. At the same time, σ_s receives 1 spiking sent by σ_aux2,0 and σ_aux2,1, respectively, to maintain at least 2 spikings, So that the subtrahend bits input from σ_in enters σ_Sub for subtraction operation. The operation process of the input auxiliary module is as follows:

(1)

t = 0, there is 1 spiking in σ_aux1,0 and σ_aux1,1.

(2)

t = 1 to k + 1, σ_aux1,0 and σ_aux1,1 send 1 spiking to each other and maintain one spiking. At the same time, σ_aux1,1 sends 1 spiking to σ_aux1,2 at each time slice, and these spiking will be transmitted sequentially along σ_aux1,2, σ_aux1,3, …, σ_{aux1,k + 1}. At time t = k − 1, σ_aux3 receives 1 spiking sent by σ_auxk−1. At t = k time slice, σ_aux1,0 and σ_aux1,1, respectively receive 1 spiking sent by each other, and σ_aux3 sent 1 spiking to σ_aux1,0 and σ_aux1,1. It truncate the input to the auxiliary module for continuous spiking generation. At time t = k, the spiking in σ_aux1,2 are cleared.

(3)

t = k + 2 to 2k + 1, the input auxiliary module will continue to generate spiking output. σ_aux2,0 and σ_aux2,1 send 1 spiking to σ_aux4, σ_m0, σ_ms at each time slice. Send spiking to σ_aux4 to truncate the spiking corresponding to the subtraction bit and transmit it through σ_aux4. Send 1 spiking to σ_m0, respectively, to modify the spiking corresponding to the binary number 0 in the subtrahend number. Send spiking to the σ_ms to transmit the subtraction through the σ_ms. σ_aux2,1 also sends 1 spiking to σ_aux2,2 at each time slice, and σ_aux2,2 receives the spiking and sends it to σ_aux5, which accumulates in σ_aux5. Input the spiking in σ_aux1,3, …, σ_{aux1,k + 1}, σ_aux2,0 and σ_aux2,1 of the auxiliary module in each time slice and clear them sequentially. At t = 2k + 1 time slice, σ_aux2,0 and σ_aux2,1 stops generating spiking output.

(4)

t = 2k + 2, in the input auxiliary module, σ_aux2,2 send 1 spiking to σ_aux5. And the spiking in σ_aux2,2 is cleared. At this time, 8 spikings are accumulated in σ_aux5, and the input auxiliary module stops generating spiking inputs.

(5)

t = 2k + 3, there are no rules can be firing in the input auxiliary module.

②

Minuend Input

The bits of the minuend sent by σ_in are passed to σ_Sub through σ_aux4 and the σ_mi (0 ≤ i ≤ k − 1) in the minuend cache module to participate in the subtraction operation. At t = 1 to k time slice, all the minuend bits are received by σ_in. At t = 1 to k + 2 time slice, the minuend cache module does not generate spiking output. At t = k + 3 to 2k + 2 time slice, σ_s sends the minuend bits to σ_Add at each time slice. The input process of the minuend is as follows:

(1)

t = 1 to k, the spiking corresponding to the minuend bits are received by σ_in in order from low to high. At t = k time slice, the input of the minuend is completed. At each time slice, these spikings are transmitted sequentially along σ_aux4, σ_sumk−1, σ_sumk−2, …, σ_sum0. At t = 2 to k + 1 time slice, σ_s receives the spiking sent by σ_in at each time slice. This part of the spiking is forgotten by the rule a → ƛ in σ_s.

(2)

t = k + 1 to 2k + 2, the corresponding spiking of the minuend is sequentially transmitted to σ_Sub along σ_aux4, σ_sumk−1, σ_sumk−2, …, σ_sum0, while the spiking in the neuron is sequentially cleared. At t = k + 2 to 2k + 1 time slice, the corresponding spiking of the minuend is sequentially received by σ_sum0, and at the same time, σ_sum0 also receives 1 spiking sent by σ_aux2,0, σ_aux2,1 at each time slice. At t = k + 3 to 2k + 2 time slice, the spiking corresponding to the minuend bits are received by σ_Sub in order from low to high. At t = 2k + 2 time slice, there is no spiking in the minuend cache module.

③

Subtrahend Input

The bits of the subtrahend sent by σ_in are passed to σ_Sub through σ_s to participate in the subtraction operation. At t = k + 1 to 2k time slice, all subtrahend bits are received by σ_in. At t = k + 3 to 2k + 2 time slice, σ_s sends the subtrahend bits to σ_Sub at each time slice. The input process for subtrahend is as follows:

(1)

t = 1 to k + 1, σ_s does not generate spiking output.

(2)

t = k + 1 to 2k, the corresponding spiking of the subtrahend is received by σ_in in order from low to high. At t = 2k time slice, the subtrahend input is completed. At each time slice, these spikings are sequentially transmitted along σ_s to σ_Sub.

(3)

t = k + 2 to 2k + 1, σ_s receives spiking sent by σ_in and 1 spiking sent by σ_aux2,0, σ_aux2,1 at each time slice.

(4)

t = k + 3 to 2k + 2, the spiking corresponding to the subtrahend is received by σ_Sub in order from low to high. At t = 2k + 2 time slice, there is no spiking in σ_s.

④

Subtraction Operation

(1)

t = 1 to k + 2, σ_Sub has no spiking input.

(2)

t = k + 3 to 2k + 2, the spiking corresponding to the minuend and subtrahend bits received by σ_Sub in order from low to high.

(3)

t = k + 4 to 2k + 3, σ_Sub will send the settlement results to the environment in order from low to high. At t = 2k + 2 time slice, the highest order of the two subtractions is calculated in σ_Sub. At t = 2k + 3 time slice, σ_Sub receives 5 spiking sent by σ_aux5. If a carry is generated at 2k + 2 time slice, then there are 6 spikings in σ_Sub. In the 2k + 4 time slice, the environment will receive 4 spikings sent by σ_Sub after using rule a⁶ → a⁴, indicating data overflow. If there is no carry generation at 2k + 2 time slice, then there are 5 spiking in σ_Sub without using any rules.

In summary, the LHSNP system composed of П_Sub2 can correctly calculate the difference between two k-bit binary numbers. □

To illustrate the operation process of П_Sub2, the difference between 13 and 7 is calculated. If the current system has 8-bit (i.e., k = 8), then 13 − 7 = 6 is represented as 00001101₂ − 00000111₂ = 00000110₂ in П_Sub2. In the П_Sub2 calculation process, the number of spiking in all neurons at each time slice and the number of spiking sent to the environment are shown in

Table 5. The number of spiking of all neurons in П_Sub2 and the number of spiking sent to the environment during the calculation of 00001101₂ − 00000111₂ = 00000110₂.

t	in	aux4	m7	m6, …, m1	m0	aux1,0	aux1,1	aux1,2	aux1,3, …, aux1,8	aux1,9	aux2,0	aux2,1	aux2,2	aux3	aux5	s	Sub	out
t = 0	-	0	0	…	0	1	1	0	…	0	0	0	0	0	0	0	0	-
t = 1	1	0	0	…	0	1	1	1	…	0	0	0	0	0	0	0	0	-
t = 2	0	1	0	…	0	1	1	1	…	0	0	0	0	0	0	1	0	-
t = 3	1	0	1	…	0	1	1	1	…	0	0	0	0	0	0	0	0	-
t = 4	1	1	0	…	0	1	1	1	…	0	0	0	0	0	0	1	0
t = 5	0	1	1	…	0	1	1	1	…	0	0	0	0	0	0	1	0	-
t = 6	0	0	1	…	0	1	1	1	…	0	0	0	0	0	0	0	0	-
t = 7	0	0	0	…	0	1	1	1	…	0	0	0	0	1	0	0	0	-
t = 8	0	0	0	…	0	2	2	1	…	1	0	0	0	1	0	0	0	-
t = 9	1	0	0	…	0	3	3	0	…	1	1	1	0	1	0	0	0	-
t = 10	1	3	0	…	3	4	4	0	…	1	1	1	1	1	0	3	0	-
t = 11	1	6	0	…	2	5	5	0	…	1	1	1	1	1	1	3	2	-
t = 12	0	9	0	…	3	6	6	0	…	1	1	1	1	1	2	3	3	0
t = 13	0	11	0	…	3	7	7	0	…	1	1	1	1	1	3	2	3	1
t = 14	0	13	0	…	2	8	8	0	…	1	1	1	1	1	4	2	2	1
t = 15	0	15	0	…	2	9	9	0	…	1	1	1	1	0	5	2	2	0
t = 16	0	17	0	…	2	9	9	0	…	0	1	1	1	0	6	2	2	0
t = 17	-	19	0	…	2	9	9	0	…	0	0	0	1	0	7	2	2	0
t = 18	-	19	0	…	0	9	9	0	…	0	0	0	0	0	8	0	2	0
t = 19	-	19	0	…	0	9	9	0	…	0	0	0	0	0	0	0	5	0

. In Table 5, “t” represents the time slice. “in” represents the number of spiking in σ_in. “aux_1,i (0 ≤ i ≤ k + 1), aux_2,i (0 ≤ i ≤ 2), aux₃, and aux₄” represent the number of spiking in the auxiliary neuron. “aux₅” represents the number of spiking in the overflow monitoring neuron σ_aux5. “m_i (0 ≤ i ≤ k − 1)” represents the number of spiking in the minuend auxiliary meridian element σ_mi (0 ≤ i ≤ k − 1). “s” represents the number of spiking in the subtrahend neuron σ_s. “Sub” represents the number of spiking in the subtraction operation neuron σ_Sub. “out” represents the number of spiking sent to the environment. “m₆, …, m₁” indicates the omission of spiking from σ_m6 to σ_m1. “aux_1,3, …, aux_1,8” indicates the omission of spiking from σ_aux1,3 to σ_aux1,8. The 2 k-bit binary numbers input and the calculation results are represented in bold font.

The process of calculating the difference between 00001101₂ and 00000111₂ in П_Sub2 is as follows:

①

Input Auxiliary Module

(1)

The spikingin the input auxiliary module is transmitted along σ_aux1,2, σ_aux1,3, …, σ_aux1,9, and they are all homogeneous neurons, so the cases of aux_1,3-aux_1,8 are omitted in Table 5. t = 0, σ_aux1,0 and σ_aux1,1 each have 1 spiking.

(2)

t = 1 to 7, σ_aux1,0 and σ_aux1,1 sends 1 spiking to each other. And σ_aux1,1 also sends 1 spiking to σ_aux1,2 at each time slice, and these spiking are transmitted sequentially along σ_aux1,3, σ_aux1,4, …, σ_aux1,9.

(3)

t = 7 to 14, σ_aux3 receives 1 spiking sent by σ_aux1,7 at each time slice, and these spiking are, respectively, sent to σ_aux1,0, σ_aux1,1 through σ_aux3 and stacked in it. At t = 8 time slice, σ_aux1,0, σ_aux1,1 receives 1 spiking sent by each other and 1 spiking sent by σ_aux3, truncating the continuous generation of spiking in the input auxiliary module.

(4)

t = 9 to 18, the spiking of σ_aux1,2, σ_aux1,3, …, σ_aux1,9, (σ_aux2,0, σ_aux2,1), σ_aux2,2 in the input auxiliary module are sequentially cleared. At t = 10 to 17 time slice, σ_aux2,0, σ_aux2,1 continuously generates spiking output, while σ_aux2,1 also continuously sends spiking to σ_aux2,2. After receiving the spiking, σ_aux2,2 continuously sends the spiking to σ_aux5 and accumulates it. At t = 18 time slice, there are 8 spiking stacked in σ_aux5.

(5)

t = 19, there are no rules to execute in the input auxiliary module.

②

Minuend Input

The spiking in the minuend cache module is transmitted along σ_m7, σ_m6, …, σ_m0, and are all homogeneous neurons, the cases of m₆–m₁ are omitted in Table 5.

(1)

t = 1 to 8, the spiking corresponding to the minuend bits are received by σ_in in the order of 1, 0, 1, 1, 0, 0, 0, 0, 0. These spikings are transmitted sequentially to σ_Sub along σ_aux4, σ_m7, σ_m6, …, σ_m0.

(2)

t = 2 to 9, the minuend bits are sequentially received by σ_aux4 and σ_s. During this time slice, the spiking received by σ_s is consumed by the forgetting rule a → ƛ.

(3)

t = 10 to 17, the minuend bits are sequentially received by σ_m0, and at each time slice σ_aux2,0 and σ_aux2,1 is also sent a spiking to σ_m0.

(4)

t = 11 to 18, the corresponding spiking 1, 2, 1, 1, 2, 2, 2, 2, 2, 2 of the minuend bits are sequentially sent to σ_sub.

③

Subtrahend Input

The spiking corresponding to the subtrahend bits is received by σ_in in descending order and then transmitted along σ_s to the σ_sub. The transmission of the subtrahend is as follows:

(1)

t = 0 to 8, σ_s did not generate spiking output.

(2)

t = 9 to 16, the spiking corresponding to the subtrahend bits are received by σ_in in the order of 1, 1, 1, 0, 0, 0, 0, 0, 0 from low to high.

(3)

t = 10 to 17, the corresponding spiking of the subtrahend bits are sequentially received by σ_s. At the same time, σ_s also receives 1 spiking sent by σ_aux2,0, σ_aux2,1 at each time slice. σ_s has 3, 3, 3, 2, 2, 2, 2, 2 spiking in each time slice, using rule a² → ƛ or a³ → a direction sends spiking to σ_sub.

(4)

t = 11 to 18, the spiking corresponding to the subtrahend bits 1, 1, 1, 0, 0, 0, 0, 0 is sequentially received by σ_sub.

④

Subtraction Operation

At t = 12 to 19 time slice, σ_sub sequentially sends the calculation results to the environment. After the calculation of the highest bits of the two subtractions in σ_sub is completed, the spiking sent by σ_aux5 is used to detect whether there is a carry generation. If there is a carry generation, the rule a⁶ → a⁴ is used to send 4 spiking to the environment, indicating data overflow. The calculation process is as follows:

(1)

t = 1 to 11, σ_sub did not generate spiking output.

(2)

t = 11 to 18, the minuend and subtrahend bits are sequentially received by σ_sub, and σ_sub has 2, 3, 3, 2, 2, 2, 2, 2 spiking in each time slice.

(3)

t = 12 to 19, σ_sub sends the operation results 0, 1, 1, 0, 0, 0, 0, 0 to the environment in sequence. At t = 19 time slice, σ_sub received 5 spikings sent by σ_aux5, no rules can be used, and there is no data overflow.

From Table 5, it can be seen that the operation result of two natural numbers is 00000110₂ = 6, which is correct and verifies that the system can achieve subtraction operation.

4.3. An LHSNP System with 1 Input Neuron for n-Subtraction

П_Sub2 can only perform subtraction operations on 2 k-bit binary numbers, which has limitations in practical applications. Therefore, we have made improvements to П_Sub2. The improved LHSNP system П_Sub3 with one input neuron can perform subtraction operations on any n k-bit numbers (k ≥ 5). The structure of П_Sub3 is shown in Figure 5. In Figure 5, the solid arrows represents the directed connection between two neurons. The dashed arrows indicates the omission of connections between multiple neurons. Due to the similarity between П_Sub3 and П_Sub2, the formal definition of П_Sub3 has been omitted.

The design idea of П_Sub3 is as follows: ① The system input section consists of two modules, namely the input module and the minuend cache module. The input module consists of an input auxiliary module and an input selection module. The input auxiliary module controls the minuend number to be transmitted through σ_aux4, and the subtrahend number to be transmitted through σ_s. ② Spiking control neuron σ_aux3 controls σ_aux1,0 and σ_aux1,1 to stop generating spiking output. ③ When two subtrahends are performing subtraction operations in σ_sub, σ_sub sends the operation results to both the environment and the subtrahend cache module. The spiking waiting stored in the minuend cache module completes the subtraction operation with the next subtrahend in σ_sub to achieve accumulated subtract. ④ During the process of accumulating subtract, the high-order detection neuron σ_aux5 sends 5 spikings to detect whether the calculation results of the two highest orders of subtraction overflow. Five rules have been designed in σ_sub to determine whether the highest calculation result overflows. If the calculation result overflows, it sends 4 spikings each to the environment and overflow monitoring neuron σ_OF. ⑤ When the calculation result overflows, σ_OF will generate spiking output to truncate the transmission of spikings in П_Sub3 and cause П_Sub3 to stop running.

The rules in П_Sub2 are divided into seven groups: (1) Homogeneous neurons: auxiliary neurons, minuend cache neurons σ_mi (1 ≤ i ≤ k − 1), and input neurons use rule set R = {a → a}. (2) Spiking control (neuron σ_aux3) uses rule set R_aux3 = {a^(n−1)k → a}. (3) Binary highest bit detection (neuron σ_aux5) uses rule set R_aux5 = {a^k → a⁵}. (4) Minuend spiking adjustment (neuron σ_m0) uses rule set R_m = {a² → a²; a³ → a}. (5) Subtrahend (neuron σ_s) uses rule set R_s = {a → ƛ; a² → ƛ; a³ → a}. (6) Subtrahend operator (neuron σ_Sub) uses rule set R_Sub = {a → a; a² → ƛ; a³/a² → a; a⁴/a³ → ƛ; a⁵ → ƛ; a⁶ → a; a⁷ → ƛ; a⁸ → a⁴; a⁹ → a⁴}. (7) Overflow monitoring neuron (neuron σ_OF) uses rule set R_OF = {a → ƛ; a⁴ → a⁴}.

Analyzing the structure diagram of П_Sub3, it can be seen that П_Sub3 contains 2k + 10 neurons with 15 rules, and completing the n k-bit binary number subtraction operation requires nk + 5 time slices.

To illustrate the operation process of П_Sub3, an example is used to calculate the difference between 13, 15, and 8. If the current system is 8-bit, i.e., k = 8. Then 13 − 15 − 8 = −10 in the П_Sub3 is represented as 00001101₂ − 00001111₂ − 00001000₂ = −00001010₂ (calculation result overflow). In the calculation process of П_Sub3, the number of spiking in all neurons and the number of spiking sent to the environment at each time slice are shown in

Table 6. The number of spiking of all neurons in П_Sub3 and the number of spiking sent to the environment during the calculation of 00001101₂ − 00001111₂ − 00001000₂ = − 00001010₂ (data overflow).

t	in	aux4	m7	m6, …, m2	m1	m0	s	aux1,0	aux1,1	aux1,2	aux1,3, …, aux1,7	aux1,8	aux2,0	aux2, 1	aux3	aux5	Sub	out	OF
t = 0	-	0	0	…	0	0	0	1	1	0	…	0	0	0	0	0	0	-	0
t = 1	1	0	0	…	0	0	0	1	1	1	…	0	0	0	1	0	0	-	0
t = 2	0	1	0	…	0	0	1	1	1	1	…	0	0	0	2	0	0	-	0
t = 3	1	0	1	…	0	0	0	1	1	1	…	0	0	0	3	0	0	-	0
t = 4	1	1	0	…	0	0	1	1	1	1	…	0	0	0	4	0	0	-	0
t = 5	0	1	1	…	0	0	1	1	1	1	…	0	0	0	5	0	0	-	0
t = 6	0	0	1	…	0	0	0	1	1	1	…	0	0	0	6	0	0	-	0
t = 7	0	0	0	…	0	0	0	1	1	1	…	0	0	0	7	0	0	-	0
t = 8	0	0	0	…	0	0	0	1	1	1	…	1	0	0	8	0	0	-	0
t = 9	1	0	0	…	1	0	0	1	1	1	…	1	1	1	9	0	0	-	0
t = 10	1	3	0	…	0	3	3	1	1	1	…	1	1	1	10	0	0	-	0
t = 11	1	6	0	…	1	2	3	1	1	1	…	1	1	1	11	1	2	-	0
t = 12	1	9	0	…	1	3	3	1	1	1	…	1	1	1	12	2	3	0	0
t = 13	0	12	0	…	0	3	3	1	1	1	…	1	1	1	13	3	3	1	1
t = 14	0	15	0	…	0	2	2	1	1	1	…	1	1	1	14	4	3	1	1
t = 15	0	16	0	…	0	2	2	1	1	1	…	1	1	1	15	5	3	1	1
t = 16	0	18	0	…	0	2	2	1	1	1	…	1	1	1	16	6	3	1	1
t = 17	0	20	0	…	0	2	2	2	2	1	…	1	1	1	1	7	3	1	1
t = 18	0	22	0	…	1	2	2	2	2	0	…	1	1	1	1	8	3	1	1
t = 19	0	24	0	…	1	3	2	2	2	0	…	1	1	1	1	1	8	1	1
t = 20	1	26	0	…	1	3	2	2	2	0	…	1	1	1	1	2	1	4	4
t = 21	0	29	0	…	5	7	7	6	6	0	…	5	1	1	1	3	7	1	1
t = 22	0	31	0	…	5	9	9	6	6	0	…	5	0	0	1	4	0	0	0

. In Table 6, t represents time slice. “in” represents the number of spiking sent by subtraction to neuron σ_in. “aux_1,i (0 ≤ i ≤ k)” represents the number of spiking in auxiliary neuron σ_aux1,i (0 ≤ i ≤ k). “aux_1,3, …, aux_1,7” indicates omitting the number of spiking in the description σ_aux1,3, …, σ_aux1,7. “aux_2,0, aux_2,1” represents the number of spiking in the auxiliary neuron σ_aux2,0, σ_aux2,1. “aux_i (3 ≤ i ≤ 5)” represents the auxiliary neuron the number of spiking in σ_auxi (3 ≤ i ≤ 5). “m_i (0 ≤ i ≤ k − 1)” represents the number of spiking in the minuend auxiliary neuron σ_mi (0 ≤ i ≤ k). “m₆, …, m₂” indicates omitting the number of spiking in the description m₆, …, m₂. “s” represents the number of spiking in the minuend auxiliary neuron σ_s. “Sub” represents the number of spiking in the subtractive operation neuron σ_Sub. “out” represents the number of spiking sent to the environment. “OF” represents the number of spikings in the overflow monitoring neuron σ_OF. The input n k-bit binary subtractions and calculation results are represented in bold font.

From Table 6, it can be seen that the operation result of the three natural numbers is 0011₂, which is correct and verifies that the system can perform subtraction operations.

The process of calculating the difference between 00001101₂, 00001111₂, and 00001000₂ in П_Sub3 is as follows:

①

Input Auxiliary Module

(1)

The spikings continuously sent by σ_aux1,1 in the auxiliary module are transmitted along σ_aux1,2, σ_aux1,3, …, σ_aux1,8. And these neurons are homogeneous neurons. So, we omit the description of the spiking situation of aux_1,3, …, aux_1,7 in Table 6. t = 0, there is 1 spiking in σ_aux1,0 and σ_aux1,1.

(2)

t = 1 to 17, σ_aux1,0 and σ_aux1,1 sends 1 spiking to each other. And σ_aux1,1 also sends 1 spiking to σ_aux3 at each time slice. These spikings are stacked in σ_aux3. At t = 16 time slice, σ_aux3 accumulates 16 spikings in neurons. σ_aux1,1 also sends 1 spiking to σ_aux1,2 at each time slice. And these spikings are transmitted sequentially along σ_aux1,3, σ_aux1,4, …, σ_aux1,8, (σ_aux2,0, σ_aux2,1). At t = 1 to 9 time slice, the input auxiliary module does not generate spiking output. At each time slice after t = 10, the input auxiliary module generates spiking output, σ_aux2,0 and σ_aux2,1 send one spiking to σ_aux4, σ_m0, σ_s at each time slice. At the same time, σ_aux2,1 also sends one spiking to σ_aux5, which is stacked in σ_aux5 until the number of spikings reaches 8. Then, use the rule a⁸ → a⁵ to consume spikings. At t = 17, σ_aux1,0 and σ_aux1,1 receive 1 spiking sent to each other. σ_aux3 uses rule a¹⁶ → a consume 16 spikings and generates 1 spiking output.

(3)

t = 18 to 22, σ_aux1,0, σ_aux1,1 no longer generates spiking output. The spikings in σ_aux1,2, σ_aux1,3, σ_aux1,4 are sequentially cleared. At t = 21 time slice, σ_aux1,0, σ_aux1,1, σ_aux1,2, σ_aux1,3, …, σ_aux1,8 simultaneously receives 4 spikings sent by σ_OF, truncating the transmission of spiking in the input auxiliary module.

②

Minuend Input

The corresponding spiking of the minuend bit is received by σ_in and transmitted along σ_aux4, σ_m7, σ_m6, …, σ_m0 to the σ_sub. The transmission process of the minuend is as follows:

(1)

t = 1 to 8, the corresponding spiking of the minuend bit is received by σ_in, and these spikings are transmitted along σ_aux4, σ_m7, σ_m6, …, σ_m0.

(2)

t = 2 to 9, σ_in simultaneously sends spiking to σ_aux4 and σ_s. After receiving the spiking, σ_aux4 passes the spiking to the minuend cache module. After receiving spiking, σ_s does not generate spiking output, and these spiking are consumed by the forgetting rule a → ƛ in σ_s.

(3)

t = 10 to 17, the corresponding spiking of the first minuend bit is sequentially received by σ_m0. And at each time slice, σ_m0 also receives 1 spiking sent by σ_aux2,0 and σ_aux2,1. In σ_m0, the spiking corresponding to the minuend binary number 0 is changed to 2 through the rule a² → a², in order to distinguish it from the spiking corresponding to the subtrahend binary number 0.

(4)

t = 11 to 18, the spikings 1, 2, 1, 1, 2, 2, 2, 2 corresponding to the first minuend bit are sequentially received by σ_Sub. A total of 1 spiking represents the minuend number 1₂, and 2 spikings represent the minuend number 0₂.

(5)

From t = 12 to the system stops, σ_m6 receives spikings (i.e., calculation results) sent by σ_Sub at each time slice. And these spikings are transmitted along σ_m5, σ_m4, …, σ_m0 to σ_Sub achieve accumulate plus with the next subtrahend. At t = 20 time slice, σ_m6 receives 4 spikings sent by σ_Sub, and σ_m6 no longer generates spiking output in the following time. At t = 21 time slice, σ_m5, σ_m4, …, σ_m0 simultaneously receives 4 spikings sent by σ_OF. These spikings truncate the transmission of spiking in the minuend module. And σ_m6 receives 1 spiking sent by σ_Sub.

③

Subtrahend Input

The spiking corresponding to the subtrahend bit is received by σ_in and transmitted along σ_s to σ_Sub. The transmission process of the subtrahend is as follows:

(1)

t = 1 to 8, σ_s does not generate spiking output. And the spiking σ_s received at each time slice has been consumed by the forgetting rule a → ƛ.

(2)

t = 9 to 16, the corresponding spiking 1, 1, 1, 1, 0, 0, 0, 0 of the first subtrahend bit are sequentially received by σ_in. These spikings are transmitted along σ_s to the σ_in.

(3)

t = 10 to 17, σ_s receives the spiking corresponding to the first subtrahend bit sent by σ_in. At the same time, σ_s receives 1 spiking sent by σ_aux2,0 and σ_aux2,1 at each time slice. σ_s uses rule a² → ƛ or a³ → a to consume spikings and send spikings to σ_Sub. From t = 10 to system stop, σ_aux4 receives spiking from σ_in, σ_aux2,0, and σ_aux2,1 at each time slice, these spikings are stacked in σ_aux4. t = 13 to 20, the spiking corresponding to each of the first subtrahend bits, 1, 1, 1, 1, 0, 0, 0, 0 are sequentially received by σ_Sub. In a neuron, 1 spiking represents the binary number 1₂, and 0 spiking represents the binary number 0₂.

(4)

From 17 to 22, the spiking 0, 0, 0, 1, 0, 0 corresponding to the second subtrahend are received by σ_in. These spikings are transmitted along σ_s to the σ_Sub. The transmission process is consistent with the first subtrahend. At t = 21 time slice, 4 spikings sent by σ_OF are received in σ_s, and the subtrahend transmission is truncated.

④

Subtraction Operation

(1)

t = 1 to 10, σ_Sub has no spiking input.

(2)

t = 11 to 18, the spiking corresponding to the first minuend and each subtrahend bit is received by σ_Sub in order from low to high.

(3)

t = 12 to 19, σ_Sub sends the calculation results to the environment, σ_OF, and σ_m6 simultaneously at each time. If σ_OF receives 1 spiking, it consumes the spiking by forgetting rule a → ƛ. After receiving the spiking in σ_m6, these spikings are transmitted along σ_m5, σ_m4, …, σ_m0 to the σ_sub to achieve accumulate subtract with the next subtrahend. At t = 19 time slice, the highest bit of the first minuend and subtrahend are received by σ_sub. And at the same time, σ_sub received 5 spikings sent by σ_aux5 after using the rule a⁸ → a⁵. At this time, σ_sub has 8 spikings.

(4)

t = 20, the environment, σ_OF, and σ_m6 receives four spikings sent by σ_Sub after using rule a⁸ → a⁴. It represents data overflow. At the same time, 1 spiking sent by σ_m0 was received in the σ_Sub.

(5)

At t = 21, σ_m5, σ_m4, …, σ_m0, σ_aux1,0, σ_aux1,1, …, σ_aux1,8, σ_s, σ_Sub simultaneously receives 4 spikings sent by σ_OF after using rule a⁴ → a⁴. It truncates the transmission of spiking in П_Sub3. At the same time, σ_Sub sends 1 spiking to the environment, σ_OF, and σ_m6, respectively.

(6)

At t = 22, there are no rules can be fired in П_Sub3.

4.4. Comparison

This section implements three different types of LHSNP systems П_Sub1, П_Sub2, and П_Sub3 for subtraction. The three LHSNP systems designed in this article and the SN P system designed in [23] require the number of neurons, the time required to complete the operation, and the number of rules in the system, as shown in

Table 7. Three types of LHSNP system for subtraction.

	SN P System	SN P System with 2 Input for 2 Natural Number Subtraction ПSub1			SN P System with One Input for 2 Natural Numbers Subtraction ПSub2			SN P System with 1 Input for n Natural Numbers Subtraction ПSub3
Parameter
		Number of Neurons	Complete Time	Number of Rules	Number of Neurons	Complete Time	Number of Rules	Number of Neurons	Complete Time	Number of Rules
This work		15	k + 4	9	2k + 11	2k + 3	9	2k + 10	nk + 5	15
Zeng Xiang [23]		12	time free	4	-	-	-	-	-	-

.

The number of neurons required for П_Sub1 is 15, and the time required to complete the calculation is k + 4. The number of rules involved in all neurons in the system is 9. Compared to the SN P system with 12 neurons and 4 rules for subtraction proposed by Zeng Xiangxiang et al. in [23], it has fewer rules and the structure is more concise.

The data of П_Sub2 and П_Sub3 are basically the same. The required number of neurons is 2k + 11 and 2k + 10. The required time to complete the calculation is 2k + 3 and nk + 5. The number of rules involved in all neurons in the system is 9 and 15. Since no SN P system with one input neuron for natural number subtraction has been found in existing references, comparative analysis will not be conducted.

5. Conclusions

Membrane computing as a parallel computing model has been applied in many fields in recent years. Because of the simplicity of the neuron structure, the spiking neural P system especially is considered to be the most promising membrane computing model for hardware implementation. One of the goals of spiking neural P system research is to use fewer neurons and simpler rules.

Based on this, this paper studies the LHSNP system for performing addition and subtraction. And we designed two kinds of LHSNP systems for addition and three kinds of LHSNP systems for subtraction that are performed on the eld of natural numbers. These five LHSNP systems are as follows:

• The LHSNP system П_Add2 with 1 input neuron for any 2 k-bit binary number addition operation;
• The LHSNP system П_Add3 with 1 input neuron for any n k-bit binary number addition;
• The LHSNP system П_Sub1 with 2 input neurons for any 2 k-bit binary number subtraction;
• The LHSNP system П_Sub2 with 1 input neuron for any 2 k-bit binary number subtraction;
• The LHSNP systemП_Sub3 with 1 input neuron for any n k-bit binary number subtraction.

The five LHSNP systems we designed achieved no delay in the system by adding neurons and were weightless from adding rule types. In this case, compared to other SN P systems, our designed LHSNP system reduces the time required to complete arithmetic operations while reducing system complexity. It improved system performance. At the same time, we considered the overflow of the performance results that make the LHSNP system have a higher application value.

In this work, we only studied the LHSNP system to perform addition and subtraction operations. Although multiplication and division can be realized by successive addition and subtraction. But it is more valuable to design an LHSNP system that can directly carry out multiplication and division.