Next Article in Journal
Silicon Carbide Technology for Advanced Human Healthcare Applications
Previous Article in Journal
Design and Modeling of Fiber-Free Optical MEMS Accelerometer Enabling 3D Measurements
 
 
Font Type:
Arial Georgia Verdana
Font Size:
Aa Aa Aa
Line Spacing:
Column Width:
Background:
Article

Polarization Gradient Effect of Negative Capacitance LTFET

Key Laboratory for Wide-Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian University, Xi’an 710071, China
*
Authors to whom correspondence should be addressed.
Micromachines 2022, 13(3), 344; https://doi.org/10.3390/mi13030344
Submission received: 25 January 2022 / Revised: 11 February 2022 / Accepted: 16 February 2022 / Published: 22 February 2022
(This article belongs to the Topic Micro/Nano Satellite Technology, Systems and Components)

Abstract

:
In this paper, an L-shaped tunneling field effect transistor (LTFET) with ferroelectric gate oxide layer (Si: HfO2) is proposed. The electric characteristic of NC-LTFET is analyzed using Synopsys Sentaurus TCAD. Compared with the conventional LTFET, a steeper subthreshold swing (SS = 18.4 mV/dec) of NC-LTFET is obtained by the mechanism of line tunneling at low gate voltage instead of diagonal tunneling, which is caused by the non-uniform voltage across the gate oxide layer. In addition, we report the polarization gradient effect in a negative capacitance TFET for the first time. It is noted that the polarization gradient effect should not be ignored in TFET. When the polarization gradient parameter g grows larger, the dominant tunneling mechanism that affects the SS is the diagonal tunneling. The on-state current (Ion) and SS of NC-LTFET become worse.

1. Introduction

Due to the limitation of SS (60 mV/dec) at room temperature, detrimental effects, such as short channel effect, higher off-state current (Ioff) and subthreshold swing, would appear in the continuous miniaturization of complementary MOS technology [1,2]. It is no longer feasible to reduce power consumption by lowering the supply voltage [3,4]. As a breakthrough, the TFET with a gate-controlled reverse biased p-i-n diode structure is one of candidates for the next generation of low-power devices because of its lower Ioff and steep subthreshold slope [5,6,7,8]. Accordingly, it is a meaningful work to study TFET. Till now, some structures with overlapping gate/channel/source are proposed to increase the Ion and improve the subthreshold characteristic by increasing the effective tunneling area. Others use hetero-materials such as Si/GexSi1−x to form a shorter tunneling path to achieve steeper SS and greater Ion [9,10,11,12]. However, all the above methods are based on the band-to-band tunneling mechanism to change the n factor of SS to obtain better subthreshold characteristics. The expression of SS is as follows [13]:
S S = V G S log 10 I D S = V G S ψ s m × ψ s log 10 I D S n = ( 1 + C d C o x ) × k T q ln 10
where Ψ S is the channel surface potential, Cd is the channel capacitance and Cox is the gate oxide capacitance.
Recently, ferroelectric materials were introduced into the device as a gate oxide layer to obtain a body factor m < 1 and extend the steep-slope region, which provides a new idea for the design and optimization of TFET [13,14,15]. Hu et al. [16] reported a negative capacitance vertical-tunnel FET based on GaAs0.51Sb0.49/In0.53Ga0.47As with large on-current. Saeidi et al. [17] presented a ferroelectric planner TFET with a minimal subthreshold swing. A novel silicon-based dual source U-shaped channel TFET with negative capacitance (NCDU-TFET) was proposed by Wang et al. [2] However, these studies only consider the effects of remnant polarization, coercive electric field and ferroelectric layer thickness on device performance. In the actual ferroelectric layer, the polarization gradient effect is also very important, it should not be ignored. Although Kao et al. [18] have investigated the influence of polarization gradient effect on Fin-FET, the related work about TFET is hardly reported.
LTFET with the ferroelectric gate oxide layer, namely, NC-LTFET, is proposed in this article. Compared with the traditional LTFET, NC-LTFET has a steeper SS (18.4 mV/dec) and greater Ion (2.4 × 10−7 A/μm). We then study the working mechanism of the NC-LTFET. Unlike traditional LTFET, NC-LTFET with a small polarization gradient parameter will be turned on by line tunneling at low voltage instead of diagonal tunneling. Finally, the electrical characteristic parameters of NC-LTFET with different g values are analyzed. This will be of great help in understanding the working mechanism of negative capacitance recessed gate tunneling field effect transistors.

2. Materials and Methods

Figure 1 shows the schematic of LTFET and the proposed NC-LTFET structure. To improve the performance of LTFET, Si: HfO2 (SiO2 doped hafnium oxide) is regarded as gate oxide in the proposed structure. The manufacturing process of Si: HfO2 thin film is compatible with the existing CMOS technology, which lays a good foundation for the preparation of high-performance negative capacitance tunneling transistors. Kim et al. gives the key process steps for manufacturing LTFET [9]. Meanwhile, the manufacturing process of the ferroelectric materials (Si: HfO2) could be obtained from reference [19]. It needs to convert the process steps into a process of ferroelectric material growth when depositing the gate oxide layer. Device parameters of LTFET and NC-LTFET are listed below: gate length, Lg, is 40 nm; gate oxide thickness, Tox, is 2 nm; N+ pocket thickness, Tp, is 5 nm; drain region height, HD, is 20 nm; source region height, HS, is 40 nm; and the buried oxide height, HB, is 80 nm. The doping concentrations of source, drain, pocket and channel are 1 × 1020 cm−3, 1 × 1018 cm−3, 5 × 1018 cm−3 and 1 × 1015 cm−3, respectively. The gate work function is 4.43 eV and drain voltage is 0.5 V.
The simulation of the NC-LTFET is carried out on a Sentaurus simulator. To calculate the band-to-band tunneling and ferroelectric polarization effect, the non-local band-to-band tunneling (BTBT) model and Landau–Khalatnikov equation are applied in this simulation. Compared with the applicable scope of local model, non-local model was usually described as the spatial variation of the energy bands and it is appropriate for simulating arbitrary tunneling barriers involving nonuniform electric field and abrupt/graded heterojunctions. To obtain the performance of all Si-based TFET devices correctly, this paper uses the approach proposed by Biswas et al. [20] with high accuracy. The fitting coefficients of calibrated model are Apath = 1.63 × 1014 cm−3s−1, Bpath = 1.47 × 106 Vcm1 and the corresponding reduced mass is mr = 0.033 × mo.
The Landau–Kalashnikov equation and Gibb’s free energy U of ferroelectric materials/system are described as follows:
ρ d P d t = P U
U = α P 2 + β P 4 + γ P 6 E P g P 2
where ρ is the kinetic coefficient associated with polarization-switching dynamics. Chatterjee et al. [21] reports that the intrinsic delay of a doped hafnium oxide-based ferroelectric is negligible in digital circuits. Thus, the kinetic coefficient of the ferroelectric system is zero. P is the total polarization, E is the electric field of ferroelectric material, and α, β and γ are static coefficients for a ferroelectric material. g is a coupling coefficient for the polarization gradient term of the free energy, typical value of g ranges from 10−6 to 10−2 cm3/F [22]. Figure 2a shows RC network to calibrate the ferroelectric parameters, which consists of an external resistor (capacitor) and a ferroelectric capacitor. According to the recently published experimental data of ferroelectric materials Si: HfO2, the calibration of the P–E curve is shown in Figure 2b [19]. The calibration parameters for the ferroelectric material Si: HfO2 are α = 4.32 × 10 10 cm / F , β = 3.86 × 10 19 cm 5 / FC 2 , γ = 6.48 × 10 29 cm 9 / FC 4 and the corresponding E C = 1   MV / cm and P r = 11.2   μ C / cm 2 .
By combining Equations (2) and (3), the relationship between the electric field and polarization is obtained, as shown in Equation (4):
E = 2 α P + 4 β P 3 + 6 γ P 5 2 g Δ P
Here, is the Laplace operator. Considering that the gate charge is equal to the polarization near the interface between gate and gate oxide P Q g , the voltage across the ferroelectric materials could be expressed as below [18]:
V F E = T o x × ( 2 α Q g + 4 β Q g 3 + 6 γ Q g 5 2 g d 2 Q g d 2 x 2 g d 2 Q g d 2 y )
where Tox is the thickness of ferroelectric oxide. Moreover, mobility with doping and electric field dependence, Shockley–Read–Hall recombination, bandgap narrowing and Fermi statistics are also considered. A detailed description of these device parameters can be found in Table 1, and they are used in the following sections unless stated otherwise.

3. Results

3.1. Performance and Mechanism Comparison of NC-LTFET with LTFET

Figure 3a shows the transfer characteristic curve of NC-LTFET and LTFET at VDS = 0.5 V. In order to intuitively display the change of transfer characteristic curve, the NC-LTFET transfer characteristic curve moves 0.1 V to the right, as the illustration of Figure 3a shows. The SS of NC-LTFET and LTFET is 18.3 mV/dec and 33 mV/dec at the range of drain current from 4 × 10−17 to 1 × 10−9 A/μm, respectively (the SS calculated in this manuscript is average subthreshold swing). The much smaller SS shows that NC-LTFET is more sensitive to the influence of low gate voltage. Moreover, because of its large Ion (2.4 × 10−7 A/μm at VGS = 1 V), NC-LTFET would have a stronger driving capability in digital circuits. Meanwhile, the smaller Ioff (4 × 10−17 A/μm at VGS = 0 V) value, the smaller the static power consumption in the off state. Therefore, NC-LTFET is one of the most promising low-power devices, and further research is needed.
To clarify the working mechanism of NC-LTFET, Figure 3b exhibits the electrostatic potential along A-B direction when Vg = 1 V. Figure 3c gives the band diagram of NC-LTFET and LTFET along A-B direction. Unlike the traditional high-K gate oxide materials (HfO2), ferroelectric material (Si: HfO2) has large remnant polarization, and high depolarization electric field is throughout the ferroelectric bulk. The high depolarization electric field would induce the increase of surface potential in device, which can be clearly observed in Figure 3b. However, the variation can not only cause the downward bending of the energy band, but also expand the range of the overlap area between the conduction band and the valence band, as shown in Figure 3c. The electron/hole transmission probability, T, can be calculated through the Wentzel–Kramers–Brillouin (WKB) method, which is given by the expression in (6) [23]:
T exp ( 4 λ 2 m * E g 3 3 q ( E g + Δ ϕ ) )
where m* is the carriers’ effective mass, Eg is the bandwidth and λ is the effective tunneling length. LTFET and NC-LTFET have the overlapping regions 1 and 2 , respectively. It is easy to infer that the NC-LTFET with greater energy overlapping region 2 will produce a larger band-to-band tunneling rate in the pocket area. Figure 3d reveals the electron band-to-band tunneling rate of NC-LTFET is larger than that of LTFET along the C-D direction, which confirms the previous speculation. Finally, NC-LTFET with larger current density is shown in Figure 3e.
Figure 4a shows the electric field distribution of the LTFET near the source region at VGS = 0.4 V and VDS = 0.5 V. Next, the electrostatic potential of NC-LTFET in Figure 4b is extracted along the cutline C-D marked in the inset. Additionally, the electrostatic potential of the LTFET is extracted in the same way. Obviously, the crowd electric field at the corner of the source region would elevate the surface potential near the corner, which is given as black squares in Figure 4b. However, contrary to the case of LTFET, NC-LTFET has a greater electrostatic potential near the pocket region, instead of the corner region. The change is attributed to the inconsistent rise of the surface potential, which is caused by the difference in the voltage amplification effect along the C-D direction. It could be observed that the surface potential near the pocket region of NC-LTFET is 0.2 V higher than that of traditional LTFET at VGS = 0.4 V and VDS = 0.5 V, but the value is 0.03 V far away from pocket region. At the same time, according to the previous discussion, the greater the surface potential, the greater the downward bending of the energy band, the greater the energy overlap region, and the greater the probability of electron tunneling. Therefore, the introduction of ferroelectric materials would significantly enhance the line tunneling. Figure 4c represents the significant enhancement of line tunneling in NC-LTFET when the gate voltage changes from 0.25 to 0.4 V. Compared with the LTFET, NC-LTFET will be the first to be turned on by line tunneling as shown in Figure 4c. Additionally, the tunneling generation rate of line tunneling in NC-LTFET is much larger than that of diagonal tunneling in LTFET at VGS = 0.25 V. Ultimately, the transfer characteristic curve with ultra-steep SS would be obtained under the low gate voltage.
Figure 5a not only shows the change of gate potential along the C-D direction, but also exhibits the change of surface potential under the gate oxide and the change of the voltage Vox across the gate oxide layer. As previously described, the surface potential of LTFET near the corner region will increase because of the electric field crowding effect. For this reason, the voltage across the gate oxide of LTFET will be the smallest near the source corner and the largest near the source region. Like LTFET, the voltage assigned to the gate oxide layer near the source region of NC-LTFET is higher than voltage assigned to the gate oxide layer near the source corner. Hence, the ferroelectric gate oxide layer near the pocket region would generate larger polarized charges under applied voltage, and establish higher electric field. It can be concluded that the ferroelectric polarization at the corner of the recessed gate would be much smaller than that of near the source region as the black arrow shown in Figure 5b. Finally, as the red arrow shows in Figure 5c, NC-LTFET has a strong voltage amplification effect in the pocket area and starts to weaken at the corner when the gate voltage is 0.4 V. With the help of the non-uniform VFe, the performance of the device would be optimized and the working mechanism would be changed.

3.2. The Impact of Polarization Gradient on NC-LTFET Performance

To further investigate the influence of polarization distribution on the electrical characteristic of NC-LTFET, different polarization gradient parameter g is selected as the variable, and static ferroelectric parameters still remained ( α = 4.32 × 10 10 cm / F , β = 3.86 × 10 19 cm 5 / FC 2 , γ = 6.48 × 10 29 cm 9 / FC 4 ). Note that instead of multidomain state, sections of the FE material are stable in the case of different g values, and the single domain with inhomogeneous polarization (polarization gradient) is considered in this simulation. These g values are 10−4 cm3/F, 5 × 10−3 cm3/F, 10−2 cm3/F, respectively. Figure 6a shows that g has a great impact on the transfer characteristic curve of NC-LTFET, especially in the subthreshold region. When g value changes from 10−4 to 10−2 cm3/F, the SS and drain current would be deteriorated. SS increases with the increase of g value, and the drain current decreases with the increase of g. Therefore, the smaller the g value, the greater the improvement in the device performance. It should be noted that, when the gate voltage is 0.5 V, the drain current is saturated and it decreases a little. Figure 6b shows the SSs with different g values. These SSs are 18.4 mV/dec, 20.8 mV/dec and 23.2 mV/dec, respectively. Additionally, they are calculated by fixing the current range from 4 × 10−17 to 1 × 10−9 A/μm.
Figure 7a shows the ferroelectric polarization of NC-LTFET along C-D direction at different g values. The method of extracting data has been described above. Figure 7b,c show the electrostatic potential and the conduction band energy along C-D direction at different g values, respectively. As shown in Figure 7a, with the increase of the polarization gradient parameter g, the polarization near the pocket region decreases, and the polarization near the corner of NC-LTFET increases. As we discussed previously, the degree of ferroelectric polarization determines the value of surface potential. Accordingly, the electrostatic potential near corner regions increases and near pocket regions decreases with the increase of the polarization gradient parameter g at VGS = 0.25 V. Hence, as shown in Figure 7c, the conduction band energy near the corner is bound to reduce and the conduction band energy near the pocket region is bound to increase. As shown in Figure 7c,d, the tunneling will open at a location with a lower conduction band energy along the C-D direction. When the polarization gradient parameter g grows larger, the dominant tunneling mechanism that affects the SS will change from line tunneling to the diagonal tunneling. Both line tunneling and diagonal tunneling appear in the position along C-D direction. The tunneling mechanism dominated by diagonal tunneling will deteriorate the device performance.

4. Conclusions

This article proposes an L-shaped gate tunneling field effect transistor with a ferroelectric gate oxide layer. Firstly, the characteristics of traditional LTFET and negative capacitance LTFET are compared and discussed. According to the curves obtained in A-B and C-D directions, it can be seen that NC-LTFET has higher potential in the pocket area and deeper band bending will occur, which can help NC-LTFET have a larger current and a steeper SS. In addition, by studying the relationship between voltage and potential at the corner and near the pocket region, it is found that NC-LTFET has strong voltage amplification effect near pocket region. This leads NC-LTFET turns on at first by line tunneling at low gate voltage. Finally, different polarization gradient parameters are used to study the potential and conduction band energy of NC-LTFET. The experiment shows that the higher the parameter g, the smaller the line tunneling rate that will be generated, and the role of diagonal tunneling will be greater, which will further worsen Ion and SS.

Author Contributions

Conceptualization, methodology, formal analysis, visualization, data curation, writing—original draft preparation, H.Z.; Supervision, S.C.; Resources, Project administration, H.L.; Validation, Writing-reviewing and editing, S.W.; Validation, Supervision, Writing—reviewing and editing, D.W.; Writing—reviewing and editing, X.F.; Writing—reviewing and editing, C.C.; Writing—reviewing and editing, C.Y.; Writing-reviewing and editing, T.G. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the National Natural Science Foundation of China (grant No. U1866212), the Laboratory Open Fund of Beijing Smart-chip Microelectronics Technology Co., Ltd. (grant No. SGITZXDDKJQT2002303), and the Innovation Foundation of Radiation Application (grant No. KFZC2018040206).

Informed Consent Statement

Informed consent was obtained from all subjects involved in the study.

Data Availability Statement

Data are contained within the article.

Conflicts of Interest

We declare that we do not have any commercial or associative interest that represents a conflict of interest in connection with the submitted work.

References

  1. Khatami, Y.; Banerjee, K. Steep subthreshold slope n-and p-type tunnel-FET devices for low-power and energy-efficient digital circuits. IEEE Trans. Electron Devices 2009, 56, 2752–2761. [Google Scholar] [CrossRef]
  2. Wang, S.; Chen, X.; Pan, Y.; Jia, Q.; Yin, Y.; Wu, Y.; Wang, Y.; Li, W. Design of negative capacitance tunneling field effect transistor with dual-source U-shape channel, super-steep subthreshold swing and large on-state current. Superlattices Microstruct. 2021, 155, 106905. [Google Scholar] [CrossRef]
  3. Saripalli, V.; Datta, S.; Narayanan, V.; Kulkarni, J.P. Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design. In Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, San Diego, CA, USA, 8–9 June 2011; pp. 45–52. [Google Scholar] [CrossRef] [Green Version]
  4. Tajalli, A.; Leblebici, Y. Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 2011, 58, 2189–2200. [Google Scholar] [CrossRef]
  5. Zhang, Q.; Zhao, W.; Seabaugh, A. Low-subthreshold-swing tunnel transistors. IEEE Electron Device Lett. 2006, 27, 297–300. [Google Scholar] [CrossRef]
  6. Choi, W.Y.; Park, B.; Lee, J.D.; Liu, T.K. Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec. IEEE Electron Device Lett. 2007, 28, 743–745. [Google Scholar] [CrossRef]
  7. Chen, Z.X.; Yu, H.Y.; Singh, N.; Shen, N.S.; Sayanthan, R.D.; Lo, G.Q.; Kwong, D.L. Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires. IEEE Electron Device Lett. 2009, 30, 754–756. [Google Scholar] [CrossRef]
  8. Jhan, Y.; Wu, Y.; Hung, M. Performance Enhancement of Nanowire Tunnel Field-Effect Transistor with Asymmetry-Gate Based on Different Screening Length. IEEE Electron Device Lett. 2013, 34, 1482–1484. [Google Scholar] [CrossRef]
  9. Kim, S.W.; Kim, J.H.; Liu, T.K.; Choi, W.Y.; Park, B. Demonstration of L-Shaped Tunnel Field-Effect Transistors. IEEE Electron Device Lett. 2016, 63, 1774–1778. [Google Scholar] [CrossRef]
  10. Chen, S.; Wang, S.; Liu, H.; Li, W.; Wang, Q.; Wang, X. Symmetric U-Shaped Gate Tunnel Field-Effect Transistor. IEEE Electron Device Lett. 2017, 64, 1343–1349. [Google Scholar] [CrossRef]
  11. Kao, K.; Verhulst, A.S.; Vandenberghe, W.G.; Soree, B.; Groeseneken, G.; de Meyer, K. Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs. IEEE Electron Device Lett. 2012, 59, 292–301. [Google Scholar] [CrossRef]
  12. Shih, C.; Chien, N.D. Design and Modeling of Line-Tunneling Field-Effect Transistors Using Low-Bandgap Semiconductors. IEEE Trans. Electron Devices 2014, 61, 1907–1913. [Google Scholar] [CrossRef]
  13. Kobayashi, M.; Jang, K.; Ueyama, N.; Hiramoto, T. Negative Capacitance for Boosting Tunnel FET performance. IEEE Trans. Nanotechnol. 2017, 16, 253–258. [Google Scholar] [CrossRef]
  14. Liu, C.; Chen, P.G.; Xie, M.J.; Liu, S.N.; Lee, J.W.; Huang, S.J.; Liu, S.; Chen, Y.S.; Lee, H.Y.; Liao, M.H.; et al. Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack. Jpn. J. Appl. Phys. 2016, 55, 04EB08. [Google Scholar] [CrossRef]
  15. Zhao, Y.; Liang, Z.; Huang, Q.; Wang, H.; Peng, Y.; Han, G.; Huang, R. Experimental Study on the Transient Response of Negative Capacitance Tunnel FET. In Proceedings of the 2019 Electron Devices Technology and Manufacturing Conference (EDTM), Singapore, 12–15 March 2019; pp. 88–90. [Google Scholar] [CrossRef]
  16. Hu, V.P.; Lin, H.; Lin, Y.; Hu, C. Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET). IEEE Electron Device Lett. 2020, 67, 2593–2599. [Google Scholar] [CrossRef]
  17. Saeidi, A.; Jazaeri, F.; Stolichnov, I.; Luong, G.V.; Zhao, Q.T.; Mantl, S.; Ionescu, A.M. Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance. Nanotechonlogy 2018, 29, 095202. [Google Scholar] [CrossRef] [PubMed] [Green Version]
  18. Kao, M.-Y.; Pahwa, G.; Dasgupta, A.; Salahuddin, S.; Hu, C. Analysis and Modeling of Polarization Gradient Effect on Negative Capacitance FET. IEEE Electron Device Lett. 2020, 67, 4521–4525. [Google Scholar] [CrossRef]
  19. Böscke, T.S.; Müller, J.; Bräuhaus, D.; Schröder, U.; Böttger, U. Ferroelectricity in hafnium oxide thin films. Appl. Phys. Lett. 2011, 99, 102903. [Google Scholar] [CrossRef]
  20. Biswas, A.; Dan, S.S.; le Royer, C.; Grabinski, W.; Ionescu, A.M. TCAD simulation of SOI TFETs and calibration of non-local band to-band tunneling model. Microelectron. Eng. 2012, 98, 334–337. [Google Scholar] [CrossRef]
  21. Chatterjee, K.; Rosner, A.J.; Salahuddin, S. Intrinsic speed limit of negative capacitance transistors. IEEE Electron Device Lett. 2017, 38, 1328–1330. [Google Scholar] [CrossRef]
  22. Synopsys Inc. Sentaurus Device User Guide; Synopsys: Mountain View, CA, USA, 2017. [Google Scholar]
  23. Landau, L.D.; Lifshitz, E.M. Quantum Mechanics; Addison-Wesley: Reading, MA, USA, 1990; p. 174. [Google Scholar]
Figure 1. (a) The cross-section view of LTFET and (b) NC-LTFET.
Figure 1. (a) The cross-section view of LTFET and (b) NC-LTFET.
Micromachines 13 00344 g001
Figure 2. (a) Negative capacitance measurement circuit, (b) comparison between simulated P–E curve with experimental results for Si: HfO2 [19].
Figure 2. (a) Negative capacitance measurement circuit, (b) comparison between simulated P–E curve with experimental results for Si: HfO2 [19].
Micromachines 13 00344 g002
Figure 3. (a) The transfer characteristic curve of NC-LTFET and LTFET, (b) the electrostatic potential of NC-LTFET and LTFET along A-B direction, (c) the band energy of NC-LTFET and LTFET along A-B direction, (d) the band-to-band generation rate of NC-LTFET and LTFET along C-D direction, (e) total current density distribution of NC-LTFET and LTFET.
Figure 3. (a) The transfer characteristic curve of NC-LTFET and LTFET, (b) the electrostatic potential of NC-LTFET and LTFET along A-B direction, (c) the band energy of NC-LTFET and LTFET along A-B direction, (d) the band-to-band generation rate of NC-LTFET and LTFET along C-D direction, (e) total current density distribution of NC-LTFET and LTFET.
Micromachines 13 00344 g003aMicromachines 13 00344 g003b
Figure 4. (a) The electric field distribution near the source region of LTFET at VGS = 0.4 V and VDS = 0.5 V, (b) the surface potential under the gate oxide along the C-D direction at VGS = 0.4 V and VDS = 0.5 V and (c) the electron band-to-band generation rate of LTFET and NC-LTFET at low gate voltage.
Figure 4. (a) The electric field distribution near the source region of LTFET at VGS = 0.4 V and VDS = 0.5 V, (b) the surface potential under the gate oxide along the C-D direction at VGS = 0.4 V and VDS = 0.5 V and (c) the electron band-to-band generation rate of LTFET and NC-LTFET at low gate voltage.
Micromachines 13 00344 g004
Figure 5. (a) The surface potential under the LTFET’s gate oxide along the C-D direction, the gate potential of LTFET and the voltage across gate oxide layer of LTFET are also considered, (b) polarization distribution of NC-LTFET at VGS = 0.4 V and VDS = 0.5 V and (c) the voltage across the ferroelectric gate oxide layer along the C-D direction.
Figure 5. (a) The surface potential under the LTFET’s gate oxide along the C-D direction, the gate potential of LTFET and the voltage across gate oxide layer of LTFET are also considered, (b) polarization distribution of NC-LTFET at VGS = 0.4 V and VDS = 0.5 V and (c) the voltage across the ferroelectric gate oxide layer along the C-D direction.
Micromachines 13 00344 g005
Figure 6. (a) The transfer characteristic curves under different g values and (b) the influence of g on SS.
Figure 6. (a) The transfer characteristic curves under different g values and (b) the influence of g on SS.
Micromachines 13 00344 g006
Figure 7. (a) Ferroelectric polarization of NC-LTFET along C-D direction at VGS = 0.25 V, (b) the electrostatic potential of NC-LTFET along C-D direction, (c) the conduction band energy of NC-LTFET along C-D direction and (d) the tunneling position of NC-LTFET with different g values at VGS = 0.25 V and VDS = 0.5 V.
Figure 7. (a) Ferroelectric polarization of NC-LTFET along C-D direction at VGS = 0.25 V, (b) the electrostatic potential of NC-LTFET along C-D direction, (c) the conduction band energy of NC-LTFET along C-D direction and (d) the tunneling position of NC-LTFET with different g values at VGS = 0.25 V and VDS = 0.5 V.
Micromachines 13 00344 g007aMicromachines 13 00344 g007b
Table 1. Device parameters of LTFET and NC-LTFET.
Table 1. Device parameters of LTFET and NC-LTFET.
LTFETNC-LTFET
Gate length (Lg)40 nm40 nm
Source height (HS)40 nm40 nm
Drain height (HD)20 nm20 nm
Gate oxide thickness (TOX)2 nm2 nm
N+ pocket thickness (Tp)5 nm5 nm
Buried oxide thickness (HB)80 nm80 nm
Source doping (NAS)1020 cm−31020 cm−3
Drain doping (NDD)1018 cm−31018 cm−3
Channel doping (NAC)1015 cm−31015 cm−3
Pocket doping (NDP)5 × 1018 cm−35 × 1018 cm−3
Coercive field (Ec) 1 MV/cm
Remnant polarization (Pr) 11.2   μ C / cm 2
Gate   oxide   dielectric   constant   ( ε r ) 2226
Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Share and Cite

MDPI and ACS Style

Zhang, H.; Chen, S.; Liu, H.; Wang, S.; Wang, D.; Fan, X.; Chong, C.; Yin, C.; Gao, T. Polarization Gradient Effect of Negative Capacitance LTFET. Micromachines 2022, 13, 344. https://doi.org/10.3390/mi13030344

AMA Style

Zhang H, Chen S, Liu H, Wang S, Wang D, Fan X, Chong C, Yin C, Gao T. Polarization Gradient Effect of Negative Capacitance LTFET. Micromachines. 2022; 13(3):344. https://doi.org/10.3390/mi13030344

Chicago/Turabian Style

Zhang, Hao, Shupeng Chen, Hongxia Liu, Shulong Wang, Dong Wang, Xiaoyang Fan, Chen Chong, Chenyu Yin, and Tianzhi Gao. 2022. "Polarization Gradient Effect of Negative Capacitance LTFET" Micromachines 13, no. 3: 344. https://doi.org/10.3390/mi13030344

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Metrics

Back to TopTop