# Compensating Circuit to Reduce the Impact of Wire Resistance in a Memristor Crossbar-Based Perceptron Neural Network

## Abstract

**:**

## 1. Introduction

## 2. Materials and Methods

_{IN,j}is the input voltage applied to the jth row. V

_{C,k}is the column-line voltage on the kth column. The column line, V

_{C,F}, is added in Figure 1 instead of using another memristor array [21]. The column line, V

_{C,F}, is connected to the inputs, from V

_{IN,1}to V

_{IN,m}. In Figure 1, V

_{C,F}enters G

_{F}that constitutes an inverting OP amp with the negative feedback resistor, R

_{F1}. The output voltage of G

_{F}is V

_{F}that is connected to all the column lines from V

_{C,1}to V

_{C,n}via R

_{F2}, as shown in Figure 1. By applying Kirchhoff current law to the column line, V

_{C,F}, we can calculate V

_{F}and V

_{O,k}with Equations (1) and (2).

_{F1}= R

_{F2}and combining Equation (1) with Equation (2), the following Equation (3) can be obtained [21].

_{j}

_{,k}, we can rewrite Equation (3) with Equation (4).

_{j,k}is the memristance value of the crossing point between the jth row and kth column. R

_{B}is a constant. The synaptic weight, w

_{j,k}, can be decided to be either negative or positive by adjusting the memristance, M

_{j,k}. The output of the perceptron neuron is decided by a threshold function which produces 0 or 1. By adding the comparator to the output voltage, V

_{O,k}, we can decide if the neuron’s output of the kth column, OUT

_{k}, should be activated or not.

_{b1}, V

_{b2}as the voltages of node b

_{1}, b

_{2}, which are on the first column. Generally, V

_{bj}is the voltage of node b

_{j}on the first column. Similarly, V

_{kj}is the voltage of node k

_{j}, which is on the jth column. Applying Kirchhoff current law for all nodes in Figure 2a, V

_{F}and V

_{O,k}can be estimated as follows:

_{F1}= R

_{F2}, Equation (7) can be simplified as follow:

_{j,k}is the memristance of the crossing point between the jth row and the kth column. V

_{bj}and V

_{kj}are the voltage at nodes b

_{j}and k

_{j}of the first column and the kth column, respectively, as shown in Figure 2a. M

_{j,k}is calculated using Equation (4). It is possible to infer that the variation of voltage presented in Equation (9) can be very small because there are a negative term and a positive term in the right side of Equation (9).

_{j(k)}as the amount of voltage drop on wire resistance, which is on the jth row and between the (k − 1)th and kth column, the voltage applied to the jth row of the kth column is calculated as Equation (10).

_{IN,j(k)}is the voltage applied to the jth row of the kth column. The column-line voltage on the kth column, V

_{O,k}, can be calculated using Equation (11).

_{k}, of the kth column as follows.

_{IN,j(k)}by using Equation (10), we obtain ∆V

_{k}as presented in Equation (13).

_{s,2}to G

_{s,26}are inserted into the circuit. The gain of these amplifiers is 1, so they work as the subtractors. The output voltages from V

_{O,1}to V

_{O,n}are the neuron’s output of columns from Col

_{1}to Col

_{n}. V

_{O,1}enter the comparator C

_{1}to decide if the neuron’s output of column Col

_{1}should be activated or not. V

_{O,2}and V

_{O,1}go into G

_{s,2}that produces V

_{Os,2}. V

_{Os,2}enters the comparator C

_{2}to decide if the neuron’s output of column Col

_{2}should be activated or not. In general, the output voltage of the column Col

_{k}

_{−1}and the column Col

_{k}enter the subtractor G

_{s,k}for generating the neuron’s output, V

_{Os,k}, of the column Col

_{k}. Using superposition theorem, V

_{Os,k}can be calculated with the difference of V

_{O,k − 1}and V

_{O,k}.

_{3}= R

_{4}= R

_{5}= R

_{6}, we can obtain:

## 3. Results

_{B}to generate the negative voltage as mentioned in the previous section. The remaining 26 columns are for recognition of 26 characters from “A” to “Z”. The 64 input voltages obtained from 64 pixels are applied to the inputs of 64 rows.

_{3}/Nb-doped SrTiO

_{3}stacked layer [28]. The black line in Figure 5b represents the behavior model of the memristor used in this paper. This model can well describe various memristive behaviors that come from different kinds of memristors [29]. The circuit simulation is performed using the SPECTRE circuit simulation provided by Cadence Design Systems Inc. Memristors are modeled using Verilog-A and the CMOS technology is given by SAMSUNG 0.13 mm process technology [29,30]. The Verilog-A model parameters are presented in [28]. The wire resistance between two adjacent junctions is set to be 2.5 Ω for a 4F

^{2}cross-point structure [19,31]. Figure 6a shows the neuron’s output of the 25th column, which is trained to be activated when character “Y” is applied to the input. Ideally, V

_{O,25}is close to 1V for character “Y”, and close to 0V for others. However, the output voltage of the 25th column, V

_{O,25}, is shifted up because of wire resistance, as reasoned in the previous section. Similarly, in Figure 6b, the neuron’s output of the 26th column is shifted up as a result of the voltage drop along wire resistance. It can be realized that if we compare the column’s output voltage, V

_{O,26}, with the reference voltage, V

_{REF}, the neuron’s output of the 26th column can be activated for several input characters, which consequently degrades the recognition rate. The output voltage of the 25th column and the 26th column are put into a subtractor circuit to produce the neuron’s output voltage of the 26th column, V

_{Os,26}. By doing this, the voltage variation is mitigated significantly, as demonstrated in Figure 6c. When the character “Y” is applied to the inputs, V

_{Os,26}is negative, because V

_{O,25}is higher than V

_{O,26}. For the character “Z”, V

_{Os,26}is high, as indicated in Figure 6c. The simulation result shown in Figure 6c indicates that the neuron’s output of the 26th column is only activated for the input character “Z”, because the variation of voltage caused by wire resistance is mitigated remarkably by the subtractor circuit.

## 4. Discussion

## 5. Conclusions

## Funding

## Conflicts of Interest

## References

- Mead, C. Neuromorphic electronic systems. Proc. IEEE
**1990**, 78, 1629–1636. [Google Scholar] [CrossRef] [Green Version] - Pacheco, P.S. An Introduction to Parallel Programmin; Elsevier: Amsterdam, The Netherlands, 2011. [Google Scholar]
- Mirsa, J.; Saha, I. Artificial neural networks in hardware: A survey of two decades of progress. Neurocomputing
**2010**, 74, 239–255. [Google Scholar] - Himavathi, S.; Anitha, D.; Muthuramalingam, A. Feedforward neural network implementation in FPGA using layer multiplexing for effective resource utilization. IEEE Trans. Neural Netw.
**2007**, 18, 880–888. [Google Scholar] [CrossRef] [PubMed] - Du, Y.; Du, L.; Gu, X.; Du, J.; Wang, X.S.; Hu, B.; Jiang, M.; Chen, X.; Su, J.; Iye, S.S.; et al. An analog neural network computing engine using CMOS-compatible charge-trap-transistor (CTT). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
**2018**, 38, 1811–1819. [Google Scholar] [CrossRef] - Kawaguchia, M.; Ishiib, N.; Umeno, M. Analog neural circuit and hardware design of deep learning model. Procedia Comput. Sci.
**2015**, 60, 976–985. [Google Scholar] [CrossRef] - Wang, F.; Li, Y.X. Analog Circuit Design Automation Using Neural Network-Based Two-Level Genetic Programming. In Proceedings of the 2006 International Conference on Machine Learning and Cybernetics, Dalian, China, 13–16 August 2006. [Google Scholar]
- Shima, T.; Kimura, T.; Kamatani, Y.; Itakura, T.; Fujita, Y.; Iida, T. Neuro chips with on-chip back-propagation and/or Hebbian learning. IEEE J. Solid-State Circuits
**1992**, 27, 1868–1875. [Google Scholar] [CrossRef] - Solomon, P.M. Device innovation and material challenges at the limit of CMOS technology. Annu. Rev. Mater. Sci.
**2000**, 30, 681–697. [Google Scholar] [CrossRef] - Brđanin, T.P.; Dokić, B. Strained silicon layer in CMOS technology. Electronics
**2014**, 18, 63–69. [Google Scholar] - Kügeler, C.; Meier, M.; Rosezin, R.; Gilles, S.; Waser, R. High density 3D memory architecture based on the resistive switching effect. Solid State Electron.
**2009**, 53, 1287–1292. [Google Scholar] [CrossRef] - Chua, L.O. Memristor—The missing circuit element. IEEE Trans. Circuit Theory
**1971**, 18, 507–519. [Google Scholar] [CrossRef] - Strukov, D.B.; Sinder, G.S.; Stewart, D.R.; Williams, R.S. The missing memristor found. Nature
**2008**, 453, 80–83. [Google Scholar] [CrossRef] [PubMed] - Jo, S.H.; Chang, T.; Ebong, I.; Bhadviya, B.B.; Mazumder, P.; Lu, W. Nanoscale memristor device as synapse in neuromorphic systems. Nano Letters
**2010**, 10, 1297–1301. [Google Scholar] [CrossRef] [PubMed] - Wang, H.; Li, H.; Pino, R.E. Memristor-based synapse design and training scheme for neuromorphic computing architecture. In Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), Brisbane, Australia, 10–15 June 2012; pp. 1–5. [Google Scholar]
- Kim, H.; Sad, M.P.; Yang, C.; Roska, T.; Chua, L.O. Neural synapse weighting with a pulse-based memristor circuit. IEEE Trans. Circuit Syst.
**2012**, 59, 148–158. [Google Scholar] [CrossRef] - Adhikari, S.P.; Yang, C.; Kim, H.; Chua, L.O. Memristor bridge synapse-based neural network and its learning. IEEE Trans. Neural Netw. Learn. Syst.
**2012**, 23, 1426–1435. [Google Scholar] [CrossRef] [PubMed] - Chen, Y.C.; Li, H.; Zhang, W.; Pino, R.E. The 3-D stacking bipolar RRAM for high density. IEEE Trans. Nanotechnol.
**2012**, 11, 948–956. [Google Scholar] [CrossRef] - Liang, J.; Wong, H.S.P. Cross-point memristor array without cell selector—Device characteristics and data storage pattern dependencies. IEEE Trans. Electron. Device
**2010**, 57, 2531–2538. [Google Scholar] [CrossRef] - Hu, M.; Li, H.; Wu, Q.; Rose, G.S.; Chen, Y. Memristor crossbar based hardware realization of BSB recall function. In Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), Brisbane, Australia, 10–15 June 2012; pp. 1–7. [Google Scholar]
- Truong, S.N.; Min, K.S. New memristor-based crossbar array architecture with 50-% area reduction and 48-% power saving for matrix-vector multiplication of analog neuromorphic computing. J. Semicond. Technol. Sci.
**2014**, 14, 356–363. [Google Scholar] [CrossRef] - Soudry, D.; Castro, D.D.; Gal, A.; Kolodny, A.; Kvatinsky, S. Memristor-Based Multilayer Neural Networks with Online Gradient Descent Training. IEEE Trans. Neural Netw. Learn. Syst.
**2015**, 36, 2048–2421. [Google Scholar] [CrossRef] - Wang, L.; Shen, Y.; Yin, Q.; Zhang, G. Adaptive synchronization of memristor-based neural networks with time-varying delays. IEEE Trans. Neural Netw. Learn Syst.
**2014**, 26, 2033–2042. [Google Scholar] [CrossRef] - Linn, E.; Rosezin, R.; Kügeler, C.; Waser, R. Complementary resistive switches for passive nanocrossbar memories. Nature Mater.
**2010**, 9, 403–406. [Google Scholar] [CrossRef] - Shin, S.H.; Byeon, S.D.; Song, J.S.; Truong, S.N.; Mo, H.S.; Kim, D.J.; Min, K.S. Dynamic reference scheme with improved read voltage margin for compensating cell-position and back ground-pattern dependencies in pure memristor array. J. Semicond. Technol. Sci.
**2015**, 15, 685–694. [Google Scholar] [CrossRef] - Levisse, A.; Royer, P.; Giraud, B.; Noel, J.P.; Moreau, M.; Portal, J.M. Architecture, design and technology guidelines for crosspoint memories. In Proceedings of the 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Newport, RI, USA, 25–26 July 2017. [Google Scholar]
- Giraud, B.; Makosiej, A.; Boumchedda, R.; Gupta, N.; Levisse, A.; Vianello, E.; Noel, J.-P. Advanced memory solutions for emerging circuits and systems. In Proceedings of the 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2–6 December 2017. [Google Scholar]
- Truong, S.N.; Pham, K.V.; Yang, W.; Shin, S.; Pedrotti, K.; Min, K.S. New pulse amplitude modulation for fine tuning of memristor synapses. Mircoelectron. J.
**2016**, 55, 162–168. [Google Scholar] [CrossRef] - Yakopcic, C.; Taha, T.M.; Subramanyam, G.; Pino, R.E.; Rogers, S. A memristor device model. IEEE Electron Device Lett.
**2011**, 32, 1436–1438. [Google Scholar] [CrossRef] - Spectre® Circuit Simulator User Guide. Available online: https://www.ee.columbia.edu/~harish/uploads/2/6/9/2/26925901/spectre_reference.pdf (accessed on 1 October 2019).
- International Technology Roadmap for Semiconductors. 2007. Available online: https://www.semiconductors.org/wp-content/uploads/2018/08/2007Interconnect.pdf (accessed on 1 October 2019).
- Kim, S.; Zhou, J.; Lu, W.D. Crossbar RRAM arrays: Selector device requirements during wire operation. IEEE Trans. Electron. Devices
**2014**, 61, 2820–2826. [Google Scholar] - Schindler, G.; Steinlesberger, G.; Engelhardt, M.; Steinhögl, W. Electrical characterization of copper interconnects with end-of-roadmap feature sizes. Solid State Electron.
**2003**, 47, 1233–1236. [Google Scholar] [CrossRef] - Kohonen, T. Self-organization and Associative Memory. In Information Sciences; Springer: Berlin/Heidelberg, Germany, 1989. [Google Scholar]
- Li, C.; Belkin, D.; Li, Y.; Yan, P.; Hu, M.; Ge, N.; Jiang, H.; Montgomery, E.; Lin, P.; Wang, Z.; et al. Efficient and self-adaptive in-situ learning in multilayer memristor neural networks. Nat. Commun.
**2018**, 9, 2385. [Google Scholar] [CrossRef] - Caravelli, F.; Carbajal, J.P. Memristors for the curious outsider. Technologies
**2018**, 6, 118. [Google Scholar] [CrossRef]

**Figure 1.**The memristor-based crossbar architecture with a single memristor array and a constant-term circuit for realizing the synaptic matrix of a perceptron neural network [21].

**Figure 2.**Wire resistance between two adjacent junctions is modeled by a small-value resistor, r, connecting between two crossing points. (

**a**) Wire resistance on horizontal lines is omitted. (

**b**) Wire resistance on vertical lines is omitted.

**Figure 3.**The proposed memristor crossbar with compensating circuit for implementing a perceptron neural network. The outputs of two adjacent columns are put into a differential amplifier working as a subtractor to eliminate the output voltage variation.

**Figure 4.**The concept of the proposed circuit for compensating the output voltage variation caused by wire resistance. (

**a**) The ideal output of the 25th and 26th columns, which are trained to recognize character images of “Y” and “Z”, respectively. (

**b**) The output voltage of the 25th and 26th columns when the wire resistance is taken into account. V

_{Os,26}is the output of subtractor for the 26th column, as depicted in Figure 3.

**Figure 6.**The simulation result of the proposed memristor crossbar array depicted in Figure 4. (

**a**) The neuron’s output of the 25th column without compensating circuit. (

**b**) The neuron’s output of the 26th column without compensating circuit. (

**d**) The neuron’s output of the 26th column with compensating circuit. The wire resistance between two adjacent junctions is set to be 2.5 Ω [19,28].

**Figure 7.**The comparison of the recognition rate between the memristor crossbar without compensating circuit and the proposed memristor crossbar with compensating circuit. The wire resistance is set to be 0.5, 1.0, 1.5, 2.0, and 2.5 Ω, respectively.

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**MDPI and ACS Style**

Truong, S.N.
Compensating Circuit to Reduce the Impact of Wire Resistance in a Memristor Crossbar-Based Perceptron Neural Network. *Micromachines* **2019**, *10*, 671.
https://doi.org/10.3390/mi10100671

**AMA Style**

Truong SN.
Compensating Circuit to Reduce the Impact of Wire Resistance in a Memristor Crossbar-Based Perceptron Neural Network. *Micromachines*. 2019; 10(10):671.
https://doi.org/10.3390/mi10100671

**Chicago/Turabian Style**

Truong, Son Ngoc.
2019. "Compensating Circuit to Reduce the Impact of Wire Resistance in a Memristor Crossbar-Based Perceptron Neural Network" *Micromachines* 10, no. 10: 671.
https://doi.org/10.3390/mi10100671