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Article

Processing-in-Memory Development Strategy for AI Computing Using Main-Path and Doc2Vec Analyses

by
Euiyoung Chung
1 and
So Young Sohn
2,*
1
Memory System R&D, SK Hynix America, 3101 N 1st, San Jose, CA 95134, USA
2
Department of Industrial Engineering, Yonsei University, Shinchon-Dong 134, Seoul 03722, Republic of Korea
*
Author to whom correspondence should be addressed.
Sustainability 2023, 15(16), 12439; https://doi.org/10.3390/su151612439
Submission received: 25 June 2023 / Revised: 5 August 2023 / Accepted: 14 August 2023 / Published: 16 August 2023
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Abstract

:
Processing-in-Memory (PiM), which combines a memory device with a Processing Unit (PU) into an integrated chip, has drawn special attention in the field of Artificial Intelligence semiconductors. Currently, in the development and commercialization of PiM’s technology, there are challenges in the hegemony competition between the PU and memory device industries. In addition, there are challenges in finding strategic partnerships rather than independent development due to the complexity of technological development caused by heterogeneous chips. In this study, patent Main Path Analysis (MPA) is used to identify the majority and complementary groups between PU and memory devices for PiM. Subsequently, Document-to-Vector (Doc2Vec) and similarity-scoring analyses are used to determine the potential partners for technical cooperation required for PiM technology development for the majority group identified. According to the empirical results, PiM core technology is evolving from PU to memory device with an ‘architecture-operation-architecture’ design pattern. The ten ASIC candidates are identified for strategic partnerships with memory device suppliers. Those partnership candidates include several mobile AP firms, implying PiM’s opportunities in the field of mobile applications. It suggests that memory device suppliers should prepare for different technology strategies for PiM technology development. This study contributes to the literature and high-tech industry via the proposed quantitative technology partnership model.

1. Introduction

With the advancements in the Artificial Intelligence (AI) era, such as generative AI, a strong demand for innovation in AI semiconductor technology is increasing. Consequently, Processing-in-Memory (PiM), which is crucial in AI computing, has drawn special attention from industry and academia. PiM is an emerging semiconductor technology that combines a memory device and Processing Unit (PU) into a chip [1], supporting the heavy AI-related computational workload of the Central Processing Unit (CPU) or Graphics Processing Unit (GPU) [2]. Presently, PiM technology development faces two primary challenges.
The first challenge Is identifying the core technology of PiM, which has the combined form of memory devices for buffering data and PU for processing data. It is a critical issue because the firm’s strategy for PiM technology can vary depending on where its core technology is rooted, which subsequently will affect technology partnerships. Memory device suppliers can take advantage of the advances in PiM technology to improve system performance and expand their business into the PU domain. Conversely, PU suppliers can also use memory device technology to optimize performance and create new business. PiM should not be merely considered a convergence chip that combines two different technologies. Instead, PiM is a critical element in technology capacity and business strategy, which determine not only the strategic technology direction of a firm but also the scope of new business opportunities. The first challenge can be interpreted as an implicit competition between PU and Memory for hegemony over PiM technological standards. The technical standards in the semiconductor industry can be powerful weapons [3]. This is because technical standards enable large-scale production, IP business, and lock-in of standard technology that is advantageous to each semiconductor firm. Ref. [4] explained that the reason South Korea, which has the memory device initiative, emphasizes PiM in the AI semiconductor area is to secure hegemony in PiM technology.
The second challenge arises from the convergence required for complex technological collaboration models in PiM. The second challenge comes from the complexity inherent in the semiconductor industry. Ref. [5] explains that the semiconductor industry is a very complex industry from a supply chain perspective. Meanwhile, Ref. [6] explained that in the process of designing and manufacturing heterogeneous chips, there are complex and challenging factors related to the difficulty of combining different chips and balancing performance, power, and cost. In particular, PiM has the challenges of existing semiconductor technology and, at the same time, faces new technological challenges such as workload analysis and classification, OS and runtime support, and coherency and consistency [7]. These PiM challenges cannot be solved by a single firm alone but can only be achieved through collaboration between companies that make up the value chain. These challenges demonstrate the importance of integrated partnership strategies in AI semiconductors. PiM is composed of complex IPs, and it should be able to provide an optimized chip design for various AI applications. Furthermore, cost optimization must also be realized using mass-production infrastructure. Technological collaboration between the memory device and PU suppliers in the semiconductor industry is becoming crucial.
In order to address the aforementioned challenges regarding PiM technology development, in this paper, we first identify the evolution path of PiM technology. In this way, one can find out which technology played the main role on the evolution path of PiM: memory devices or PU. This information is applied to propose a direction for a strategic partnership between the memory device and PU suppliers. To identify the majority and complementary groups of PiM, we applied a Main Path Analysis (MPA) to the citation data of PiM patents from 1980 to 2018 [8]. Next, Doc2Vec-based similarity-scoring analysis is used to find appropriate technology partners to develop PiM technologies. This study can suggest a technology partnership framework to apply not only to PiM technology but also to various advanced technologies.
The rest of the paper is organized as follows: Section 2 reviews the prior research on PiM and MPA. Section 3 introduces the research methodology. Section 4 explains the results of our analysis, while Section 5 and Section 6 offer a discussion and conclusions.

2. Literature Review

2.1. Processing-in-Memory

A semiconductor designed to process deep learning algorithms is referred to as an AI semiconductor [9]. AI semiconductors can be defined both in broad and narrow terms. The broad one includes basic AI computation and general-purpose semiconductors used in general computing, while the narrow one refers to semiconductors optimized and exclusively used for AI algorithms, such as AI accelerators, neural network processors, neural processing units, and neural processors. In addition, AI semiconductors are typically categorized on the basis of three generations of technology. The first-generation AI semiconductors include CPUs, GPUs, and Field-Programmable Gate Arrays (FPGAs), and they are primarily used to support general computations with limited AI-related computing support. The second-generation AI semiconductors include Application-Specific Integrated Circuits (ASICs) optimized for customized AI applications. The third-generation AI semiconductor involves neuromorphics. Neuromorphics is a non-von Neumann architecture that aims for ultra-efficient processing by mimicking the neural activity of the human brain. Although the potential of neuromorphics remains high, only a few readily available fundamental technologies are available in this field.
All the current computing systems are designed with the basic architecture of von Neumann’s design, developed in 1945. Its key challenge is a phenomenon called ‘the von Neumann bottleneck’, also known as ‘memory bottleneck’, which refers to a performance gap between the memory devices and PUs due to the performance limit of the memory device. Consequently, the performance of the entire computing system deteriorates due to the bottleneck issue. AI computing requires significantly massive and rapid workload processing, and PiM is increasingly being recognized as an attractive solution to resolve the bottleneck issue. PiM is an innovative technology that overcomes the von Neumann bottleneck by stacking either a PU on top of a memory device or a memory device on top of a PU, thereby physically integrating the two and minimizing data movements. Ref. [10] explained how PiM is formed (Figure 1). Figure 1a shows a traditional computing architecture without an AI accelerator, while Figure 1b shows a PiM-based computing architecture.
Ref. [11] chronicles the evolution of PiM technology since its inception in the 1970s. This study makes evident that early PiM architectures closely positioned the memory device and PU as separate form factors. Later, with the advent of three-dimensional (3D) die-stacking technology, a processing-near-memory type, which integrates a memory device and PU into one, emerged. Despite the promising potential of the PiM, particularly due to the recent advances in adjacent technologies such as 3D-integrated package technology, its successful commercialization remains elusive, although it has been theoretically possible for some time. Specifically, high technological and cost barriers related to the physical integration of convergence technologies, changing computing hierarchy, and systematic compatibility issues are significant hurdles that must be overcome. In other words, there are technical absences in the integration of memory devices and PUs on the same die, physical stability between memory device and PU integration, interface technology between memory devices and PUs, and appropriate software architecture [12].
Meanwhile, due to the technological nature of PiM, which is an advanced technology for combining heterogeneous integrated chips with different functions and physical structures, it is very difficult to develop PiM at a single firm. The core of PiM technology development is the technological partnership between firms that have respective technologies for memory devices and PU. Technological partnership defines a voluntary agreement such as jointly developing, exchanging, and sharing products, technologies, and services [13]. In relation to technological partnership, many studies have been conducted on defining and discovering technological partners, types of cooperation, and the effect of performance. Ref. [14] pointed out that empirical studies on the relationship between alliance selection and performance are very limited, arguing that the cause lies in the absence of appropriate partner selection criteria. Ref. [15] explained that cooperation with a partner operating an existing business can have a more positive effect on technological innovation than with a newly established partner. Ref. [16] presented an evaluation index centered on research capabilities, commercialization performance, and IPs in studies on strategic technological partner selection. Ref. [17] suggested key success factors that influence partner selection, along with task-related criteria for partner selection. Ref. [18] argued that the importance of partner selection criteria may change over time, reflecting the dynamics of capabilities. Ref. [19] explained that the selection of a technological partner should be based on the partner firm’s competency, expertise, and cultural suitability with the host firm.
Although there are various studies on technological partnership strategies, there are limited approaches using systematic or quantitative analysis of actual industries and firms for technological partnerships. Ref. [13] pointed out that there are problems with vagueness in the assessment of open innovation, including partner selection, and suggested input variables for the open innovation level of the firm such as external search breadth, external R&D, and open innovation culture. Actually, many firms approach technological partnerships based on the needs of top management in terms of market dominance or brand power, individual networking, and mutual business models. The reason why the probability of success is limited for numerous technological partnerships, such as joint development or joint ventures within the industry, is that the technological factors have not been systematically analyzed. Many firms review some of the technology factors, but there is a lack of systematic and quantitative aspects about whether the technology is in line with the core technical trend and whether there are similar or alternative technologies.

2.2. Main Path Analysis

MPA is a mathematical analysis method that identifies the main path of a technology’s trajectory based on the relationships between citations to patents or research papers. It is used to track the flow of scientific and technological knowledge [8]. First introduced by [20], MPA was applied to the field of information science by [21]. MPA finds the paths that connect different nodes. Source nodes have outward connections but no inward connections. The opposite of source nodes are sink nodes, which have inward connections but no outward connections [22]. MPA calculates the traversal weights of all arcs and paths between nodes. The arc with the greatest weight is the main path. Each combination of source and sink nodes is analyzed. Between each pair, there are a certain number of nodes. The traversal weight is the proportion of a particular node that passes through a given node between a pair of sources and sink nodes [23]. There are various MPA algorithms, but the most common are the Search Path Link Count (SPLC), Search Path Node Pair (SPNP), and Search Path Count (SPC) algorithms [24]. The main path can be selected through local search, global search, or key-route search. A local search was proposed by [20]. This method determines which path has the highest count in the next link selection. Global search determines which link has the highest accumulated count of all paths between the beginning and end nodes. Key-route search is designed to supplement local and global searches because they leave out important paths.
MPA has been used to identify the trajectories of particular technologies, mainly to identify R&D paths and research trends and make predictions for the future directions of technological developments. Ref. [25] described the evolution of Dye-Sensitized Solar Cells (DSSC) using MPA. They conducted text mining on DSSC patent data to extract research trends and topics. They found that technologies involving DSSCs were being used in the development of several technologies, including devices, components, and materials. Ref. [26] used MPA to show how data quality and data quality management knowledge were spread. They conducted MPA on G-Index and H-Index data and found that data quality knowledge was being applied to website design, decision support, assessments, and applications. Ref. [27] used MPA to investigate trends in cloud computing research. They analyzed data from information systems, electronic commerce, and management journals and conferences and found that cloud computing had evolved through the incubation and exploration stages and was now in the burgeoning stage. Ref. [28] used MPA to show how New Energy Vehicle (NEV) technologies were evolving. They analyzed data from research papers and found that NEV research moved from market penetration to subsidies and then to charging stations.
Despite the importance of AI semiconductors in the AI era, there has been no MPA study on AI semiconductors, including PiM. The reason is that the need for AI-purpose high-performance computing has started recently, and it is a more recent issue that the semiconductor and computing industries have begun to pay attention to PiM from the perspectives of development, manufacturing, business, and market. Therefore, a study on the technology strategy for PiM was inevitably absent. In this study, the technology trajectory of the PiM, a convergence technology of memory devices and PU, is identified using the MPA perspective on the technology strategy of the PiM.

3. Methodology

3.1. Research Design

This study aims to identify the PiM core technologies and suggest complementary technology partnerships for those organizations that hold these core technologies. The proposed framework consists of three stages, as shown in Figure 2: First, we use the MPA with patent citation data to identify if the majority of PiM core technologies belong to memory devices or PUs. Next, we use Document-to-Vector (Doc2Vec) to identify technological attributes of related claims in patent documents on the main path and entire patents of complementary groups. Lastly, we use a similarity-scoring analysis to evaluate the priority among the technology partnership candidates between the major group and the complementary group.

3.2. Trajectory Analysis

MPA is primarily used to trace the path of scientific and technological knowledge flow in various fields. MPA has been used to identify the trajectories of particular technologies, mainly to identify R&D paths and research trends and make predictions for the future directions of technological developments. As a research methodology that analyzes technological evolution or technological trajectory, qualitative research such as interviews and case studies is mainly used [29,30,31]. MPA is highly valuable in that it can quantitatively measure the path of technological development.
We apply MPA to identify the main path of a PiM core technology trajectory. First, we use patent citation analysis for MPA. There are three main methods of analyzing citations in patents: patent citation analysis, patent co-classification analysis, and co-word analysis. Patent citation analysis shows how frequently a given patent is cited by later patents. Patent co-classification analysis shows how closely related technologies are based on the similarity of their classification codes. Co-word analysis extracts keywords from patents and determines whether they are used in different fields to determine whether the patent is for a convergence technology. These methods are effective for small citation networks but not for large citation networks. Second, traversal counts are obtained for each link in a citation network using the weight calculation method of Search Path Count (SPC). SPC is defined as the total number of links that can be linked, starting from all the sources to all the sinks. Ref. [32] observed that the performance of SPC was the best, although other approaches such as Search Path Link Count (SPLC) and Search Path Node Pair (SPNP) produced nearly identical results to SPC. The third step searches for the main paths by linking the significant links according to the size of the traversal counts.
Local search, key-route search, and global search are common techniques used to obtain a main path. The local search used in this study is based on the ‘priority first’ algorithm [20]. When connecting each source node and sink node, the highest link is selected to form the main path. In other words, at each technological inflection point, local search can select the next most robust technological evolution path. Unlike local search, which is based on the priority first algorithm, global search selects the path with the largest sum of all links from the beginning to the end of the main path. The global search can identify the mainstream of the entire technology, but there is a limit to the interpretation of each technological inflection point. Key-route search was developed to overcome the limitations of local search and global search, which present unified routes. Since key-route search considers forward and backward link values together, it is possible to check the spread of various technology routes.
In this study, MPA was used to distinguish the majority and complementary groups between the PU and memory devices that constituted the PiM technology. In order to identify the majority and complementary groups, the identification of each technology inflection point is required, and the technical properties of each technology must be analyzed. In addition, since this study focuses on the ‘evolution of PiM core technology’ rather than the ‘spread of PiM technology’, local search is more suitable than global search and key-route search. Of course, in this study, three algorithms were used for verification, and the same main path could be derived. These results are from a small dataset and can be recognized as a limitation of this study.
In this study, a local search that strongly traces the core flow of technological evolution was adopted based on SPC. As a result of MPA, one can identify if the majority of the PiM core technologies are memory devices or PUs, along with their ownership.

3.3. Partnership Analysis

As the uncertainty of R&D and market success increases, many R&D based companies are using technological partnerships to supplement scarce R&D resources, improve R&D efficiency, and hedge risk [33]. Technological partnership is an important corporate strategy that has been continuously increasing since the 1980s. A technological partnership refers to the role of aggregating different competencies through networks between organizations based on internal R&D capabilities [34]. Furthermore, technological partnership defines a voluntary agreement such as jointly developing, exchanging, and sharing products, technologies, and services.
Although there are various studies [14,15,16,17,18,19] on technological partnership strategies, actual industries and companies use a limited approach to technological partnerships. Many companies approach technological partnerships based on the needs of top management in terms of market dominance or brand power, individual networking, and mutual business models. The reason why the probability of success is limited despite numerous technological partnerships, such as joint development or joint ventures within the industry, is that the technological factors have not been systematically analyzed. Many companies review some of the technology factors, but there is a lack of systematic and quantitative analysis of whether the technology is in line with the technical trend, penetrates the core of the trend, and whether there are similar or alternative technologies.
In this study, we conduct a Doc2Vec and similarity-scoring analysis based on the results of the MPA to identify complementary technology partnerships for PiM technology development. Doc2Vec was used to discover potential partnerships. Doc2Vec, TF-IDF, and LDA are used to classify and analyze the meaning of documents. TF-IDF expresses words as vectors according to their frequency. LDA determines a document’s topic by comparing the frequency of certain words in the document against a pre-determined frequency list of words for various topics. Doc2Vec has been successfully used to classify documents in various fields. Doc2Vec is more accurate than other document classification methods in various areas, such as sentiment classification, news categorization, and forum question duplication [24]. Although the performance results for similar techniques are different for each study, some studies have demonstrated that Doc2Vec can show high performance because it can understand not only the frequency but also the meaning and context of words [35]. Therefore, the use of the Doc2Vec technique is meaningful because it is necessary to understand the PiM technology viewpoint, not the PU and memory device viewpoint, for the PiM-related patent documents analyzed in this study. We define ‘technological similarity’ as a ‘suitability of technology partnership’ that possesses similar PiM core technologies between memory device and PU firms. In this study, the claims on the patent are set as documents for similarity-scoring analysis via Doc2Vec analysis with the Distributed Memory (DM) algorithm. Finally, to propose technology partnerships for PiM technology development between memory device and PU firms, the similarity-scoring analysis is derived by combining the technical similarity and patent recency weights of each firm in the majority and complementary positions. To analyze similarity-scoring, we analyze the cosine similarity to measure the technological similarity between memory device and PU firms for PiM technology development. Furthermore, we applied a recency weight to each patent filing date to reflect the latest PiM technologies held by memory device and PU firms. We assign a recency weight of 0.5 to patents filed after 2018, 0.3 to patents filed after 2013, and 0.2 to all other patents. We multiply the cosine similarity values and the recency weights and then sum them to derive a similarity score for each firm. Finally, we prioritize the top 10 partnerships based on similarity scores between the majority group and complementary groups to develop PiM technologies.
In sum, this study analyzes the evolution path of PiM core technology through MPA- and Doc2Vec-based similarity-scoring analysis to shed light on a technology partnership decision-making framework to secure PiM core technology. That is, the MPA provides the answers to “What is the PiM core technology?” and “Who owns it?”. Utilizing the results of MPA- and Doc2Vec-based similarity-scoring analysis can provide the answer to “Who is the potential partner that can complement the majority group to develop PiM core technology?”.

4. Results

PiM technologies have rapidly developed since their concept first emerged in the 1970s. Recently, its development speed has increased, particularly owing to the high-performance computing requirements necessary for AI processing.
The patent data from the United States Patent and Trademark Office (USPTO) was used for the MPA and Doc2Vec-based similarity-scoring analysis for this study. For MPA, 1034 sets of broadly PiM-related patents filed at the USPTO from 1980 to 2018 were first extracted based on the discussion with technical experts and patent specialists on PiM. Table A1 presents the PiM-related patent search terms. Most of those patents consist of technologies related to interface software or the technical performance estimation of computing architecture. However, in this study, we only focus on the pure PiM hardware-based technology at the integrated chipset level between the memory device and PU. Finally, we utilized 173 sets of PiM patent data focused on our research purposes.
As depicted in Figure 3, the MPA revealed 11 core patents and 13 derivative patents related to PiM from the mid-1980s to 2017. The MPA of PiM revealed three key findings.
First, one core patent (US7167890) and six derivative patents (US4811269, US6014684, US6286024, US6704762, US6523055, and US6718465) were filed between the mid-1980s and early 2000s. The six derivative patents were converged into the core patent (US7167890) in 2003, marking the beginning of the first main path for PiM.
Secondly, the MPA of PiM observed that PiM R&D had been primarily driven by PU suppliers from the mid-1980s to 2003. All of the patent applicants in this period, such as Hitachi (US4811269), Intel (US6014684), Toshiba (US6286024), NEC (US6704762), and LSI (US6523055), owned PU technology portfolios. Additionally, it was confirmed that the applicants of the patents from the Research Foundation of the State University of New York (RF SUNY) (US6718465) and RF SUNY and the University of Rochester (UR) (US7167890) were also involved in the PU technology research. However, since 2009, PiM R&D has been increasingly driven by memory device suppliers. Additionally, from the MPA of this study, it was found that a memory device supplier, Micron Technology, has owned all the core patents related to PiM since 2009. Therefore, it can be interpreted that while PiM core technology started with PUs, the majority of PiM core technology in the last 20 years has been driven by memory devices.
The third key takeaway is that PiM has been developed in the order of architecture-operation-architecture. Typically, semiconductor development begins with architecture design and moves to operation design. This study found that the PiM architecture design patents had been filed between the 1980s and 2009 (US9477636), followed by patents on operation design from 2013 up to the point of a core patent (US9898253) filed in 2016. Subsequently, starting with a core patent (US9767864) in 2016, architecture design patents resumed. Table 1 summarizes the analytical results of the core technology of PiM applicants and attributes. In Table 1, Level 1 represents the domain of design, such as architecture and operation. Level 2 represents the detailed functions that comprise Level 1.
As suggested in the second key finding, PiM core technologies are currently based on memory devices such as those manufactured by Micron Technology from 2009 to 2017. Therefore, memory device suppliers should be the majority group or lead technological partner, with PU suppliers playing a complementary role in developing the PiM technology. Accordingly, we considered PU suppliers as complementary partners for memory device suppliers led technology partnerships required for PiM development. In this study, PU’s patents were set to Application-Specific Integrated Circuits (ASICs), which is one of the AI semiconductors. ASICs are expected to become the dominant type of AI semiconductor for training as well as inference usage. The PiM is also suitable for processing mid-low workloads, similar to ASICs rather than training-focused GPUs. Therefore, it makes sense that memory device suppliers choose ASIC suppliers as PiM’s technical partners. Therefore, we analyzed Doc2Vec and similarity-scoring analysis between patent claims on the main path and PiM-related ASICs. A total of 470 sets of PiM-related ASIC patents filed at the USPTO before 2018 were identified by AI semiconductor experts and patent specialists. Table A2 presents the ASIC-related patent search terms. Additionally, another 251 sets of PiM-related patents owned by ASIC firms were made available by firm information providers, CB Insight and PitchBook, for the analysis. Finally, a total of 721 ASIC-related patents were analyzed in this study.
We analyzed Doc2Vec with patent claims on 24 PiM core and derivative technologies, along with the 721 PiM-related ASIC patents. Hyperparameters for the Doc2Vec analysis were set as follows: the learning rate as 0.05, the dimension of the vector as 3000, and the window size as 5. With Doc2Vec embedding, the cosine similarity scores between 24 core and derivative patent documents of the PiM main path and 721 ASIC-related patents were analyzed. As a result, a total of 17,304 cosine similarity scores for ASIC patents owned by 61 firms were organized. For each organization, a recency weighted similarity score is summed up to determine the top 10 ASIC suppliers as a list of partnership candidates for memory device suppliers (Table 2).
Based on the results of similar-scoring analysis, large firms such as Intel, Samsung Electronics, Apple, and Qualcomm and six startups (i.e., Cambricon Technologies, Gyrfalcon Technology, Graphcore, Achronix Semiconductor, GEO Semiconductor, and Kneron) might be the best candidates for memory device suppliers as a majority group of the PiM core technology. To validate the results, we conducted additional simulations by changing the weight. With the adjusted weights (80%, 50%, and 10%) compared to the base weights (50%, 30%, and 20%), there were no changes in the top six suppliers. However, with the adjusted weighting, there were some changes in the ranking. Qualcomm ranks seventh, Kneron ranks eighth, GEO Semiconductor ranks ninth, and Achronix Semiconductor ranks tenth. It means that Qualcomm and Kneron have more up-to-date patents since 2018 than the other two. As a result, we confirmed that the top rankings of the priority group were still valid, although there were some changes in the bottom ranking.

5. Discussion

This study began with the following research questions: “What are the main trajectories of the core technologies of PiM?”, “What is the majority group and complementary group on PiM technologies?”, and “Which partner is the right technological partnership candidate to develop PiM technologies?” Our discussion is based on the MPA and Doc2Vec, and a similarity-scoring analysis of related patents follows.
First, it was observed that the early stage of PiM development from the mid-1980s to 2009 was mainly driven by PU suppliers. After 2009, PiM technology development was mainly led by a memory device supplier such as Micron Technology. Micron Technology is a US-based firm with the third-largest share of the global memory device market in 2022. Since the core patents that involved PiM were mainly filed by PU suppliers until 2009 and then by memory device suppliers thereafter, the primary innovations in PiM have mainly been attributed to memory device suppliers for most of the 2010s. The key role of memory device suppliers for PiM resulted in new architecture innovations, such as 3D-stacked memory devices, thereby strengthening PiM technology development in recent years [36].
Second, the semiconductor design process generally first involves building a structural basis through architecture design, followed by operation design for optimizing performance within the architecture. The R&D of PiM is also performed in accordance with the same process. The core patents until 2009 show that they mainly focused on 2D architecture design in which a memory device and PU were aligned in a flat form factor. Subsequently, the core patents filed up to 2016 indicate that their patents were mainly focused on a 2D operation design. Additionally, from a core patent (US9767864) in 2016, a transition occurred back to architecture design patents, and this transition is attributed to an innovation in the memory device architecture that shifted from the 2D flat structure to the 3D stacked structure. Ref. [37] explained that applying a 3D-stacked technology called Through-Silicon Vias (TSVs) to memory devices eased their integration with PUs, which consequently served as a basis for PiM innovation. In 2013, SK Hynix, the second-ranked memory device supplier worldwide, developed the first-ever 3D stack-based memory device, called ‘High Bandwidth Memory (HBM)’, to which the TSV technology was applied. The firm began to mass produce HBM in 2015. Micron Technology also developed a technology similar to HBM called the ‘Hybrid Memory Cube (HMC)’.
Third, the analysis identified a large PU firm (i.e., Intel) and a startup (i.e., Cambricon Technologies) as potential partners for enabling PiM technology development for memory device suppliers. Intel is the largest semiconductor manufacturer in the world and possesses an impressive technology portfolio in the field of PUs, such as CPUs, GPUs, FPGAs, and ASICs. It has also acquired ASIC startups, including Movidius, Nervana, and Harbana, further solidifying its strong position with an up-to-date ASIC-related patent portfolio. In particular, Intel was historically the first firm to develop DRAM, a kind of memory device, in the world. Since then, due to a strategic choice, Intel switched to a processor unit such as a CPU, and in 2018, Intel also had a history of re-entering the memory device market through a technology called 3D Xpoint. In other words, Intel is the only firm that has experience in the technology development and business of both PU and memory devices and has a wealth of IPs as well. The other potential partner, Cambricon Technologies, is a highly promising AI semiconductor startup with a Chinese market valuation of $2.5 billion, one of the highest values ever for a startup in the country, as of 2018. Other potential partners for PiM technology development, as identified in this study, include Samsung Electronics, Apple, and Qualcomm among the large firms, and Gyrfalcon Technology, Graphcore, Achronix Semiconductor, GEO Semiconductor, and Kneron among the ASIC startups. Meanwhile, technology partnerships between memory device and PU suppliers in support of PiM technology development can be analyzed from a bargaining power perspective. Presently, only three firms account for approximately 90% of the memory device supplier market: Samsung Electronics, SK Hynix, and Micron Technology. However, the PU landscape is significantly more diverse, with many firms occupying dissimilar shares of the market. This asymmetry, thus, provides memory device suppliers (particularly Samsung Electronics, SK Hynix, and Micron Technology) significant leverage in forming partnership negotiations with many PU firms.
Fourth, among the top 10 PU candidates identified for PiM technology partnerships, four candidates have a technology portfolio related to mobile Application Processors (APs). Cambricon Technologies (second ranked on the partnership list of this study) provided its AI-based ASIC technology to Huawei’s mobile AP (Kirin Series), while Samsung Electronics (Exynos Series), Apple (Ax Series), and Qualcomm (Snapdragon Series) have mobile AP portfolios both in-house and through outsourcing development services. Firms with such portfolios are potential partners for PiM technology development because the commercialization of AI semiconductors has been focused on mobile technology in recent years, particularly with regard to ‘on-device AI’. Notably, on-device AI involves directly integrating AI functions into individual mobile devices rather than making those devices dependent on cloud-based infrastructures. Samsung Electronics, Apple, and Qualcomm, with their expansive AP portfolios, have heavily invested in the R&D of on-device AI, thereby embedding APs with ASIC chips to create NPUs, deep learning processing units, and brain processing units. In other words, PiM can provide opportunities for technological development in on-device AI-based mobile applications.
The final and main takeaway is that memory device suppliers should pursue different strategies based on different technological resources. Samsung Electronics, the biggest memory device supplier in the world, can develop the PiM technology entirely on its own resources without requiring outside partnerships. Samsung Electronics not only has memory devices and mobile AP technological capabilities, but it also boasts ASIC capabilities that rank third in the similarity-scoring analysis of this study. The firm has significantly diverse technical portfolios that contain all the capabilities required for PiM technology development. Micron Technology mainly focuses on memory device R&D and business; however, it shows a high degree of concentration in R&D in the PU field. Micron Technology owns one of the AI semiconductors, an FPGA, and an FPGA-based development platform as well. Micron Technology has also acquired firms, including FWDNXT (a machine-learning engine) and Virtensys (a system virtualization vendor), to possess the capabilities for AI and computing systems. Therefore, in terms of R&D, Micron Technology can be interpreted as a firm equipped both with memory device and PU capabilities, which, thus, provides a rationale to acquire PiM core patents. The fact that Micron Technology spun off Natural Intelligence Semiconductor, which is a kind of PiM corporate and the only memory device supplier, proves that Micron Technology has capabilities in PiM-related technologies. SK Hynix is not well-positioned to develop the core technology of PiM and does not have PiM patents or PU technology portfolios. Thus, SK Hynix should consider a technology partnership with PU suppliers more strongly than Samsung Electronics and Micron Technology for PiM technology development.

6. Conclusions

In this study, we identified a technology development partnership strategy for the PiM technology, which is an emerging AI semiconductor that is drawing significant attention from the industry and academia. We investigated the core technology on which PiM is based. Additionally, we shed light on the technology partnership required to develop the PiM technology.
MPA was used to perform an empirical analysis of the core technology of PiM. It was observed that memory device suppliers have made efforts to focus on the core technology of PiM since 2009. Therefore, we suggest that a memory device supplier that possesses these core technologies form a technology partnership with a PU supplier. ASIC suppliers were especially considered as possible partner candidates for PiM technology development with memory device suppliers. Furthermore, it was revealed that the PiM technology was evolving in the order ‘architecture-operation-architecture’ and that the starting point of this evolution was the transition of memory devices from 2D flat architecture to 3D stacked architecture. A Doc2Vec-based similarity-scoring analysis identified the top 10 ASIC-related technology partnership candidates perspectives on memory device suppliers. We also confirmed that PiM technology partnership candidates include several mobile AP firms that are leading on-device AI, and PiM has opportunities in the field of mobile applications. In addition, we explained that memory device suppliers should pursue different technology strategies for PiM technology development.
This study contributed to the literature and practice from the following perspectives: First, it was the first proposal for technology trajectory analysis and strategic technology partnerships for AI semiconductors, especially PiM. Second, this study suggested a ‘Quantitative Partnership Model’ by combining MPA, Doc2Vec, and Similarity-scoring analysis. Third, this study provided strategic interpretations using field data from the firm. The technology partnership selection approach proposed for PiM technology can be applied to many other technologies or high-tech industries. Therefore, this approach can help businesses save time to market when identifying appropriate R&D partners for their technical collaboration.
However, this study has the following limitations: First, we could only utilize a limited number of patents obtained from the USPTO. For example, an analysis using not only SPC but also SPLC and SPNP was conducted, and all approaches showed the same path results. We interpreted these results due to the limited number of samples. As the sample size increases and the number of linked cases increases, various main paths can be formed. However, in this study, the number of newly formed main paths was limited due to the small number of samples. Second, the technology partnership proposal considered was limited only to ASIC suppliers among all types of PU suppliers. Furthermore, R&D partnerships typically prefer commercial confidentiality over patents [38]. In the semiconductor industry, it is common practice for firms to keep their developed technologies confidential. This is due to the reverse-engineering-related risks involved in patent disclosure; thus, we might not have covered all the technology of the semiconductor suppliers discussed in this study. Third, this study lacked suggestions for specific partnership strategies between memory devices and PUs. Fourth, although in this study we attempted to quantify a technology partnership, other factors, including the potential of human resources and perceived competencies, were not discussed. Lastly, this study suggests that while technological similarity between partners can lead to positive cooperation outcomes, it can also have negative effects, such as inter-firm conflict over similar patents. This study may be expanded to predict which of the seven derivative patents in 2017 (US10043570, US10049721, US10152271, US10013197, US9997212, US10068664, and US10147467) will emerge as core patents in the future. Identifying the next main path is left as a topic for further research.

Author Contributions

Conceptualization, E.C. and S.Y.S.; methodology, E.C. and S.Y.S.; software, E.C.; validation, E.C. and S.Y.S.; formal analysis, E.C.; investigation, S.Y.S.; resources, E.C.; data curation, E.C.; writing—original draft preparation, E.C.; writing—review and editing, E.C. and S.Y.S.; visualization, E.C.; supervision, S.Y.S.; project administration, S.Y.S.; funding acquisition, S.Y.S. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the Korean government (MSIT), grant number 2020R1A2C2005026.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Data was obtained from the United States Patent and Trademark Office (USPTO), Pitchbook, and Crunchbase.

Acknowledgments

The corresponding author of this study was funded by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIT) [grant number 2020R1A2C2005026].

Conflicts of Interest

The authors declare no conflict of interest.

Appendix A

Table A1. PiM-related patent search terms.
Table A1. PiM-related patent search terms.
Search Terms
(processor-in-memory processing-in-memory in-memory-processing computing-in-memory computation-in-memory in-memory-computing in-memory-computation processor-near-memory processing-near-memory near-memory-processing near-memory-processor processor-near-data processing-near-data near-data-processing near-data-processor processor-in-storage processing-in-storage in-storage-processing computing-in-storage computation-in-storage in-storage-computing in-storage-computation) OR (“intelligent memory” AND (semiconductor process* compute*) AND (semiconductor comput* process*))
Table A2. ASIC-related patent search terms.
Table A2. ASIC-related patent search terms.
Search Terms
(“artificial intelligence*” “machine learning*” “deep learning*” “neural network*” “deep network*” “deep architecture*”) AND (ASIC and chip and accele* and process* and comput* and hardware and (RNN CNN ANN))

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Figure 1. (a) The traditional computing architecture. (b) The PiM-based computing architecture.
Figure 1. (a) The traditional computing architecture. (b) The PiM-based computing architecture.
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Figure 2. Methodological framework.
Figure 2. Methodological framework.
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Figure 3. MPA result of PiM.
Figure 3. MPA result of PiM.
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Table 1. Attributes of the PiM core patent technology.
Table 1. Attributes of the PiM core patent technology.
PatentTitle of InventionApplicantDomainLv 1Lv 2
US
7167890		Multiplier-based processor-in-memory architectures for image and graphics processing2003RF-SUNY
and UR		PUArchi
tecture		Design
US
8234460		Communication between internal and external processors2009Micron TechnologyMemory
Device		Archi
tecture		Control
US
9477636		Memory has internal processors and data communication methods2009Micron TechnologyMemory
Device		Archi
tecture		Interface
US
8964496		Apparatuses and methods for performing comparison operations using sensing circuitry2013Micron TechnologyMemory
Device		Opera
tion		Accumulation
US
8971124		Apparatuses and methods for performing logical operations using sensing circuitry2013Micron TechnologyMemory
Device		Opera
tion		Accumulation
US
9430191		Division operations for memory2013Micron TechnologyMemory
Device		Opera
tion		Division
US
9275701		Apparatuses and methods for performing logical operations using sensing circuitry2014Micron TechnologyMemory
Device		Opera
tion		Accumulation
US
9847110		Apparatuses and methods for storing a data value in multiple columns of an array corresponding to digits of a vector2015Micron TechnologyMemory
Device		Opera
tion		Operation
US
9898253		Division operations on variable-length elements in memory2016Micron TechnologyMemory
Device		Opera
tion		Division
US
9767864		Apparatuses and methods for storing a data value in a sensing circuitry element2016Micron TechnologyMemory
Device		Archi
tecture		Data Paths
US
9899068		Apparatuses and methods for performing logical operations using sensing circuitry2017Micron TechnologyMemory
Device		Archi
tecture		Design
Table 2. Ten candidates for PiM development partnerships with memory device suppliers.
Table 2. Ten candidates for PiM development partnerships with memory device suppliers.
RankASICSimilarity Score *
Weight Case 1 **Weight Case 2 ***
1Intel (US)10391689
2Cambricon Technologies (China)353565
3Samsung Electronics (Korea)326524
4Gyrfalcon Technology (US)205332
5Apple (US)168280
6Graphcore (UK)123197
7Achronix Semiconductor (US)97(10)62
8Qualcomm (US)94(7)154
9GEO Semiconductor (US)86(9)66
10Kneron (US)73(8)120
* Σ (cosine similarity by each patent of firm x recency weight by each patent of firm). ** After 2018: 50%, After 2013: 30%, Before 2012: 20%. *** After 2018: 80%, After 2013: 50%, Before 2012: 10%.
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Chung, E.; Sohn, S.Y. Processing-in-Memory Development Strategy for AI Computing Using Main-Path and Doc2Vec Analyses. Sustainability 2023, 15, 12439. https://doi.org/10.3390/su151612439

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Chung E, Sohn SY. Processing-in-Memory Development Strategy for AI Computing Using Main-Path and Doc2Vec Analyses. Sustainability. 2023; 15(16):12439. https://doi.org/10.3390/su151612439

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Chung, Euiyoung, and So Young Sohn. 2023. "Processing-in-Memory Development Strategy for AI Computing Using Main-Path and Doc2Vec Analyses" Sustainability 15, no. 16: 12439. https://doi.org/10.3390/su151612439

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